LMX2332A [NSC]
PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications; PLLatinum⑩双频率合成射频个人通信
| 型号： | LMX2332A |
| 厂家： | 
National Semiconductor |
| 描述： | PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| 文件： | 总17页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1999
LMX2330A/LMX2331A/LMX2332A
™
PLLatinum Dual Frequency Synthesizer for RF
Personal Communications
The LMX233xA are available in a TSSOP 20-pin surface
mount plastic package.
LMX2330A 2.5 GHz/510 MHz
LMX2331A 2.0 GHz/510 MHz
LMX2332A 1.2 GHz/510 MHz
Features
n 2.7V to 5.5V operation
n Low current consumption
General Description
=
n Selectable powerdown mode: ICC 1 µA typical at 3V
The LMX233xA family of monolithic, integrated dual fre-
quency synthesizers, including prescalers, is to be used as a
local oscillator for RF and first IF of a dual conversion trans-
ceiver. It is fabricated using National’s ABiC IV silicon
BiCMOS process.
n Dual modulus prescaler:
LMX2330A (RF) 32/33 or 64/65
LMX2331A/32A (RF) 64/65 or 128/129
LMX2330A/31A/32A (IF) 8/9 or 16/17
n Selectable charge pump TRI-STATE® mode
The LMX233xA contains dual modulus prescalers. A 64/65
or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz
LMX2330A) can be selected for the RF synthesizer and a
8/9 or a 16/17 prescaler can be selected for the IF synthe-
sizer. LMX233XA, which employs a digital phase locked loop
technique, combined with a high quality reference oscillator
and loop filters, provides the tuning voltages for voltage con-
trolled oscillators to generate very stable low noise RF and
IF local oscillator signals. Serial data is transferred into the
LMX233xA via a three wire interface (Data, Enable, Clock).
Supply voltage can range from 2.7V to 5.5V. The LMX233xA
™
n Selectable FastLock mode
n Small outline, plastic, surface mount TSSOP 0.173"
wide package
Applications
n Portable Wireless Communications (PCS/PCN, cordless)
n Cordless and cellular telephone systems
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
n Other wireless communication systems
family
features
very
low
current
consumption;
LMX2330A — 13 mA at 3V, LMX2331A — 12 mA at 3V,
LMX2332A — 8 mA at 3V.
Functional Block Diagram
DS012331-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
Fastlock , MICROWIRE and PLLatinum are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS012331
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Connection Diagram
Thin Shrink Small Outline Package (TM)
DS012331-2
Order Number LMX2330ATM, LMX2331ATM or LMX2332ATM
NS Package Number MTC20
Pin Description
Pin
No.
1
Pin
I/O
Description
Name
VCC1
—
Power supply voltage input for RF analog and RF digital circuits. Input may range from 2.7V to
5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
2
3
VP1
—
O
Power Supply for RF charge pump. Must be ≥ VCC.
Do RF
Internal charge pump output. For connection to a loop filter for driving the input of an external
VCO.
4
5
6
GND
fIN RF
fIN RF
—
Ground for RF digital circuitry.
I
I
RF prescaler input. Small signal input from the VCO.
RF prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected directly to the ground plane. Capacitor is optional with some loss of
sensitivity.
7
8
GND
—
I
Ground for RF analog circuitry.
OSCin
Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS
or TTL logic gate.
™
9
GND
FoLD
—
O
Ground for IF digital, MICROWIRE , FoLD, and oscillator circuits.
10
Multiplexed output of the RF/IF programmable or reference dividers, RF/IF lock detect signals
and Fastlock mode. CMOS output (see Programmable Modes).
11
12
13
Clock
Data
LE
I
I
I
High impedance CMOS Clock input. Data for the various counters is clocked in on the rising
edge, into the 22-bit shift register.
Binary serial data input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift registers
is loaded into one of the 4 appropriate latches (control bit dependent(.
14
15
GND
fIN IF
—
I
Ground for IF analog circuitry.
IF prescaler complementry input. A bypass capacitor should be placed as close as possible to
this pin and be connected directly to the ground plane. Capacitor is optional with some loss of
sensitivity.
16
17
18
19
fIN IF
GND
Do IF
VP2
I
—
O
IF prescaler input. Small signal input from the VCO.
Ground for IF digital, MICROWIRE, FoLD, and oscillator circuits.
IF charge pump output. For connection to a loop filter for driving the input of an external VCO.
—
Power Supply for IF charge pump. Must be ≥ VCC.
www.national.com
2
(Continued)
Pin Description (Continued)
Pin
No.
20
Pin
I/O
Description
Name
VCC2
—
Power supply voltage input for IF analog, IF digital, MICROWIRE, FoLD, and oscillator circuits.
Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed
as close as possible to this pin and be connected directly to the ground plane.
Block Diagram
DS012331-27
Notes:
The RF prescaler for the LMX2331A/32A is either 64/65 or 128/129, while the prescaler for the LMX2330A is 32/33 or 64/65.
V
1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. V 2 supplies power to the IF prescaler, N-counter, phase detector,
CC
CC
R-counter along with the OSC buffer, MICROWIRE, and F LD. V 1 and V 2 are clamped to each other by diodes and must be run at the same voltage
in CC CC
o
level.
1 and V 2 can be run separately as long as V ≥ V .
CC
V
P
P
P
3
www.national.com
Absolute Maximum Ratings (Notes 1, 2)
Lead Temperature (solder 4 sec.) (TL)
+260˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Power Supply Voltage
Power Supply Voltage
VCC
−0.3V to +6.5V
−0.3V to +6.5V
VCC
2.7V to 5.5V
VCC to +5.5V
VP
VP
Voltage on Any Pin
Operating Temperature (TA)
−40˚C to +85˚C
=
with GND 0V (VI)
−0.3V to VCC+0.3V
−65˚C to +150˚C
Storage Temperature Range (TS)
Electrical Characteristics
=
=
<
<
VCC 3.0V, VP 3.0V; −40˚C TA 85˚C, except as specified
Value
Symbol
Parameter
Conditions
Units
Max
Min
Typ
13
10
12
9
ICC
Power
Supply
Current
LMX2330A RF + IF VCC = 2.7V to 5.5V
LMX2330A RF Only
16.5
13
LMX2331A RF + IF
15.5
LMX2331A RF Only
12
10.5
7
mA
LMX2332A IF + RF
8
LMX2332A RF Only
5
LMX233XA IF Only
3
3.5
25
ICC-PWDN Powerdown Current
1
µA
fIN RF
Operating
Frequency
LMX2330A
LMX2331A
LMX2332A
LMX233XA
0.5
0.2
0.1
45
5
2.5
2.0
1.2
510
40
GHz
fIN IF
fOSC
fφ
Operating Frequency
Oscillator Frequency
MHz
MHz
MHz
dBm
dBm
dBm
VPP
V
Phase Detector Frequency
RF Input Sensitivity
10
PfIN RF
VCC = 3.0V
−15
−10
+4
VCC = 5.0V
+4
PfIN IF
VOSC
VIH
VIL
IF Input Sensitivity
VCC = 2.7V to 5.5V
OSCin
−10
+4
Oscillator Sensitivity
0.5
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Oscillator Input Current
Oscillator Input Current
High-Level Output Voltage
Low-Level Output Voltage
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
*
0.8 VCC
*
0.2 VCC
1.0
V
IIH
VIH = VCC = 5.5V*
VIL = 0V, VCC = 5.5V*
VIH = VCC = 5.5V
VIL = 0V, VCC = 5.5V
IOH = −500 µA
IOL = 500 µA
−1.0
−1.0
µA
µA
µA
µA
V
IIL
1.0
IIH
100
IIL
−100
VOH
VOL
tCS
VCC − 0.4
0.4
V
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
10
50
50
50
50
ns
tCH
ns
tCWH
tCWL
tES
ns
ns
Clock to Load Enable Set Up Time
Load Enable Pulse Width
See Data Input Timing
See Data Input Timing
ns
tEW
ns
*
Clock, Data and LE. Does not include f RF, f IF and OSC
.
IN IN IN
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which
the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Char-
acteristics. The guaranteed specifications apply only for the test conditions listed.
<
Note 2: This device is a high performance RF integrated circuit with an ESD rating 2 keV and is ESD sensitive. Handling and assembly of this device should only
be done at ESD protected workstations.
www.national.com
4
Charge Pump Characteristics
=
=
<
<
VCC 3.0V, VP 3.0V; −40˚C TA 85˚C, except as specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
Max
ID -SOURCE
Charge Pump Output Current
VD = VP/2, ICP = HIGH**
−4.5
mA
mA
mA
mA
o
o
o
ID -SINK
VD = VP/2, ICP = HIGH**
4.5
o
o
o
ID -SOURCE
VD = VP/2, ICP = LOW**
−1.125
1.125
o
o
o
ID -SINK
VD = VP/2, ICP = LOW**
o o
o
ID -TRI
Charge Pump TRI-STATE
Current
0.5V ≤ VD ≤ VP − 0.5V
o
o
−2.5
2.5
10
15
nA
%
%
%
<
<
−40˚c TA 85˚C
ID -SINK vs
CP Sink vs
Source Mismatch (Note 4)
VD = VP/2
o
o
3
ID -SOURCE
TA = 25˚C
o
ID vs VD
CP Current vs Voltage
(Note 3)
0.5V ≤ VD ≤ VP − 0.5V
o
o
o
10
10
=
TA 25˚C
ID vs TA
CP Current vs Temperature
(Note 5)
VD = VP/2
o
o
<
<
−40˚C TA 85˚C
**
See PROGRAMMABLE MODES for I
CPo
description.
Note 3: See charge pump current specification definitions below.
Note 4: See charge pump current specification definitions below.
Note 5: See charge pump current specification definitions below.
5
www.national.com
Charge Pump Current Specification Definitions
DS012331-25
=
=
=
=
=
I1 CP sink current at V
V
V
∆V
− ∆V
/2
Do
Do
Do
P
P
I2 CP sink current at V
=
I3 CP sink current at V
=
=
=
=
=
=
I4 CP source current at V
V
V
∆V
− ∆V
/2
Do
Do
Do
P
P
I5 CP source current at V
I6 CP source current at V
=
∆V Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
and ground. Typical values are between 0.5V and 1.0V.
CC
=
=
Charge Pump Output Current magnitude variation vs Voltage
3. I vs V
Do Do
1
1
[1⁄
2
{|I1| − |I3|}]/[ ⁄
2
{|I1| + |I3|}] 100
%
and [1⁄
Charge Pump Output Current Sink vs Source Mismatch
2
{|I4| − |I6|}]/[ ⁄
2
{|I4| + |I6|}] 100
%
*
*
*
*
*
*
=
=
4. I
vs I
Do-sink
Do-source
[|I2| − |I5|]/[1⁄
2
{|I2| + |I5|}] 100
%
*
*
=
=
5. I vs T
Do
Charge Pump Output Current magnitude variation vs Temperature
A
@
@
@
*
%
@
@
@
*
[|I2 temp| − |I2 25˚C|]/|I2 25˚C| 100
and [|I5 temp| − |I5 25˚C|]/|I5 25˚C| 100
%
RF Sensitivity Test Block Diagram
DS012331-28
=
=
=
Note: N 10,000 R 50 P 64
Note: Sensitivity limit is reached when the error of the divided RF output, F LD, is ≥ 1 Hz.
o
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6
Typical Performance Characteristics
ICC vs VCC
LMX2330A
ICC vs VCC
LMX2331A
DS012331-31
DS012331-32
ICC vs VCC
LMX2332A
IDoTRI-STATE
vs Do Voltage
DS012331-4
DS012331-33
Charge Pump Current vs Do Voltage
Charge Pump Current vs Do Voltage
=
ICP HIGH
=
ICP LOW
DS012331-34
DS012331-35
7
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Typical Performance Characteristics (Continued)
Charge Pump Current Variation
(See Note 3 under Charge Pump Current Specification
Definitions)
Sink vs Source Mismatch
(See Note 4 under Charge Pump Current Specification
Definitions)
DS012331-36
DS012331-37
RF Input Impedance
IF Input Impedance
= =
VCC 2.7V to 5.5V, fIN 10 MHz to 1000 MHz
=
=
VCC 2.7V to 5.5V, fIN 50 MHz to 3 GHz
DS012331-38
DS012331-39
=
=
=
= = =
Marker 1 100 MHz, Real 589, Imag. −209
Marker 1 1 GHz, Real 101, Imag. −144
=
=
=
= = =
Marker 2 200 MHz, Real 440, Imag. −286
Marker 2 2 GHz, Real 37, Imag. −54
=
=
=
= = =
Marker 3 300 MHz, Real 326, Imag. −287
Marker 3 3 GHz, Real 22, Imag. −2
=
=
=
= = =
Marker 4 500 MHz, Real 202, Imag. −234
Marker 4 500 MHz, Real 209, Imag. −232
www.national.com
8
Typical Performance Characteristics (Continued)
LMX2330A RF Sensitivity vs Frequency
LMX2331A RF Sensitivity vs Frequency
DS012331-40
DS012331-41
LMX2332A RF Sensitivity vs Frequency
IF Input Sensitivity vs Frequency
DS012331-42
DS012331-43
Oscillator Input Sensitivity vs Frequency
DS012331-44
9
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Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (in-
termediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The
data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Con-
trol Bits. The DATA is transferred into the counters as follows:
Control Bits
DATA Location
C1
0
C2
0
IF R Counter
RF R Counter
IF N Counter
RF N Counter
0
1
1
0
1
1
DS012331-1
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
DS012331-14
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
R
R
R
R
R
R
R
9
0
0
R
8
0
0
R
7
0
0
R
6
0
0
R
5
0
0
R
4
0
0
R
3
0
1
R
2
1
0
R
1
1
0
Ratio 15 14 13 12 11 10
3
4
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
•
•
•
•
•
•
•
•
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
www.national.com
10
Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care
bits.
DS012331-15
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
RF
IF
Divide
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
N
7
N
6
N
5
N
4
N
3
N
2
N
1
Ratio
Ratio
A
0
1
A
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
X
X
•
X
X
•
X
X
•
0
0
•
0
0
•
0
0
•
0
1
•
•
•
127
1
1
1
1
1
1
1
15
X
X
X
1
1
1
1
=
DON’T CARE condition
Note: Divide ratio: 0 to 127
B ≥ A
X
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
N
N
N
N
N
N
N
N
N
N
9
N
8
Ratio
18
17
16
15
14
13
12
11
10
B
3
4
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B ≥ A
PULSE SWALLOW FUNCTION
=
fVCO [(P x B) + A] x fOSC/R
fVCO
B:
:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
Preset divide ratio of binary 7-bit swallow counter
A:
(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B)
fOSC
R:
:
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
=
Preset modulus of dual moduIus prescaler (for IF ; P 8 or 16;
P:
=
=
LMX2331A/32A: P 64 or 128)
for RF ; LMX2330A: P 32 or 64
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump
TRI-STATE and the output of the FoLD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The pro-
grammable modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Table 2 and
Table 3.
11
www.national.com
Functional Description (Continued)
TABLE 1. Programmable Modes
C1
C2
R16
R17
R18
R19
R20
IF Phase
Detector Polarity
IF Do
TRI-STATE
0
0
IF ICP
IF LD
IF Fo
o
RF Phase
Detector Polarity
RF Do
TRI-STATE
0
1
RF ICP
RF LD
RF Fo
o
C1
1
C2
0
N19
N20
IF Prescaler
RF Prescaler
Pwdn IF
Pwdn RF
1
1
TABLE 2. Mode Select Truth Table
ICP
IF
2330A RF
Prescaler
2331A/32A RF
Prescaler
Pwdn
o
Phase Detector Polarity
Negative
Do TRI-STATE
(Note 6) Prescaler
(Note 7)
Normal
Operation
Pwrd
Up
0
LOW
HIGH
8/9
32/33
64/65
64/65
Pwrd
Dn
1
Positive
TRI-STATE
16/17
128/129
=
Note 6: The I
LOW current state 1/4 x I
HIGH current.
CPo
CPo
Note 7: Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective f inputs
IN
(to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program mode is
loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter functionality does not become disabled until
both IF and RF powerdown bits are activated. The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown
modes.
TABLE 3. The FoLD (Pin 10) Output Truth Table
RF R[19]
IF R[19]
RF R[20]
IF R[20]
Fo Output State
Disabled (Note 8)
(RF LD)
(IF LD)
(RF Fo)
(IF Fo)
0
0
1
1
X
X
X
X
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
1
IF Lock Detect (Note 9)
RF Lock Detect (Note 9)
RF/IF Lock Detect (Note 9)
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
Fastlock (Note 10)
For Internal Use Only
For Internal Use Only
Counter Reset (Note 11)
=
X
don’t care condition
Note 8: When the F LD output is disabled, it is actively pulled to a low logic state.
o
Note 9: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 10: The Fastlock mode utilizes the F LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
o
occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
Note 11: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes counting in “close”
alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated the R counter is also forced to Reset, allowing smooth ac-
quisition upon powering up.
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12
Functional Description (Continued)
PHASE DETECTOR POLARITY
Depending upon VCO characteristics, R16 bit should be set
accordingly: (see figure right)
VCO Characteristics
When VCO characteristics are positive like (1), R16 should
be set HIGH;
When VCO characteristics are negative like (2), R16 should
be set LOW.
DS012331-16
SERIAL DATA INPUT TIMING
DS012331-17
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V /2. The test waveform has an edge rate of 0.6V/ns with
CC
=
=
5.5V.
@
@
V
CC
amplitudes of 2.2V
V
2.7V and 2.6V
CC
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
DS012331-18
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the D pin when the loop is locked.
o
=
R16 HIGH
13
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Typical Application Example
DS012331-19
Operational Notes:
*
VCO is assumed AC coupled.
**
RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to
200Ω depending on the VCO power level. fIN RF impedance ranges from 40Ω to 100Ω. fIN IF impedances are higher.
***
50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a
CMOS clock is used and no terminating resistor is required. OSCin may be AC or DC coupled. AC coupling is recom-
mended because the input circuit provides its own bias. (See Figure below)
****
Adding RC filters to the VCC line is recommended to reduce loop-to-loop noise coupling.
DS012331-20
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board
layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
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14
Application Information
A block diagram of the basic phase locked loop is shown in Figure 1.
DS012331-21
FIGURE 1. Basic Charge Pump Phase Locked Loop
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (KVCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3, while
the complex impedance of the filter is given in Equation (2).
(5)
From Equation (3) we can see that the phase term will be de-
pendent on the single pole and zero such that the phase
margin is determined in Equation (6).
−1
φ(ω) tan (ω • T2) − tan−1 (ω • T1) + 180˚
(6)
=
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
φp shows the amount of phase margin that exists at the point
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison fre-
quency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase — just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
of Figure 4 over to a different cutoff frequency, illustrated by
the dotted line, without affecting the relative open loop gain
and phase relationships. To maintain the same gain/phase
relationship at twice the original cutoff frequency, other terms
in the gain and phase Equations (5), (6) will have to compen-
sate by the corresponding “1/w” or “1/w2” factor. Examination
of Equations (3), (4), (6) indicates the damping resistor vari-
able R2 could be chosen to compensate the “w”’ terms for
the phase margin. This implies that another resistor of equal
value to R2 will need to be switched in parallel with R2 during
the initial lock period. We must also ensure that the magni-
DS012331-23
FIGURE 2. PLL Linear Model
DS012331-22
FIGURE 3. Passive Loop Filter
(1)
(2)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
=
tude of the open loop gain, H(s)G(s) is equal to zero at wp’
(3)
2wp. Kvco, Kφ, N, or the net product of these terms can be
changed by a factor of 4, to counteract the w2 term present
in the denominator of Equations (3), (4). The Kφ term was
chosen to complete the transformation because it can
readily be switch between 1X and 4X values. This is accom-
plished by increasing the charge pump output current from 1
mA in the standard mode to 4 mA in Fastlock.
and
=
T2 R2 • C2
(4)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants Kφ, KVCO, and N.
15
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Application Information (Continued)
DS012331-29
FIGURE 4. Open Loop Response Bode Plot
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233xA PLL is shown in Figure 5.
When a new frequency is loaded, and the RF Icpo bit is set
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter compo-
nent values for the normal steady state considerations. The
device configuration ensures that as long as a second iden-
tical damping resistor is wired in appropriately, the loop will
lock faster without any additional stability considerations to
account for. Once locked on the correct frequency, the user
can return the PLL to standard low noise operation by send-
ing a MICROWIRE instruction with the RF Icpo bit set low.
This transition does not affect the charge on the loop filter
capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be-
tween Fastlock and standard mode.
DS012331-30
FIGURE 5. Fastlock PLL Architecture
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16
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2330ATM, LMX2331ATM or LMX2332ATM
*
For Tape and Reel (2500 units per reel)
Order Number LMX2330ATMX, LMX2331ATMX or LMX2332ATMX
NS Package Number MTC20
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相关型号：
LMX2332ATMX
IC PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20, 0.173 INCH, PLASTIC, TSSOP-20, PLL or Frequency Synthesis Circuit
NSC
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