LMX2531LQ1312E [NSC]
High Performance Frequency Synthesizer System with Integrated VCO; 集成VCO的高性能频率合成器系统
| 型号： | LMX2531LQ1312E |
| 厂家： | 
National Semiconductor |
| 描述： | High Performance Frequency Synthesizer System with Integrated VCO |
| 文件： | 总36页 (文件大小：701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 23, 2009
LMX2531
High Performance Frequency Synthesizer System with
Integrated VCO
General Description
Features
The LMX2531 is a low power, high performance frequency
synthesizer system which includes a fully integrated delta-
sigma PLL and VCO with fully integrated tank circuit. The third
and fourth poles are also integrated and also adjustable. Also
included are integrated ultra-low noise and high precision
LDOs for the PLL and VCO which give higher supply noise
immunity and also more consistent performance. When com-
bined with a high quality reference oscillator, the LMX2531
generates very stable, low noise local oscillator signals for up
and down conversion in wireless communication devices.
The LMX2531 is a monolithic integrated circuit, fabricated in
an advanced BiCMOS process. There are several different
versions of this product in order to accommodate different
frequency bands.
Multiple Frequency Options Available
■
See Selection Guide Below
—
—
Frequencies from: 553 MHz - 3132 MHz
PLL Features
■
Fractional-N Delta Sigma Modulator Order
programmable up to 4th order
—
FastLock/Cycle Slip Reduction with Timeout Counter
Partially integrated, adjustable Loop Filter
Very low phase noise and spurs
—
—
—
VCO Features
■
■
Integrated tank inductor
Low phase noise
—
—
Other Features
Device programming is facilitated using
MICROWIRE Interface that can operate down to 1.8 volts.
a three-wire
2.8 V to 3.2 V Operation
Low Power-Down Current
1.8 V MICROWIRE Support
Package: 36 Lead LLP
—
—
—
—
Supply voltage range is 2.8 to 3.2 Volts. The LMX2531 is
available in a 36 pin 6x6x0.8 mm Lead-Free Leadless Lead-
frame Package (LLP).
Part
Low Band
High Band
Target Applications
LMX2531LQ1146E 553 - 592 MHz 1106 - 1184 MHz
LMX2531LQ1226E 592 - 634 MHz 1184 - 1268 MHz
LMX2531LQ1312E 634 - 680 MHz 1268 - 1360 MHz
LMX2531LQ1415E 680 - 735 MHz 1360 - 1470 MHz
LMX2531LQ1515E 725 - 790 MHz 1450 - 1580 MHz
LMX2531LQ1570E 765 - 818 MHz 1530 - 1636 MHz
LMX2531LQ1650E 795 - 850 MHz 1590 - 1700 MHz
LMX2531LQ1700E 831 - 885 MHz 1662 - 1770 MHz
3G Cellular Base Stations (WCDMA, TD-
■
SCDMA,CDMA2000)
2G Cellular Base Stations (GSM/GPRS, EDGE,
CDMA1xRTT)
■
Wireless LAN
■
■
■
■
■
■
■
■
Broadband Wireless Access
Satellite Communications
Wireless Radio
Automotive
CATV Equipment
LMX2531LQ1742
880 - 933 MHz 1760 - 1866 MHz
Instrumentation and Test Equipment
LMX2531LQ1778E 863 - 920 MHz 1726 - 1840 MHz
LMX2531LQ1910E 917 - 1014 MHz 1834 - 2028 MHz
LMX2531LQ2080E 952 - 1137 MHz 1904 - 2274 MHz
LMX2531LQ2265E 1089 - 1200 MHz 2178 - 2400 MHz
LMX2531LQ2570E 1168 - 1395 MHz 2336 - 2790 MHz
LMX2531LQ2820E 1355 - 1462 MHz 2710 - 2925 MHz
LMX2531LQ3010E 1455 - 1566 MHz 2910 - 3132 MHz
RFID Readers
© 2009 National Semiconductor Corporation
201011
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Functional Block Diagram
20101101
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2
Connection Diagrams
36-Pin LLP (LQ) Package, D Version
(LMX2531LQ1146E/1226E/1312E/1415E/1515E/2820E/3010E)
20101104
36-Pin LLP (LQ) Package, A Version
(All Other Versions)
20101102
3
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Pin Descriptions
Pin #
Pin Name
VccDIG
GND
I/O
Description
Power Supply for digital LDO circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be
placed as close as possible to this pin and ground.
1
-
-
3
Ground
2,4,5,7,
12, 13,
29, 35
NC
-
No Connect.
6
VregBUF
DATA
-
I
Internally regulated voltage for the VCO buffer circuitry. Connect to ground with a capacitor.
MICROWIRE serial data input. High impedance CMOS input. This pin must not exceed 2.75V. Data is
clocked in MSB first. The last bits clocked in form the control or register select bits.
8
MICROWIRE clock input. High impedance CMOS input. This pin must not exceed 2.75V. Data is clocked
into the shift register on the rising edge.
9
CLK
LE
I
I
MICROWIRE Latch Enable input. High impedance CMOS input. This pin must not exceed 2.75V. Data
stored in the shift register is loaded into the selected latch register when LE goes HIGH.
10
Chip Enable Input. High impedance CMOS input. This pin must not exceed 2.75V. When CE is brought
high the LMX2531 is powered up corresponding to the internal power control bits. Although the part can
be programmed when powered down, it is still necessary to reprogram the R0 register to get the part to
re-lock.
11
CE
I
14, 15
16
NC
-
-
No Connect. Do NOT ground.
Power Supply for VCO regulator circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should
be placed as close as possible to this pin and ground.
VccVCO
Internally regulated voltage for VCO circuitry. Not intended to drive an external load. Connect to ground
with a capacitor and some series resistance.
17
18
VregVCO
VrefVCO
-
-
Internal reference voltage for VCO LDO. Not intended to drive an external load. Connect to ground with
a capacitor.
19
20
21
GND
GND
Fout
-
-
Ground for the VCO circuitry.
Ground for the VCO Output Buffer circuitry.
Buffered RF Output for the VCO.
O
Power Supply for the VCO Buffer circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should
be placed as close as possible to this pin and ground.
22
23
VccBUF
Vtune
-
I
Tuning voltage input for the VCO. For connection to the CPout Pin through an external passive loop
filter.
24
25
CPout
FLout
O
O
Charge pump output for PLL. For connection to Vtune through an external passive loop filter.
An open drain NMOS output which is used for FastLock or a general purpose output.
Internally regulated voltage for PLL charge pump. Not intended to drive an external load. Connect to
ground with a capacitor.
26
27
28
VregPLL1
VccPLL
-
-
-
Power Supply for the PLL. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as
close as possible to this pin and ground.
Internally regulated voltage for RF digital circuitry. Not intended to drive an external load. Connect to
ground with a capacitor.
VregPLL2
30
31
Ftest/LD
OSCin
O
I
Multiplexed CMOS output. Typically used to monitor PLL lock condition.
Oscillator input.
Oscillator complimentary input. When a single ended source is used, then a bypass capacitor should be
placed as close as possible to this pin and be connected to ground.
32
OSCin*
I
33
34
36
Test
GND
O
-
This pin is for test purposes and should be grounded for normal operation.
Ground
VregDIG
-
Internally regulated voltage for LDO digital circuitry.
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4
Connection Diagram
20101111
Pin(s)
Application Information
These pins are inputs to voltage regulators. Because the LMX2531 contains internal regulators, the power supply noise
rejection is very good and capacitors at this pin are not critical. An RC filter can be used to reduce supply noise, but if the
capacitor is too large and is placed too close to these pins, they can sometimes cause phase noise degradation in the 100
- 300 kHz offset range. Recommended values are from open to 1 μF. The series resistors serve to filter power supply noise
and isolate these pins from large capacitances.
VccDIG
VccVCO
VccBUF
VccPLL
VregDIG There is not really any reason to use any other values than the recommended value of 10 nF
If the VrefVCO capacitor is changed, it is recommended to keep this capacitor between 1/100 and 1/1000 of the value of
the VregVCO capacitor.
VrefVCO
Because this pin is the output of a regulator, there are stability concerns if there is not sufficient series resistance. For
ceramic capacitors, the ESR (Equivalent Series Resistance) is too low, and it is recommended that a series resistance of
VregVCO
1 - 3.3Ω is necessary. If there is insufficient ESR, then there may be degradation in the phase noise, especially in the 100
- 300 kHz offset. Recommended values are from 1 μF to 10 μF.
The choice of the capacitor value at this pin involves a trade-off between integer spurs and phase noise in the 100 - 300
kHz offset range. Using a series resistor of about 220 mΩ in series with a capacitance that has an impedance of about 150
mΩ at the phase detector frequency seems to give an optimal trade-off. For instance, if the phase detector frequency is
2.5 MHz, then make this series capacitor 470 nF. If the phase detector frequency is 10 MHz, make this capacitance about
VregPLL1
VregPLL2
100 nF.
CLK
DATA
LE
Since the maximum voltage on these pins is less than the minimum Vcc voltage, level shifting may be required if the output
voltage of the microcontroller is too high. This can be accomplished with a resistive divider.
5
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Pin(s)
Application Information
As with the CLK, DATA, and LE pins, level shifting may be required if the output voltage of the microcontroller is too high.
A resistive divider or a series diode are two ways to accomplish this. The diode has the advantage that no current flows
through it when the chip is powered down.
CE
Ftest/LD It is an option to use the lock detect information from this pin.
This is the high frequency output. This needs to be AC coupled, and matching may also be required. The value of the DC
blocking capacitor may be changed, depending on the output frequency.
Fout
CPout
Vtune
In most cases, it is sufficient to short these together, although there always the option of adding additional poles. C1_LF,
C2_LF, and R2_LF are used in conjunction with the internal loop filter to make a fourth order loop filter.
This is the fastlock resistor, which can be useful in many cases, since the spurs are often better with low charge pump
currents, and the internal loop filter can be adjusted during fastlock.
R2pLF
OSCin
This is the reference oscillator input pin. It needs to be AC coupled.
OSCin* If the device is being driven single-ended, this pin needs to be shunted to ground with a capacitor.
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6
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter
Symbol
Ratings
Units
VCC
-0.3 to 3.5
(VccDIG, VccVCO,
VccBUF, VccPLL)
Power Supply Voltage
V
All other pins (Except
Ground)
-0.3 to 3.0
Storage Temperature
Range
TSTG
TL
-65 to 150
+ 260
°C
°C
Lead Temperature (solder 4 sec.)
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
3.0
Max
Units
Power Supply Voltage
(VccDig, VccVCO, VccBUF)
Vcc
2.8
3.2
V
V
Serial Interface and Power Control
Voltage
Vi
0
2.75
+85
Ambient Temperature
(Note 5)
TA
-40
°C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only to the test conditions listed.
7
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Electrical Characteristics (VCC = 3.0 V, -40°C ≤ TA ≤ 85 °C; except as specified.)
Symbol
Parameter
Conditions
Min
Typ Max
Units
Current Consumption
LMX2531LQ2265E
/2570E
38
44
Divider Disabled
Divider Enabled
LMX2531LQ2820E
/3010E
38
34
41
46
41
49
All Other Options
Power Supply Current Power
Supply Current
ICC
mA
µA
LMX2531LQ2265E
/2570E
LMX2531LQ2820E
/3010E
44
52
46
All Other Options
37
7
ICCPD
Power Down Current
CE = 0 V, Part Initialized
Oscillator
IIHOSC
IILOSC
fOSCin
VIH = 2.75 V
VIL = 0
Oscillator Input High Current
Oscillator Input Low Current
Frequency Range
100
µA
µA
-100
5
(Note 2)
80
MHz
Vpp
vOSCin
Oscillator Sensitivity
0.5
2.0
PLL
fPD
Phase Detector Frequency
32
MHz
µA
ICP = 0
ICP = 1
90
180
360
1440
2
µA
Charge Pump
Output Current Magnitude
ICPout
ICP = 3
µA
ICP = 15
µA
ICPoutTRI
ICPoutMM
0.4 V < VCPout < 2.0 V
CP TRI-STATE Current
10
8
nA
VCPout = 1.2 V
TA = 25°C
Charge Pump
Sink vs. Source Mismatch
2
%
Charge Pump
Current vs. CP Voltage
Variation
0.4 V < VCPout < 2.0 V
TA = 25°C
ICPout
V
T
4
%
CP Current vs. Temperature
Variation
ICPout
VCPout = 1.2 V
8
%
Normalized PLL 1/f Noise
LNPLL_flicker(10 kHz)
(Note 3)
ICP = 1X Charge Pump Gain
ICP = 16X Charge Pump Gain
ICP = 1X Charge Pump Gain
ICP = 16X Charge Pump Gain
-94
dBc/Hz
-104
-202
-212
LN(f)
Normalized PLL Noise Floor
LNPLL_flat
dBc/Hz
(Note 4)
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Symbol
Parameter
Conditions
VCO Frequencies
LMX2531LQ1146E
LMX2531LQ1226E
LMX2531LQ1312E
LMX2531LQ1415E
LMX2531LQ1515E
LMX2531LQ1570E
LMX2531LQ1650E
LMX2531LQ1700E
LMX2531LQ1742
LMX2531LQ1778E
LMX2531LQ1910E
LMX2531LQ2080E
LMX2531LQ2265E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
Min
Typ Max
Units
1106
1184
1268
1360
1450
1530
1590
1662
1760
1726
1834
1904
2178
2336
2710
2910
1184
1268
1360
1470
1580
1636
1700
1770
1866
1840
2028
2274
2400
2790
2925
3132
Operating Frequency Range
(All options have a frequency
divider, this applies before the
divider. The frequency after the
divider is half of what is shown)
fFout
MHz
9
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Symbol
Parameter
Conditions
Other VCO Specifications
LMX2531LQ1742
Min
Typ Max
Units
65
90
Maximum Allowable
Temperature Drift for
Continuous Lock
(Note 5)
LMX2531LQ1570E/1650E/1146E/1226/1312E/1415E/
1515E
ΔTCL
°C
LMX2531LQ1700E/1778E/1910E/2080E/2265E/
2570E/2820E/3010E
125
LMX2531LQ1146E
LMX2531LQ1226E
LMX2531LQ1312E
LMX2531LQ1415E
LMX2531LQ1515E
LMX2531LQ1570E
LMX2531LQ1650E
1
1
4.0
3.5
3.5
3.0
2.5
4.5
4.5
3.5
3.5
3.5
3.5
3.5
3.5
3.0
2.5
1.5
2.0
2.0
1.5
0.5
0.5
3.0
3.0
3.0
3.0
3.0
3.0
2.5
2.5
1.5
0
7
7
1
7
0
6
-1
2
5
8
2
8
LMX2531LQ1700E
Divider Disabled
1
7
dBm
LMX2531LQ1742
1
7
LMX2531LQ1778E
LMX2531LQ1910E
LMX2531LQ2080E
LMX2531LQ2265E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
LMX2531LQ1146E
LMX2531LQ1226E
LMX2531LQ1312E
LMX2531LQ1415E
LMX2531LQ1515E
LMX2531LQ1570E
LMX2531LQ1650E
1
7
1
7
1
7
1
7
0
6
-0.5
-1.5
-1
-1
-1
-2
-2
1
5.5
4.5
5
Output Power to a 50 Ω Load
(Applies across entire tuning
range.)
pFout
5
4
3
3
6
1
6
LMX2531LQ1700E
Divider Enabled
1
6
dBm
LMX2531LQ1742
1
6
LMX2531LQ1778E
LMX2531LQ1910E
LMX2531LQ2080E
LMX2531LQ2265E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
1
6
1
6
0
5
0
5
-1
-2.5
-3
4
2.5
2
-0.5
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Symbol
Parameter
Conditions
Min
Typ Max
Units
2.5
-5.5
LMX2531LQ1146E
LMX2531LQ1226E
LMX2531LQ1312E
3-6
3-6
3.5
-6.5
LMX2531LQ1415E
Fine Tuning Sensitivity
(When a range is displayed in
the typical column, indicates the
lower sensitivity is typical at the
lower end of the tuning range,
and the higher tuning sensitivity
is typical at the higher end of the
tuning range.)
LMX2531LQ1515E
LMX2531LQ1570E
LMX2531LQ1650E
LMX2531LQ1700E
LMX2531LQ1742
LMX2531LQ1778E
LMX2531LQ1910E
LMX2531LQ2080E
LMX2531LQ2265E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
4-7
4-7
4-7
KVtune
MHz/V
6-10
4-7
6-10
8-14
9-20
10-16
10-23
12-28
13-29
LMX2531LQ1146E
/1226E/1312E
/1415E/1515E
-35
-25
Divider
Disabled
LMX2531LQ2820E
/3010E
-40
-30
All Other Options
-25
-20
2nd Harmonic
50 Ω Load
LMX2531LQ1146E
/1226E/1312E
-30
/1415E/1515E
Divider
Enabled
LMX2531LQ2820E
/3010E
-30
-20
-35
-15
-15
-30
Harmonic Suppression
(Applies Across Entire Tuning
Range)
All Other Options
HSFout
dBc
LMX2531LQ1146E
/1226E/1312E
Divider
Disabled
LMX2531LQ2820E
/3010E
-50
-40
All Other Options
-35
-15
3rd Harmonic
LMX2531LQ1146E
/1226E/1312E
50 Ω Load
-20
/1570E/1650E
Divider
Enabled
LMX2531LQ2820E
/3010E
-40
-20
-20
All Other Options
-25
PUSHFout
PULLFout
ZFout
Creg = 0.1uF, VDD ± 100mV, Open Loop
VSWR = 2:1, Open Loop
Frequency Pushing
Frequency Pulling
Output Impedance
300
kHz/V
kHz
Ω
±600
50
11
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Symbol
Parameter
Conditions
Min
Typ Max
Units
VCO Phase Noise (Note 6)
10 kHz Offset
-96
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
-121
-142
-156
-101
-126
-147
-156
-95
fFout = 1146 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1146E)
L(f)Fout
dBc/Hz
fFout = 573 MHz
DIV2 = 1
-121
-142
-155
-101
-126
-147
-155
-95
fFout = 1226 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1226E)
L(f)Fout
L(f)Fout
L(f)Fout
L(f)Fout
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fFout = 613 MHz
DIV2 = 1
-121
-140
-154
-101
-126
-146
-154
-95
fFout = 1314 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1312E)
fFout = 657 MHz
DIV2 = 1
-121
-141
-154
-100
-126
-146
-154
-96
fFout = 1415 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1415E)
fFout = 707.5 MHz
DIV2 = 1
-122
-142
-153
-99
fFout = 1515 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1515E)
-125
-145
-154
-93
fFout = 757.5 MHz
DIV2 = 1
-118
-140
-154
-99
fFout = 1583 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1570E)
L(f)Fout
-122
-144
-155
fFout = 791.5 MHz
DIV2 = 1
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Symbol
Parameter
Conditions
10 kHz Offset
Min
Typ Max
-93
Units
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
-118
-140
-154
-99
fFout = 1645 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1650E)
L(f)Fout
dBc/Hz
-122
-144
-155
-92
fFout = 822.5 MHz
DIV2 = 1
-117
-139
-153
-98
fFout = 1716 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1700E)
L(f)Fout
L(f)Fout
L(f)Fout
L(f)Fout
L(f)Fout
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-122
-144
-154
-92
fFout = 858 MHz
DIV2 = 1
-117
-140
-152
-99
fFout= 1813 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1742)
-122
-143
-152
-92
fFout = 906.5 MHz
DIV2 = 1
-117
-139
-152
-97
fFout = 1783 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1778E)
-122
-144
-154
-89
fFout = 891.5 MHz
DIV2 = 1
-115
-138
-151
-95
fFout = 1931 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ1910E)
-121
-143
-155
-87
fFout = 965.5 MHz
DIV2 = 1
-113
-136
-150
-93
fFout = 2089 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ2080E)
-119
-142
-154
fFout = 1044.5 MHz
DIV2 = 1
13
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Symbol
Parameter
Conditions
10 kHz Offset
Min
Typ Max
-88
Units
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
5 MHz Offset
-113
-136
-150
-94
fFout = 2264 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ2265E)
L(f)Fout
dBc/Hz
-118
-141
-154
-86
fFout = 1132 MHz
DIV2 = 1
-112
-135
-149
-91
fFout = 2563 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ2570E)
L(f)Fout
L(f)Fout
L(f)Fout
dBc/Hz
dBc/Hz
dBc/Hz
-117
-139
-152
-84
fFout = 1281.5 MHz
DIV2 = 1
-111
-133
-148
-90
fFout = 2818 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ2820E)
-117
-138
-150
-83
fFout = 1409 MHz
DIV2 = 1
-110
-132
-147
-88
fFout = 3021 MHz
DIV2 = 0
Phase Noise
(LMX2531LQ3010E)
-116
-137
-148
fFout = 1510.5 MHz
DIV2 = 1
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14
Symbol
Parameter
Conditions
Min
Typ Max
Units
Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout)
VIH
VIL
IIH
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
High-Level Output Voltage
Low-Level Output Voltage
1.6
2.75
V
V
0.4
3.0
VIH = 1.75
VIL = 0 V
-3.0
-3.0
2.0
µA
µA
V
IIL
3.0
VOH
VOL
IOH = 500 µA
2.65
IOL = -500 µA
0.0
0.4
V
MICROWIRE Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
tCS
tCH
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
25
20
25
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
tCWH
tCWL
tES
Clock Pulse Width Low
Clock to Enable Set Up Time
Enable to Clock Set Up Time
Enable Pulse Width High
tCES
tEWH
Note 2: There are program bits that need to be set based on the OSCin frequency. Refer to the following sections: 2.7.8 XTLSEL[2:0] -- Crystal Select, 2.8.1
XTLDIV[1:0] -- Division Ratio for the Crystal Frequency, 2.8.2 XTLMAN[11:0] -- Manual Crystal Mode, 2.9.1 XTLMAN2 -- MANUAL CRYSTAL MODE SECOND
ADJUSTMENT, and2.9.2 LOCKMODE -- FREQUENCY CALIBRATION MODE. Not all bit settings can be used for all frequency choices of OSCin. For instance,
automatic modes described in 2.7.8 XTLSEL[2:0] -- Crystal Select do not work below 8 MHz.
Note 3: One of the specifications for modeling PLL in-band phase noise is the PLL 1/f noise normalized to 1 GHz carrier frequency and 10 kHz offset, LPLL_flicker
(10 kHz). From this normalized index of PLL 1/f noise, the PLL 1/f noise can be calculated for any carrier and offset frequency as:
LNPLL_flicker(f) = LPLL_flicker(10 kHz) - 10·log(10 kHz / f) + 20·log( Fout / 1 GHz ). Flicker noise can dominate at low offsets from the carrier and has a 10 dB/decade
slope and improves with higher charge pump currents and at higher offset frequencies . To accurately measure LPLL_flicker(10 kHz) it is important to use a high
phase detector frequency and a clean reference to make it such that this measurement is on the 10 dB/decade slope close to the carrier. LPLL_flicker(f) can be
masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker
(f) / 10 )
(f) and LPLL_flat. In other words,LPLL(f) = 10·log(10(LNPLL_flat / 10 ) + 10(LNPLL_flicker
Note 4: A specification used for modeling PLL in-band phase noise floor is the Normalized PLL noise floor, LNPLL_flat, and is defined as:
LNPLL_flat = L(f) – 20·log(N) – 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of the synthesizer.
LPLL_flat contributes to the total noise, L(f). To measure LPLL_flat the offset frequency must be chosen sufficiently smaller then the loop bandwidth of the PLL, and
yet large enough to avoid a substantial noise contribution from the reference and PLL flicker noise. LPLL_flat can be masked by the reference oscillator performance
if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat. In other
(f) / 10 )
words,LPLL(f) = 10·log(10(LNPLL_flat / 10 ) + 10(LNPLL_flicker
Note 5: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency
calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for
continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed
at, the temperature can never drift outside the frequency range of -40°C ≤TA≤ 85°C without violating specifications.
Note 6: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The maximum limits apply
only at center frequency and over temperature, assuming that the part is reloaded at each test frequency. Over frequency, the phase noise can vary 1 to 2 dB,
with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies 1 to 2 dB, assuming the part is
reloaded.
15
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Serial Data Timing Diagram
20101103
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is
sent from the shift registers to an actual counter. A slew rate of at least 30 V/μs is recommended for these signals. After the
programming is complete, the CLK, DATA, and LE signals should be returned to a low state. Although it is strongly recommended
to keep LE low after programming, LE can be kept high if bit R5[23] is changed to 0 (from its default value of 1). If this bit is changed,
then the operation of the part is not guaranteed because it is not tested under these conditions. If the CLK and DATA lines are
toggled while the in VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may
be degraded during the time of this programming.
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16
Typical Performance Characteristics
OSCin Input Impedance
20101106
Powered Up (kΩ)
Imaginary
-2.70
Powered Down (kΩ)
Frequency
(MHz)
Real
4.98
3.44
1.42
0.52
0.29
0.18
0.13
0.10
0.09
0.07
0.07
0.06
0.06
0.05
0.05
0.04
0.04
Magnitude
5.66
4.63
3.02
1.71
1.25
0.94
0.75
0.64
0.56
0.50
0.46
0.42
0.38
0.34
0.32
0.30
0.28
Real
6.77
5.73
1.72
0.53
0.26
0.17
0.14
0.10
0.09
0.08
0.07
0.07
0.07
0.06
0.06
0.05
0.05
Imaginary
-8.14
-6.72
-5.24
-2.94
-2.12
-1.58
-1.24
-1.06
-0.95
-0.86
-0.80
-0.72
-0.65
-0.59
-0.55
-0.50
-0.47
Magnitude
10.59
9.03
5.51
2.98
2.14
1.59
1.25
1.06
0.95
0.87
0.80
0.72
0.65
0.59
0.55
0.50
0.47
1
5
-3.04
10
-2.67
20
-1.63
30
-1.22
40
-0.92
50
-0.74
60
-0.63
70
-0.56
80
-0.50
90
-0.46
100
110
120
130
140
150
-0.41
-0.37
-0.34
-0.32
-0.29
-0.27
17
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N = NInteger + NFractional
1.0 Functional Description
For example, if the phase detector frequency (fPD) was 10
MHz and the VCO frequency (fVCO) was 1736.1 MHz, then N
would be 173.61. This would imply that NInteger is 173 and
NFractional is 61/100. NInteger has some minimum value restric-
tions that are arise due to the architecture of this divider. The
first restrictions arise because the N divider value is actually
formed by a quadruple modulus 16/17/20/21 prescaler, which
creates minimum divide values. NInteger is further restricted
because the LMX2531 due to the fractional engine of the N
divider.
The LMX2531 is a low power, high performance frequency
synthesizer system which includes the PLL, VCO, and par-
tially integrated loop filter. The following sections give a dis-
cussion of the various blocks of this device.
1.1 REFERENCE OSCILLATOR INPUT
Because the VCO frequency calibration algorithm is based on
clocks from the OSCin pin, there are certain bits that need to
be
set
depending
on
the
OSCin
frequency.
XTLSEL (R6[22:20]) and XTLDIV (R7[9:8]) are both need to
be set based on the OSCin frequency, fOSCin. For some op-
The fractional word, NFractional , is a fraction formed with the
NUM and DEN words. In the example used here with the
fraction of 61/100, NUM = 61 and DEN = 100. The fractional
denominator value, DEN, can be set from 2 to 4,194,303. The
case of DEN=0 makes no sense, since this would cause an
infinite N value; the case of 1 makes no sense either (but
could be done), because integer mode should be used in
these applications. All other values in this range, like 10, 32,
42, 734, or 4,000,000 are all valid. Once the fractional de-
nominator, DEN, is determined, the fractional numerator,
NUM, is intended to be varied from 0 to DEN-1.
tions
and
for
low
OSCin
frequencies,
the
XTLMAN (R7[21:10]) and XTLMAN2 (R8[4]) words need to
be set to the correct value.
1.2 R DIVIDER
The R divider divides the OSCin frequency down to the phase
detector frequency. The R divider value, R, is restricted to the
values of 1, 2, 4, 8, 16, and 32. If R is greater than 8, then this
also puts restrictions on the fractional denominator, FDEN,
than can be used. This is discussed in greater depth in later
sections.
In general, the fractional denominator, DEN, can be calculat-
ed by dividing the phase detector frequency by the greatest
common divisor (GCD) of the channel spacing (fCH) and the
phase detector frequency. If the channel spacing is not obvi-
ous, then it can be calculated as the greatest common divisor
of all the desired VCO frequencies.
1.3 PHASE DETECTOR AND CHARGE PUMP
The phase detector compares the outputs of the R and N di-
viders and puts out a correction current corresponding to the
phase error. The phase detector frequency, fPD, can be cal-
culated as follows:
FDEN = k · fPD / GCD(fPD , fCH
k = 1, 2, 3 ..
)
fPD = fOSCin / R
Choosing R = 1 yields the highest possible phase detector
frequency and is optimum for phase noise, although there are
restrictions on the maximum phase detector frequency which
could force the R value to be larger. The far out PLL noise
improves 3 dB for every doubling of the phase detector fre-
quency, but at lower offsets, this effect is much less due to
the PLL 1/f noise. Aside from getting the best PLL phase
noise, higher phase detector frequencies also make it easier
to filter the noise that the delta-sigma modulator produces,
which peaks at an offset frequency of fPD/2 from the carrier.
The LMX2531 also has 16 levels of charge pump currents and
a highly flexible fractional modulus. Increasing the charge
pump current improves the phase noise about 3 dB per dou-
bling of the charge pump current, although there are small
diminishing returns as the charge pump current increases.
For example, consider the case of a 10 MHz phase detector
frequency and a 200 kHz channel spacing at the VCO output.
The greatest common divisor of 10 MHz and 200 kHz is just
200 kHz. If one takes 10 MHz divided by 200 kHz, the result
is 50. So a fractional denominator of 50, or any multiple of 50
would work in this example. Now consider a case with a 10
MHz phase detector frequency and a 30 kHz channel spac-
ing. The greatest common divisor of 10 MHz and 30 kHz is
10 kHz. The fractional denominator therefore must be a mul-
tiple 1000, since this is 10 MHz divided by 10 kHz. For a final
example, consider an application with a fixed output frequen-
cy of 2110.8 MHz and a OSCin frequency of 19.68 MHz. If the
phase detector frequency is chosen to be 19.68 MHz, then
the channel spacing can be calculated as the greatest com-
mon multiple of 19.68 MHz and 2110.8 MHz, which is 240
kHz. The fractional denominator is therefore a multiple of 41,
which is 19.68 MHz / 240 kHz. Refer to application note 1865
for more details on frequency planning.
From a loop filter design and PLL phase noise perspective,
one might think to always design with the highest possible
phase detector frequency and charge pump current. Howev-
er, if one considers the worst case fractional spurs that occur
at an output frequency equal to 1 channel spacing away from
a multiple of the fOSCin, then this gives reason to reconsider.
If the phase detector frequency or charge pump currents are
too high, then these spurs could be degraded, and the loop
filter may not be able to filter these spurs as well as theoreti-
cally predicted. For optimal spur performance, a phase de-
tector frequency around 2.5 MHz and a charge pump current
of 1X are recommended.
To achieve a fractional N value, an integer N divider is mod-
ulated between different values. This gives rise to three main
degrees of freedom with the LMX2531 delta sigma engine in-
cluding the modulator order, dithering, and the way that the
fractional portion is expressed. The first degree of freedom is
the modulator order, which gives the user the ability to opti-
mize for a particular application. The modulator order can be
selected as zero (integer mode), two, three, or four. One sim-
ple technique to better understand the impact of the delta
sigma fractional engine on noise and spurs is to tune the VCO
to an integer channel and observe the impact of changing the
modulator order from integer mode to a higher order. The
higher the fractional modulator order is, the lower the spurs
theoretically are. However, this is not always the case, and
the higher order fractional modulator can sometimes give rise
to additional spurious tones, but this is dependent on the ap-
plication. The second degree of freedom with the LMX2531
1.4 N DIVIDER AND FRACTIONAL CIRCUITRY
The N divider in the LMX2531 includes fractional compensa-
tion and can achieve any fractional denominator between 1
and 4,194,303. The integer portion, NInteger, is the whole part
of the N divider value and the fractional portion, NFractional, is
the remaining fraction. So in general, the total N divider value,
N, is determined by:
www.national.com
18
delta sigma engine is dithering. Dithering is often effective in
reducing these additional spurious tones, but can add phase
noise in some situations. The third degree of freedom is the
way that the fraction is expressed. For example, 1/10 can be
expressed as 100000/1000000. Expressing the fraction in
higher order terms sometimes improves the performance,
particularly when dithering is used. In conclusion, there are
some guidelines to getting the optimum choice of settings, but
these optimum settings are application specific. Refer to ap-
plication note 1879 for a much more detailed discussion on
fractional PLLs and fractional spurs..
VCO internally divides up the frequency range into several
bands, in order to achieve a lower tuning gain, and therefore
better phase noise performance. The frequency calibration
routine is activated any time that the R0 register is pro-
grammed. There are several bits including LOCKMODE and
XTLSEL that need to be set properly for this calibration to be
performed in a reliable fashion. If the temperature shifts con-
siderably and the R0 register is not programmed, then it can
not drift more than the maximum allowable drift for continuous
lock, ΔTCL, or else the VCO is not guaranteed to stay in lock.
The phase noise calibration algorithm is necessary in order
to achieve the lowest possible phase noise. Each version of
the LMX2531, the VCO_ACI_SEL bit (R6[19:16]) needs to be
set to the correct value to ensure the best possible phase
noise.
1.5 PARTIALLY INTEGRATED LOOP FILTER
The LMX2531 integrates the third pole (formed by R3 and C3)
and fourth pole (formed by R4 and C4) of the loop filter. The
values for C3, C4, R3, and R4 can also be programmed in-
dependently through the MICROWIRE interface and also R3
and R4 can be changed during FastLock™, for minimum lock
time. The larger the values of these components, the stronger
the attenuation of the internal loop filter. The maximum atten-
uation can be achieved by setting R3=R4=40 kΩ and
C3=C4=100 pF while the minimum attenuation is achieved by
disabling the loop filter by setting EN_LPFLTR (R6[15]) to ze-
ro. Note that when the internal loop filter is disabled, there is
still a small amount of input capacitance on front of the VCO
on the order of 200 pF.
The gain of the VCO can change considerably over frequen-
cy. It is lowest at the minimum frequency and highest at the
maximum frequency. This range is specified in the electrical
specifications section of the datasheet. When designing the
loop filter, the following method is recommended to determine
what VCO gain to design to. First, take the geometric mean
of the minimum and maximum frequencies that are to be
used. Then use a linear approximation to extrapolate the VCO
gain.
Suppose
the
application
requires
the
LMX2531LQ2080E PLL to tune from 2100 to 2150 MHz. The
geometric mean of these frequencies is sqrt(2100 × 2150)
MHz = 2125 MHz. The VCO gain is specified as 9 MHz/V at
1904 MHz and 20 MHz/V at 2274 MHz. Over this range of 370
MHz, the VCO gain changes 11 MHz/V. So at 2125 MHz, the
VCO gain would be approximately 9 + (2125-1904)* 11/370
= 15.6 MHz/V. Although the VCO gain can change from part
to part, this variation is small compared to how much the VCO
gain can change over frequency.
Since that the internal loop filter is on-chip, it is more effective
at reducing certain spurs than the external loop filter. The
higher order poles formed by the integrated loop filter are also
helpful for attenuating noise due to the delta-sigma modula-
tor. This noise produced by the delta-sigma modulator is
outside the loop bandwidth and dependent on the modulator
order. Although setting the filtering for maximum attenuation
gives the best filtering, it puts increased restrictions on how
wide the loop bandwidth of the system can be, which corre-
sponds to the case where the shunt loop filter capacitor, C1,
is zero. Increasing the charge pump current and/or the phase
detector frequency increases the maximum attainable loop
bandwidth when designing with the integrated filter. It is rec-
ommended to set the internal loop filter as high as possible
without restricting the loop bandwidth of the system more than
desired. If some setting between the minimum and maximum
value is desired, it is preferable to reduce the resistor values
before reducing the capacitor values since this will reduce the
thermal noise contribution of the loop filter resistors. For de-
sign tools and more information on partially integrated loop
filters, go to www.national.com/wireless.
The VCO frequency is related to the other frequencies and
divider values as follows:
fVCO = fPD × N = fOSCin × N / R
1.7 PROGRAMMABLE VCO DIVIDER
All options of the LMX2531 offer the option of dividing the
VCO output by two to get half of the VCO frequency at the
Fout pin. The channel spacing at the Fout pin is also divided
by two as well. Because this divide by two is outside feedback
path between the VCO and the PLL, enabling does require
one to change the N divider, R divider, or loop filter values.
When this divider is enabled, there will be some far-out phase
noise contribution to the VCO noise. Note that the R0 register
should be reprogrammed the first time after the DIV2 bit is
enabled or disabled for optimal phase noise performance.
The frequency at the Fout pin is related to the VCO frequency
and divider value, D, as follows:
1.6 LOW NOISE, FULLY INTEGRATED VCO
The LMX2531 includes a fully integrated VCO, including the
inductors. For optimum phase noise performance, this VCO
has frequency and phase noise calibration algorithms. The
frequency calibration algorithm is necessary because the
fFout = fVCO / D
19
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2.0 General Programming Information
The LMX2531 is programmed using 11 24-bit registers used to control the LMX2531 operation. A 24-bit shift register is used as a
temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The
last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address. The remaining 20 bits
form the data field DATA[19:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is
programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank. Although there
are actually 14 registers in this part, only a portion of them should be programmed, since the state of the other hidden registers
(R13, R11, and R10) are set during the initialization sequence. Although it is possible to program these hidden registers, as well
as a lot of bits that are defined to either '1' or '0', the user should not experiment with these hidden registers and bits, since the
parts are not tested under these conditions and doing so will most likely degrade performance.
DATA[19:0]
CONTROL[3:0]
LSB
MSB
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C3 C2 C1 C0
2.01 REGISTER LOCATION TRUTH TABLE
C3
1
C2
1
C1
0
C0
0
Data Address
R12
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
2.02 INITIALIZATION SEQUENCE
The initial loading sequence from a cold start is described below. The registers must be programmed in order shown. There must
be a minimum of 10 ms between the time when R5 is last loaded and R1 is loaded to ensure time for the LDOs to power up properly.
23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA[19:0]
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
REG.
C3 C2 C1 C0
R5
INIT1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
R5
INIT2
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R5
R12
R9
0
1
1
1
1
0
0
0
0
1
0
1
Program R12 as shown in the complete register map.
Program R9 as shown in the complete register map.
See individual section for Register R8 programming information.
R8
1
0
0
0
Programming of this register is necessary under specific circumstances.
See individual section for Register R7 programming information.
See individual section for Register R6 programming information.
R7
R6
0
0
1
1
1
1
1
0
See individual section for Register R4 programming information.
Register R4 only needs to be programmed if FastLock is used.
R4
0
1
0
0
R3
R2
R1
R0
See individual section for Register R3 programming information.
See individual section for Register R2 programming information.
See individual section for Register R1 programming information.
See individual section for Register R0 programming information.
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
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20
E N _ P L L
E N _ V C O
E N _ O S C
E N _ V C O L D
E N _ P L L L D O 1
E N _ P L L L D O 2
E N _ D I G L D O
E N _ L P F L T R
R E G _ R S T
21
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2.1 REGISTER R0
The action of programming the R0 register activates a frequency calibration routine for the VCO. This calibration is necessary to
get the VCO to center the tuning voltage for optimal performance. If the temperature drifts considerably, then the PLL should stay
in lock, provided that the temperature drift specification is not violated.
2.1.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator
The NUM word is split between the R0 register and R1 register. The Numerator bits determine the fractional numerator for the
delta sigma PLL. This value can go from 0 to 4095 when the FDM bit (R3[22]) is 0 (the other bits in this register are ignored), or 0
to 4194303 when the FDM bit is 1.
Fractional
Numerator
NUM[21:12]
NUM[11:0]
0
...
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
409503
4096
...
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note that there are restrictions on the fractional numerator value depending on the R divider value if it is 16 or 32.
2.1.2 N[7:0] and N[10:8]
The N counter is 11 bits. 8 of these bits are located in the R0 register, and the remaining 3 (MSB bits) are located in the R1 register.
The LMX2531 consists of an A, B, and C counter, which work in conjunction with the 16/17/20/21 prescaler in order to form the
final N counter value.
N[10:8]
N[7:0]
Values less than 55 are prohibited.
N Value
<55
C
0
1
B
A
55
0
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
...
2039
1
1
1
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22
2.2 REGISTER R1
2.2.1 NUM[21:12]
These are the MSB bits in for the fractional numerator that already have been described.
2.2.2 N[10:8] -- 3 MSB Bits for the N Counter
These are the 2 MSB bits for the N counter, which were discussed in the R0 register section.
2.2.3 ICP[3:0] -- Charge Pump Current
This bit programs the charge pump current in from 90 µA to 1440 µA in 90 µA steps. In general, higher charge pump currents yield
better phase noise for the PLL, but also can cause higher spurs.
Typical Charge Pump Current at 3 Volts
ICP
Charge Pump State
(µA)
0
1
1X
2X
90
180
270
360
450
540
630
720
810
900
990
1080
1170
1260
1350
1440
2
3X
3
4X
4
5X
5
6X
6
7X
7
8X
8
9X
9
10X
11X
12X
13X
14X
15X
16X
10
11
12
13
14
15
23
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2.3 REGISTER R2
2.3.1 R[5:0] -- R Counter Value
These bits determine the phase detector frequency. The OSCin frequency is divided by this R counter value. Note that only the
values of 1, 2, 4, 8, 16, and 32 are allowed.
Fractional
R Value
Denominator
Restrictions
R[5:0]
0,3,5-7,
9-15,17-31,
33-63
n/a
These values are illegal.
1
2
4
8
none
none
none
none
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
Must be
divisible by 2
16
32
0
1
1
0
0
0
0
0
0
0
0
0
Must be
divisible by 4
The R counter value can put some restrictions on the fractional denominator. In the case that it is 16, the fractional denominator
must be divisible by 2, which is equivalent to saying that the LSB of the fractional denominator word is zero. In the case that the
R counter is 32, the two LSB bits of the fractional denominator word must also be zero, which is equivalent to saying that the
fractional denominator must be divisible by 4. Because the fractional denominator can be very large, this should cause no issues.
For instance, if one wanted to achieve a fractional word of 1/65, and the R counter value was 16, the fractional word could be
changed to 4/260, and the same resolution could be achieved.
2.3.2 DEN[21:12] and DEN[11:0]-- Fractional Denominator
These bits determine the fractional denominator. Note that the MSB bits for this word are in register R3. If the FDM bit is set to 0,
DEN[21:12] are ignored. The fractional denominator should only be set to zero if the fractional circuitry is being disabled by setting
ORDER=1. A value of one never makes sense to use. All other values could reasonably be used in fractional mode.
Fractional
Denominator
DEN[21:12]
DEN[11:0]
0
...
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4095
4096
...
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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24
2.4 REGISTER R3
2.4.1 DEN[21:12] -- Extension for the Fractional Denominator
These are the MSB bits of the DEN word, which have already been discussed.
2.4.2 FoLD[3:0] -- Multiplexed Output for Ftest/LD Pin
The FoLD[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general purpose I/O pin, a lock
detect pin, and for diagnostic purposes. When programmed to the digital lock detect state, the output of the Ftest/LD pin will be
high when the part is in lock, and low otherwise. Lock is determined by comparing the input phases to the phase detector. The
analog lock detect modes put out a high signal with very fast negative pulses, that correspond to when the charge pump comes
on. This output can be low pass filtered with an RC filter in order to determine the lock detect state. If the open drain state is used,
a additional pull-up resistor is required. For diagnostic purposes, the options that allow one to view the output of the R counter or
the N counter can be very useful. Be aware that the output voltage level of the Ftest/LD is not equal to the supply voltage of the
part, but rather is given by VOH and VOL in the electrical characteristics specification.
FoLD
0
Output Type
High Impedance
Push-Pull
Push-Pull
Push-Pull
N/A
Function
Disabled
1
Logical High State
Logical Low State
Digital Lock Detect
Reserved
2
3
4
5
Push-Pull
Open-Drain
Push-Pull
N/A
N Counter Output Divided by 2
Analog Lock Detect
Analog Lock Detect
Reserved
6
7
8
9
N/A
Reserved
10
11
12
13
14
15
N/A
Reserved
N/A
Reserved
N/A
Reserved
N/A
Reserved
Push-Pull
N/A
R Counter Output
Reserved
2.4.3 ORDER -- Order of Delta Sigma Modulator
This bit determines the order of the delta sigma modulator in the PLL. In general, higher order fractional modulators tend to reduce
the primary fractional spurs that occur at increments of the channel spacing, but can also create spurs that are at a fraction of the
channel spacing, if there is not sufficient filtering. The optimal choice of modulator order is very application specific, however, a
third order modulator is a good starting point if not sure what to try first.
ORDER
Delta Sigma Modulator Order
0
Fourth
Reset Modulator
(Integer Mode - all fractions are ignored)
1
2
3
Second
Third
25
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2.4.4 DITHER -- Dithering
Dithering is useful in reducing fractional spurs, especially those that occur at a fraction of the channel spacing. The only exception
is when the fractional numerator is zero. In this case, dithering usually is not a benefit. Dithering also can sometimes increase the
PLL phase noise by a fraction of a dB. In general, if dithering is disabled, phase noise may be slightly better inside the loop bandwidth
of the system, but spurs are likely to be worse too.
DITHER
Dithering Mode
Weak Dithering
Reserved
0
1
2
3
Strong Dithering
Dithering Disabled
2.4.5 FDM -- Fractional Denominator Mode
When this bit is set to 1, the 10 MSB bits for the fractional numerator and denominator are considered. This allows the fractional
denominator to range from 1 to 4,194,303. If this bit is set to zero, only the 12 LSB bits of the fractional numerator and denominator
are considered, and this allows a fractional denominator from 1 to 4095. When this bit is disabled, the current consumption is about
0.5 mA lower.
2.4.6 -- DIV2
When this bit is enabled, the output of the VCO is divided by 2. Enabling this bit does have some impact on harmonic content and
output power.
DIV2
VCO Output Frequency
Not Divided by 2
Divided by 2
0
1
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26
2.5 REGISTER R4
2.5.1 TOC[13:0] -- Time Out Counter for FastLock
When the value of this word is 3 or less, then FastLock is disabled, and this pin can only be used for general purpose I/O. When
this value is 4 or greater, the time out counter is engaged for the amount of phase detector cycles shown in the table below.
TOC Value
FLout Pin State
Timeout Count
0
High Impedance
0
1
Low
Low
High
Low
.
Always Enabled
2
0
3
0
4
.
4 × 2 Phase Detector
.
16383
Low
16383 × 2 Phase Detector
When this count is active, the FLout Pin is grounded, the FastLock current is engaged, and the resistors R3 and R4 are also
potentially changed. The table below summarizes the bits that control various values in and out of FastLock differences.
FastLock State
Steady State
Fastlock
FLout
Charge Pump Current
R3
R4
High Impedance
Grounded
ICP
R3_ADJ
R4_ADJ
ICPFL
R3_ADJ_FL
R4_ADJ_FL
2.5.2 ICPFL[3:0] -- Charge Pump Current for Fastlock
When FastLock is enabled, this is the charge pump current that is used for faster lock time.
Typical Fastlock Charge Pump Current
at 3 Volts (µA)
ICPFL
Fastlock Charge Pump State
0
1
1X
2X
90
180
2
3X
270
3
4X
360
4
5X
450
5
6X
540
6
7X
630
7
8X
720
8
9X
810
9
10X
11X
12X
13X
14X
15X
16X
900
10
11
12
13
14
15
990
1080
1170
1260
1350
1440
27
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2.6 REGISTER R5
2.6.1 EN_PLL -- Enable Bit for PLL
When this bit is set to 1 (default), the PLL is powered up, otherwise, it is powered down.
2.6.2 EN_VCO -- Enable Bit for the VCO
When this bit is set to 1 (default), the VCO is powered up, otherwise, it is powered down.
2.6.3 EN_OSC -- Enable Bit for the Oscillator Inverter
When this bit is set to 1 (default), the reference oscillator is powered up, otherwise it is powered down.
2.6.4 EN_VCOLDO -- Enable Bit for the VCO LDO
When this bit is set to 1 (default), the VCO LDO is powered up, otherwise it is powered down.
2.6.5 EN_PLLLDO1 -- Enable Bit for the PLL LDO 1
When this bit is set to 1 (default), the PLL LDO 1 is powered up, otherwise it is powered down.
2.6.6 EN_PLLLDO2 -- Enable Bit for the PLL LDO 2
When this bit is set to 1 (default), the PLL LDO 2 is powered up, otherwise it is powered down.
2.6.7 EN_DIGLDO -- Enable Bit for the digital LDO
When this bit is set to 1 (default), the Digital LDO is powered up, otherwise it is powered down.
2.6.8 REG_RST -- RESETS ALL REGISTERS TO DEFAULT SETTINGS
This bit needs to be programmed three times to initialize the part. When this bit is set to one, all registers are set to default mode,
and the part is powered down. The second time the R5 register is programmed with REG_RST=0, the register reset is released
and the default states are still in the registers. However, since the default states for the blocks and LDOs is powered off, it is
therefore necessary to program R5 a third time so that all the LDOs and blocks can be programmed to a power up state. When
this bit is set to 1, all registers are set to the default modes, but part is powered down. For normal operation, this bit is set to 0.
Note that once this initialization is done, it is not necessary to do this again unless power is removed from the device.
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28
2.7 REGISTER R6
2.7.1 C3_C4_ADJ[2:0] -- VALUE FOR C3 AND C4 IN THE INTERNAL LOOP FILTER
C3_C4_ADJ
C3 (pF)
50
C4 (pF)
50
0
1
2
3
4
5
6
7
50
100
150
50
50
100
150
100
50
50
100
150
150
50
2.7.2 R3_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock
R3_ADJ_FL Value
R3 Resistor During Fastlock (kΩ)
0
1
2
3
10
20
30
40
2.7.3 R3_ADJ[1:0] -- Value for Internal Loop Filter Resistor R3
R3_ADJ
R3 Value (kΩ)
0
1
2
3
10
20
30
40
2.7.4 R4_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock
R4_ADJ_FL
R4 Value during Fast Lock (kΩ)
0
1
2
3
10
20
30
40
2.7.5 R4_ADJ[1:0] -- Value for Internal Loop Filter Resistor R4
R4_ADJ
R4 Value ( kΩ )
0
1
2
3
10
20
30
40
2.7.6 EN_LPFLTR-- Enable for Partially Integrated Internal Loop Filter
The Enable Loop Filter bit is used to enable or disable the 3rd and 4th pole on-chip loop filters.
EN_LPFLTR
3rd and 4th Poles of Loop Filter
disabled
0
1
(R3 = R4 = 0 Ω and C3 + C4 = 200pF)
enabled
29
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2.7.7 VCO_ACI_SEL
This bit is used to optimize the VCO phase noise. The recommended values are what are used for all testing purposes, and this
bit should be set as the table below instructs.
Part
VCO_ACI_SEL
All Other Options
8
LMX2531LQ2265E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
6
2.7.8 XTLSEL[2:0] -- Crystal Select
The XTLSEL bit is used to select between manual crystal mode and one of the automatic modes. The user may choose manual
crystal mode (XTLSEL=4) and program the XTLMAN (R7[21:10]) and XTLMAN2 (R7[4]) bits for a specific OSCin frequency, or
one of the automatic modes (XTLSEL = 0,1,2,3). For the LMX2531LQ2080E/2570E options or when the OSCin frequency is less
than 8 MHz, manual crystal mode must always be selected. The automatic modes can be used for the other frequency options.
When using one of the automatic modes, XTLSEL should be set based on the OSCin frequency.
XTLSEL
Mode
OSCin Frequency
8 - 25 MHz
0
1
2
3
Automatic Modes
25 - 50 MHz
50 - 70 MHz
70 - 80 MHz
Programming of XTLMAN (R7[21:10]) not required.
Programming of XTLMAN2 (R7[4]) not required.
Manual Crystal Mode
Must use this for LMX2531LQ2080E/2570E/2820E/3010E
Must use this if fOSCin < 8 MHz
4
5 - 80 MHz
Programming of XTLMAN (R7[21:10]) required.
Programming of XTLMAN2 (R7[4]) may be required.
Reserved
5,6,7
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30
2.8 REGISTER R7
2.8.1 XTLDIV[1:0] -- Division Ratio for the Crystal Frequency
The frequency provided to the VCO frequency calibration circuitry is based on the OSCin frequency divided down by a factor,
determined by the XTLDIV word. Note that this division ratio is independent of the R counter value or the phase detector frequency.
The necessary division ratio depends on the OSCin frequency and is shown in the table below:
XTLDIV
Crystal Division Ratio
Reserved
Crystal Range
Reserved
0
1
2
3
Divide by 2
< 20 MHz
Divide by 4
20-40 MHz
> 40 MHz
Divide by 8
2.8.2 XTLMAN[11:0] -- Manual Crystal Mode
XTLMAN must be programmed if word XTLSEL (2.7.8) is set to manual crystal mode. In the table below, the proper value for
XTLMAN is shown based on some common OSCin frequencies (fOSCin) and various LMX2531 options. For any OSCin frequency
XTLMAN can be calculated as 16 × fOSCin / Kbit. fOSCin is expressed in MHz and Kbit values for the LMX2531 frequency options
can be found in the Kbit table (below).
XTLMAN Values for Common OSCin Frequencies
fOSCin
Device
5 MHz
53
53
47
47
40
38
38
35
32
31
27
20
18
13
11
10
10 MHz
107
107
94
20 MHz
213
213
188
188
160
152
152
139
128
123
107
80
30.72 MHz
327
327
289
289
246
234
234
214
197
189
164
123
109
82
61.44 MHz
655
76.8 MHz
819
819
722
722
614
585
585
534
492
473
410
307
273
205
178
154
LMX2531LQ1146E
LMX2531LQ1226E
LMX2531LQ1312E
LMX2531LQ1415E
LMX1531LQ1515E
LMX2531LQ1570E
LMX2531LQ1650E
LMX2531LQ1700E
LMX2531LQ1742
LMX2531LQ1778E
LMX2531LQ1910E
LMX2531LQ2265E
LMX2531LQ2080E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
655
578
94
578
80
492
76
468
76
468
70
427
64
393
62
378
53
328
40
246
36
71
218
27
53
164
23
46
70
140
20
40
61
123
Kbit Values for Various LMX2531 options
Device
Kbit
LMX2531LQ1146E
LMX2531LQ1226E
LMX2531LQ1312E
LMX2531LQ1415E
LMX2531LQ1515E
LMX2531LQ1570E
LMX2531LQ1650E
LMX2531LQ1700E
LMX25311742
1.5
1.5
1.7
1.7
2
2.1
2.1
2.3
2.5
2.6
3
LMX2531LQ1778E
LMX2531LQ1910E
LMX2531LQ2265E
4
31
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Kbit Values for Various LMX2531 options
Device
Kbit
4.5
6
LMX2531LQ2080E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
7
8
2.9 REGISTER R8
2.9.1 XTLMAN2 -- MANUAL CRYSTAL MODE SECOND ADJUSTMENT
This bit also adjusts the calibration timing for lock time. In the case that manual mode for XTLSEL is selected and the OSCin
frequency is greater than 40 MHz, this bit should be enabled, otherwise it should be 0.
2.9.2 LOCKMODE -- FREQUENCY CALIBRATION MODE
This bit controls the method for which the VCO frequency calibration is done. The two valid modes are linear mode and mixed
mode. Linear mode works by searching through the VCO frequency bands in a consecutive manner. Mixed mode works by initially
using a divide and conquer approach and then using a linear approach. For small frequency changes, linear mode is faster and
for large frequency changes, mixed mode is faster. Linear mode can always be used, but there are restrictions for when Mixed
Mode can be used.
LOCKMODE
Description
Reserved
Conditions on Options
Conditions on OSCin Frequency
0
1
Never use this mode
Linear Mode
Works over all options and all valid OSCin Frequencies
All but the following options
LMX2531LQ1146E/1226E/1312E/1415E/1515E
Never use this mode
2
3
Mixed Mode
Reserved
fOSCin ≥ 8 MHz
2.10 REGISTER R9
All the bits in this register should be programmed as shown in the programming table.
2.11 REGISTER R12
Even though this register does not have user selectable bits, it still needs to be programmed. This register should be loaded as
shown the Complete Register Content Map (section 2.03) .
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32
Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package (NS Package Number LQA036D), D Version (Bottom View)
(LMX2531LQ1146E/1226E/1312E/1415E/1515E/2820E/3010E)
Order Number LMX2531LQX for 2500 Unit Reel
Order Number LMX2531LQ for 250 Unit Reel
Leadless Leadframe Package (NS Package Number LQA036A), A Version (Bottom View)
(All Other Options)
Order Number LMX2531LQX for 2500 Unit Reel
Order Number LMX2531LQ for 250 Unit Reel
33
www.national.com
Part
Marking
311742EA
311778EA
311910EB
312080EB
312265ED
312570EC
312820E
Package
LQA036A
LQA036A
LQA036A
LQA036A
LQA036A
LQA036A
LQA036D
LQA036D
Part
Marking
311146E
311226E
311312E
311415E
311515E
311570EB
311650EA
311778EB
Package
LQA036D
LQA036D
LQA036D
LQA036D
LQA036D
LQA036A
LQA036A
LQA036A
LMX2531LQ1742
LMX2531LQ1778E
LMX2531LQ1910E
LMX2531LQ2080E
LMX2531LQ2265E
LMX2531LQ2570E
LMX2531LQ2820E
LMX2531LQ3010E
LMX2531LQ1146E
LMX2531LQ1226E
LMX2531LQ1312E
LMX2531LQ1415E
LMX2531LQ1515E
LMX2531LQ1570E
LMX2531LQ1650E
LMX2531LQ1700E
313010E
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34
Notes
35
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相关型号：
LMX2531LQ1500E
PLL FREQUENCY SYNTHESIZER, 80MHz, QCC36, 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36
ROCHESTER
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