LP38842-ADJ [NSC]
1.5A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors; 1.5A超低压差可调线性稳压器稳定器用陶瓷输出电容器
| 型号： | LP38842-ADJ |
| 厂家： | 
National Semiconductor |
| 描述： | 1.5A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors |
| 文件： | 总8页 (文件大小：593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2005
LP38842-ADJ
1.5A Ultra Low Dropout Adjustable Linear Regulators
Stable with Ceramic Output Capacitors
General Description
Features
n Ideal for conversion from 1.8V or 1.5V inputs
n Designed for use with low ESR ceramic capacitors
The LP38842-ADJ is a high current, fast response regulator
which can maintain output voltage regulation with minimum
input to output voltage drop. Fabricated on a CMOS process,
the device operates from two input voltages: Vbias provides
voltage to drive the gate of the N-MOS power transistor,
while Vin is the input voltage which supplies power to the
load. The use of an external bias rail allows the part to
operate from ultra low Vin voltages. Unlike bipolar regula-
tors, the CMOS architecture consumes extremely low quies-
cent current at any output load current. The use of an
N-MOS power transistor results in wide bandwidth, yet mini-
mum external capacitance is required to maintain loop sta-
bility.
@
n Ultra low dropout voltage (115mV 1.5A typ)
n 0.56V to 1.5V adjustable output range
n Load regulation of 0.1%/A (typ)
n 30nA quiescent current in shutdown (typ)
n Low ground pin current at all loads
n Over temperature/over current protection
n Available in 8 lead PSOP package
n −40˚C to +125˚C junction temperature range
<
n UVLO disables output when VBIAS 3.8V
The fast transient response of these devices makes them
suitable for use in powering DSP, Microcontroller Core volt-
ages and Switch Mode Power Supply post regulators. The
parts are available in the PSOP package.
Applications
n ASIC Power Supplies In:
- Desktops, Notebooks, and Graphics Cards, Servers
- Gaming Set Top Boxes, Printers and Copiers
n Server Core and I/O Supplies
@
Dropout Voltage: 115 mV (typ) 1.5A load current.
Quiescent Current: 30 mA (typ) at full load.
n DSP and FPGA Power Supplies
n SMPS Post-Regulators
Shutdown Current: 30 nA (typ) when S/D pin is low.
Precision Reference Voltage: 1.5% room temperature ac-
curacy.
Typical Application Circuit
20117601
* Minimum value required if Tantalum capacitor is used (see Application Hints).
© 2005 National Semiconductor Corporation
DS201176
www.national.com
Connection Diagram
20117635
PSOP-8, Top View
Pin Description
Pin Name
Description
BIAS
The bias pin is used to provide the low current bias voltage to the chip which operates the internal
circuitry and provides drive voltage for the N-FET.
OUTPUT
GND
The regulated output voltage is connected to this pin.
This is both the power and analog ground for the IC. Note that both pin three and the tab of the
TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together
using the PC board copper trace material and connected to circuit ground.
The high current input voltage which is regulated down to the nominal output voltage must be
connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input
voltage can be as low as a few hundered millivolts above the output voltage.
This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if
this function is not used.
INPUT
SHUTDOWN
ADJ
The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1
and R2 (see Typical Application Circuit).
Ordering Information
Order Number
LP38842MR-ADJ
LP38842MRX-ADJ
Package Type
PSOP-8
Package Drawing
MRA08A
Supplied As
95 Units Tape and Reel
2500 Units Tape and Reel
PSOP-8
MRA08A
Block Diagram
20117624
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
IOUT (Survival)
Internally Limited
−0.3V to +6V
Output Voltage (Survival)
Junction Temperature
−40˚C to +150˚C
Storage Temperature Range
Lead Temp. (Soldering, 5 seconds)
ESD Rating
−65˚C to +150˚C
260˚C
Operating Ratings
VIN Supply Voltage
Shutdown Input Voltage
IOUT
(VOUT + VDO) to 5.5V
0 to +5.5V
Human Body Model (Note 3)
Machine Model (Note 9)
Power Dissipation (Note 2)
VIN Supply Voltage (Survival)
VBIAS Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
VADJ
2 kV
200V
1.5A
Operating Junction
Temperature Range
VBIAS Supply Voltage
VOUT
−40˚C to +125˚C
Internally Limited
−0.3V to +6V
−0.3V to +7V
−0.3V to +7V
-0.3V to +6V
4.5V to 5.5V
0.56V to 1.5V
Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA,
CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or
design.
TYP
(Note 4)
Symbol
VADJ
Parameter
Conditions
MIN
MAX
Units
<
<
Adjust Pin Voltage
10 mA IL 1.5A
0.552
0.568
VO(NOM) + 1V ≤ VIN ≤ 5.5V
4.5V ≤ VBIAS ≤ 5.5V
0.56
V
0.543
0.577
<
<
IADJ
Adjust Pin Bias Current
10 mA IL 1.5A
VO(NOM) + 1V ≤ VIN ≤ 5.5V
4.5V ≤ VBIAS ≤ 5.5V
1
µA
∆VO/∆VIN
∆VO/∆IL
VDO
Output Voltage Line Regulation VO(NOM) + 1V ≤ VIN ≤ 5.5V
(Note 6)
0.01
0.1
115
30
%/V
%/A
mV
mA
µA
<
<
Output Voltage Load
Regulation (Note 7)
10 mA IL 1.5A
0.4
1.1
175
315
35
40
1
Dropout Voltage (Note 8)
IL = 1.5A
<
<
IQ(VIN
)
Quiescent Current Drawn from 10 mA IL 1.5A
VIN Supply
V
≤ 0.3V
S/D
0.06
2
30
4
<
<
IQ(VBIAS
)
Quiescent Current Drawn from 10 mA IL 1.5A
mA
µA
VBIAS Supply
6
V
≤ 0.3V
1
S/D
0.03
30
UVLO
ISC
VBIAS Voltage Where
3.8
4
V
A
Regulator Output Is Enabled
Short-Circuit Current
VOUT = 0V
Shutdown Input
VSDT
Output Turn-off Threshold
Output = ON
Output = OFF
RLOAD X COUT
RLOAD X COUT
V S/D =1.3V
0.7
0.7
20
15
1
1.3
V
µs
0.3
<<
<<
Td (OFF)
Td (ON)
IS/D
Turn-OFF Delay
Turn-ON Delay
S/D Input Current
Td (OFF)
Td (ON)
µA
V
≤ 0.3V
−1
S/D
θJ-A
Junction to Ambient Thermal
Resistance
PSOP-8 Package (Note 10)
43
˚C/W
3
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Electrical Characteristics Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA,
CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or
design. (Continued)
TYP
(Note 4)
Symbol
Parameter
Conditions
MIN
MAX
Units
AC Parameters
PSRR (VIN
)
Ripple Rejection for VIN Input
Voltage
VIN = VOUT +1V, f = 120 Hz
VIN = VOUT + 1V, f = 1 kHz
VBIAS = VOUT + 3V, f = 120 Hz
VBIAS = VOUT + 3V, f = 1 kHz
f = 120 Hz
80
65
58
58
1
dB
PSRR (VBIAS
)
Ripple Rejection for VBIAS
Voltage
Output Noise Density
Output Noise Voltage
VOUT = 1.5V
µV/root−Hz
µV (rms)
en
BW = 10 Hz − 100 kHz
BW = 300 Hz − 300 kHz
150
90
Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. If power dissipation
causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation.
Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.
Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.
Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.
Note 9: The machine model is a 220 pF capacitor discharged directly into each pin.
Note 10: For optimum heat dissipation, the ground pad must be soldered to a copper plane or connected using vias to an internal copper plane.
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4
Typical Performance Characteristics Unless otherwise specified: TJ = 25˚C, CIN = 10 µF CER,
COUT = 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V.
VBIAS Transient Response
Load Transient Response
20117636
20117637
Load Transient Response
Dropout Voltage Over Temperature
20117638
20117639
VBIAS PSRR
VBIAS PSRR
20117651
20117641
5
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Typical Performance Characteristics Unless otherwise specified: TJ = 25˚C, CIN = 10 µF CER, COUT
= 22 µF CER, CBIAS = 1 µF CER, S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT
1V. (Continued)
+
VIN PSRR
Output Noise Voltage
20117643
20117642
VADJ / IADJ vs Temperature
20117660
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6
FZ = 1 / (2 x π x CFF x R1)
Application Hints
For best effect, select CFF so the zero frequency is approxi-
mately 70 kHz. The phase lead provided by CFF drops as the
output voltage gets closer to 0.56V (and R1 reduces in
value). The reason is that CFF also forms a pole whose
frequency is given by:
SETTING THE OUTPUT VOLTAGE
(Refer to Typical Application Circuit)
The output voltage is set using the resistive divider R1 and
R2. The output voltage is given by the formula:
FP = 1 / (2 x π x CFF x R1 // R2)
VOUT = VADJ x (1 + R1 / R2)
As R1 reduces, the two equations come closer to being
equal and the pole and zero begin to cancel each other out
which removes the beneficial phase lead of the zero.
The value of resistor R2 must be 10k or less for proper
operation.
EXTERNAL CAPACITORS
BIAS CAPACITOR
To assure regulator stability, input and output capacitors are
required as shown in the Typical Application Circuit.
The 0.1µF capacitor on the bias line can be any good quality
capacitor (ceramic is recommended).
OUTPUT CAPACITOR
BIAS VOLTAGE
An output capacitor is required on the LP3884X devices for
loop stability. The minimum value of capacitance necessary
depends on type of capacitor: if a solid Tantalum capacitor is
used, the part is stable with capacitor values as low as 4.7µF.
If a ceramic capacitor is used, a minimum of 22 µF of
capacitance must be used (capacitance may be increased
without limit). The reason a larger ceramic capacitor is re-
quired is that the output capacitor sets a pole which limits the
loop bandwidth. The Tantalum capacitor has a higher ESR
than the ceramic which provides more phase margin to the
loop, thereby allowing the use of a smaller output capacitor
because adequate phase margin can be maintained out to a
higher crossover frequency. The tantalum capacitor will typi-
cally also provide faster settling time on the output after a
fast changing load transient occurs, but the ceramic capaci-
tor is superior for bypassing high frequency noise.
The bias voltage is an external voltage rail required to get
gate drive for the N-FET pass transistor. Bias voltage must
be in the range of 4.5 - 5.5V to assure proper operation of
the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
regulator output from turning on if the bias voltage is below
approximately 3.8V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regula-
tor. The S/D pin must be actively terminated through a
pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If
this pin is driven from a source that actively pulls high and
low (such as a CMOS rail to rail comparator), the pull-up
resistor is not required. This pin must be tied to Vin if not
used.
The output capacitor must be located less than one centi-
meter from the output pin and returned to a clean analog
ground. Care must be taken in choosing the output capacitor
to ensure that sufficient capacitance is provided over the full
operating temperature range. If ceramics are selected, only
X7R or X5R types may be used because Z5U and Y5F types
suffer severe loss of capacitance with temperature and ap-
plied voltage and may only provide 20% of their rated ca-
pacitance in operation.
POWER DISSIPATION/HEATSINKING
Heatsinking for the PSOP-8 package is accomplished by
allowing heat to flow through the ground slug on the bottom
of the package into the copper on the PC board. The heat
slug must be soldered down to a copper plane to get good
heat transfer. It can also be connected through vias to inter-
nal copper planes. Since the heat slug is at ground potential,
traces must not be routed under it which are not at ground
potential. Under all possible conditions, the junction tem-
perature must be within the range specified under operating
conditions.
INPUT CAPACITOR
The input capacitor is also critical to loop stability because it
provides a low source impedance for the regulator. The
minimum required input capacitance is 10 µF ceramic (Tan-
talum not recommended). The value of CIN may be in-
creased without limit. As stated above, X5R or X7R must be
used to ensure sufficient capacitance is provided. The input
capacitor must be located less than one centimeter from the
input pin and returned to a clean analog ground.
FEED FORWARD CAPACITOR
(Refer to Typical Application Circuit)
A capacitor placed across R1 can provide some additional
phase margin and improve transient response. The capaci-
tor CFF and R1 form a zero in the loop response given by the
formula:
7
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Physical Dimensions inches (millimeters) unless otherwise noted
PSOP-8 8-Lead Molded PSOP-2
NS Package Number MRA08B
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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