LP3966ET-1.8 [NSC]
3A Fast Ultra Low Dropout Linear Regulators; 3A快速超低压降线性稳压器
| 型号： | LP3966ET-1.8 |
| 厂家： | 
National Semiconductor |
| 描述： | 3A Fast Ultra Low Dropout Linear Regulators |
| 文件： | 总14页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2000
LP3963/LP3966
3A Fast Ultra Low Dropout Linear Regulators
General Description
Features
n Ultra low dropout voltage
The LP3963/LP3966 series of fast ultra low-dropout linear
regulators operate from a +2.5V to +7.0V input supply. Wide
range of preset output voltage options are available. These
ultra low dropout linear regulators respond very fast to step
changes in load which makes them suitable for low voltage
microprocessor applications. The LP3963/LP3966 are de-
veloped on a CMOS process which allows low quiescent
current operation independent of output load current.This
CMOS process also allows the LP3963/LP3966 to operate
under extremely low dropout conditions.
n Low ground pin current
n Load regulation of 0.06%
n 15µA quiescent current in shutdown mode
n Guaranteed output current of 3A DC
n Available in TO-263 and TO-220 packages
n Output voltage accuracy 1.5%
n Error flag indicates output status (LP3963)
n Sense option improves better load regulation (LP3966)
n Extremely low output capacitor requirements
n Overtemperature/overcurrent protection
±
Dropout Voltage: Ultra low dropout voltage; typically 80mV
at 300mA load current and 800mV at 3A load current.
n −40˚C to +125˚C junction temperature range
Ground Pin Current: Typically 6mA at 3A load current.
Shutdown Mode: Typically 15µA quiescent current when
the shutdown pin is pulled low.
Applications
n Microprocessor power supplies
n GTL, GTL+, BTL, and SSTL bus terminators
n Power supplies for DSPs
n SCSI terminator
Error Flag: Error flag goes low when the output voltage
drops 10% below nominal value (for LP3963).
SENSE: Sense pin improves regulation at remote loads.
(For LP3966)
n Post regulators
Precision Output Voltage: Multiple output voltage options
n High efficiency linear regulators
n Battery chargers
are available ranging from 1.2V to 5.0V and adjustable, with
±
a guaranteed accuracy of 1.5% at room temperature, and
±
3.0% over all conditions ( varying line, load, and tempera-
n Other battery powered applications
ture).
Typical Application Circuits
DS101267-1
# Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional
stability margin.
*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications sec-
tion for more information.
© 2000 National Semiconductor Corporation
DS101267
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Typical Application Circuits (Continued)
DS101267-34
# Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional sta-
bility margin.
*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section
for more information.
Block Diagram LP3963
DS101267-3
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2
Block Diagram LP3966
DS101267-29
Block Diagram LP3966-ADJ
DS101267-35
Connection Diagrams
DS101267-5
Top View
TO220-5 Package
Bent, Staggered Leads
3
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Connection Diagrams (Continued)
DS101267-6
Top View
TO263-5 Package
Pin Description for TO220-5 and TO263-5 Packages
LP3963
LP3966
#
Pin
Name
SD
Function
Shutdown
Name
SD
Function
Shutdown
1
2
3
4
5
VIN
Input Supply
Ground
VIN
Input Supply
Ground
GND
VOUT
ERROR
GND
Output Voltage
ERROR Flag
VOUT
Output Voltage
SENSE/ADJ
Remote Sense
Pin/Output Adjust
Pin
Ordering Information
DS101267-31
Package Type Designator is ″T″ for TO220 package, and ″S″ for TO263 package.
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Ordering Information (Continued)
TABLE 1. Package Marking and Ordering Information
Output
Voltage
5.0
Order Number
LP3963ES-5.0
Description
Package
Type
Package Marking
Supplied As:
Rail
(Current, Option)
3A, Error Flag
TO263-5
LP3963ES-5.0
LP3963ESX-5.0
LP3963ES-3.3
LP3963ES-3.3
LP3963ES-2.5
LP3963ES-2.5
LP3963ES-1.8
LP3963ES-1.8
LP3966ES-5.0
LP3966ESX-5.0
LP3966ES-3.3
LP3966ES-3.3
LP3966ES-2.5
LP3966ES-2.5
LP3966ES-1.8
LP3966ES-1.8
LP3966ES-ADJ
LP3966ES-ADJ
LP3963ET-5.0
LP3963ET-3.3
LP3963ET-2.5
LP3963ET-1.8
LP3966ET-5.0
LP3966ET-3.3
LP3966ET-2.5
LP3966ET-1.8
LP3966ET-ADJ
5.0
LP3963ESX-5.0
LP3963ES-3.3
LP3963ESX-3.3
LP3963ES-2.5
LP3963ESX-2.5
LP3963ES-1.8
LP3963ESX-1.8
LP3966ES-5.0
LP3966ESX-5.0
LP3966ES-3.3
LP3966ESX-3.3
LP3966ES-2.5
LP3966ESX-2.5
LP3966ES-1.8
LP3966ESX-1.8
LP3966ES-ADJ
LP3966ESX-ADJ
LP3963ET-5.0
LP3963ET-3.3
LP3963ET-2.5
LP3963ET-1.8
LP3966ET-5.0
LP3966ET-3.3
LP3966ET-2.5
LP3966ET-1.8
LP3966ET-ADJ
3A, Error Flag
3A, Error Flag
3A, Error Flag
3A, Error Flag
3A, Error Flag
3A, Error Flag
3A, Error Flag
3A, SENSE
3A, SENSE
3A, SENSE
3A, SENSE
3A, SENSE
3A, SENSE
3A, SENSE
3A, SENSE
3A, ADJ
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO263-5
TO220-5
TO220-5
TO220-5
TO220-5
TO220-5
TO220-5
TO220-5
TO220-5
TO220-5
Tape and Reel
3.3
Rail
3.3
Tape and Reel
2.5
Rail
2.5
Tape and Reel
1.8
Rail
1.8
Tape and Reel
5.0
Rail
5.0
Tape and Reel
3.3
Rail
3.3
Tape and Reel
2.5
Rail
2.5
Tape and Reel
1.8
Rail
1.8
Tape and Reel
ADJ
ADJ
5.0
Rail
3A, ADJ
Tape and Reel
3A, Error Flag
3A, Error Flag
3A, Error Flag
3A, Error Flag
3A, SENSE
3A, SENSE
3A, SENSE
3A, SENSE
3A, ADJ
Rail
Rail
Rail
Rail
Rail
Rail
Rail
Rail
Rail
3.3
2.5
1.8
5.0
3.3
2.5
1.8
ADJ
5
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
IOUT (Survival)
Short Circuit Protected
VIN+0.3V
Maximum Voltage for ERROR Pin
Maximum Voltage for SENSE Pin
VOUT+0.3V
Operating Ratings
Storage Temperature Range
Lead Temperature
−65˚C to +150˚C
Input Supply Voltage (Operating)
2.5V to 7.0V
(Soldering, 5 sec.)
260˚C
2 kV
Shutdown Input Voltage
(Operating)
ESD Rating (Note 3)
−0.3V to VIN+0.3V
Power Dissipation (Note 2)
Input Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
Internally Limited
−0.3V to +7.5V
−0.3V to VIN+0.3V
Maximum Operating Current
(DC)
3A
Operating Junction Temp. Range
−40˚C to +125˚C
Output Voltage (Survival), (Note
6), (Note 7)
−0.3V to +7.5V
Electrical Characteristics
LP3963/LP3966
Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature
range. Unless otherwise specified: VIN = VO(NOM) + 1.5V, IL = 10 mA, COUT =10µF, VSD = VIN-0.3V.
Symbol
Parameter
Conditions
Typ(Note
LP3963/6 (Note 5)
Units
4)
Min
Max
<
<
Output Voltage
Tolerance
(Note 8)
VOUT +1.5V VIN
7.0V
-1.5
-3.0
+1.5
+3.0
VO
0
%
%
%
< <
10 mA IL 3A
<
<
∆V OL
Output Voltage Line
Regulation (Note 8)
VOUT +1.5V VIN
7.0V,
0.02
0.06
<
<
∆VO/
∆IOUT
Output Voltage Load
Regulation
10 mA IL 3A
0.06
0.01
(Note 8)
VIN
VOUT
-
IL = 300 mA
IL = 3A
80
800
5
100
120
Dropout Voltage
(Note 10)
mV
1000
1200
IL = 300 mA
IL = 3A
9
10
Ground Pin Current In
Normal Operation
Mode
IGND
mA
µA
6
14
15
IGND
Ground Pin Current In
Shutdown Mode
(Note 11)
VSD ≤ 0.2V
15
25
75
IO(PK)
Peak Output Current
(Note 2)
4.5
5.5
4
3.5
A
A
SHORT CIRCUIT PROTECTION
ISC Short Circuit Current
OVER TEMPERATURE PROTECTION
Tsh(t)
Shutdown Threshold
165
10
˚C
˚C
Tsh(h)
Thermal Shutdown
Hysteresis
SHUTDOWN INPUT
Output = High
Output = Low
IL = 3A
VIN
0
VIN–0.3
VSDT
Shutdown Threshold
V
0.2
TdOFF
TdON
ISD
Turn-off delay
Turn-on delay
SD Input Current
Threshold
20
25
1
µs
µs
nA
%
IL = 3A
VSD = VIN
(Note 9)
VT
10
5
5
2
16
8
VTH
Threshold Hysteresis
(Note 9)
%
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Electrical Characteristics
LP3963/LP3966 (Continued)
Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature
range. Unless otherwise specified: VIN = VO(NOM) + 1.5V, IL = 10 mA, COUT =10µF, VSD = VIN-0.3V.
Symbol
Parameter
Conditions
Typ(Note
LP3963/6 (Note 5)
Units
4)
Min
Max
SHUTDOWN INPUT
VEF(Sat)
Td
Error Flag Saturation
Flag Reset Delay
Isink = 100µA
0.02
1
0.1
V
µs
nA
Ilk
Error Flag Pin Leakage
Current
1
Imax
Error Flag Pin Sink
Current
VError = 0.5V
1
mA
AC PARAMETERS
VIN = VOUT + 1.5V
COUT = 100uF
VOUT = 3.3V
60
40
PSRR
Ripple Rejection
dB
µV
VIN = VOUT + 0.3V
COUT = 100uF
VOUT = 3.3V
ρn(l/f
Output Noise Density
f = 120Hz
0.8
150
100
BW = 10Hz – 100kHz
BW = 300Hz – 300kHz
Output Noise Voltage
(rms)
µV
(rms)
en
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is in-
tended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Charateristics. The guar-
anteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θ = 50˚C/W
jA
2
(with 0.5in , 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at θ = 60˚C/W (with
jA
2
0.5in , 1oz. copper area), junction-to-ambient.
Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm.
Note 5: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to ground.
Note 7: The output PMOS structure contains a diode between the V and V
terminals. This diode is normally reverse biased. This diode will get forward biased
OUT
IN
if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp
of peak current.
Note 8: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load
regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only
the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.
Note 9: Error Flag threshold and hysteresis are specified as percentage of regulated output voltage.
Note 10: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage speci-
fication applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential, since
the minimum input voltage is 2.5V.
Note 11: This specification has been tested for −40˚C ≤ T ≤ 85˚C since the temperature rise of the device is negligible under shutdown conditions.
J
7
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Typical Performance Characteristics Unless otherwise specified, VIN = VO(NOM) + 1.5V, VOUT
=
2.5V, COUT = 10µF, IOUT = 10mA, CIN = 10µF, VSD = VIN, and TA = 25˚C.
Drop-Out Voltage Vs Temperature for Different Load
Currents
Drop-Out Voltage Vs Temperature for Different Output
Voltages (IOUT = 800mA)
DS101267-9
DS101267-10
Ground Pin Current Vs Input Voltage (VSD=VIN
)
Ground Pin Current Vs Input Voltage (VSD=100mV)
DS101267-11
DS101267-15
Ground Current Vs Temperature (VSD=VIN
)
Ground Current Vs Temperature (VSD=0V
DS101267-18
DS101267-12
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Typical Performance Characteristics Unless otherwise specified, VIN = VO(NOM) + 1.5V, VOUT
=
2.5V, COUT = 10µF, IOUT = 10mA, CIN = 10µF, VSD = VIN, and TA = 25˚C. (Continued)
Ground Pin Current Vs Shutdown Pin Voltage
Input Voltage Vs Output Voltage
DS101267-16
DS101267-17
Output Noise Density, VOUT= 2.5V
Output Noise Density, VOUT= 5V
DS101267-13
DS101267-14
9
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quency component and a high frequency component, which
depend strongly on the silicon area and quiescent current.
Noise can be reduced in two ways: by increasing the transis-
tor area or by increasing the current drawn by the internal
reference. Increasing the area will decrease the chance of
fitting the die into a smaller package. Increasing the current
drawn by the internal reference increases the total supply
current (ground pin current). Using an optimized trade-off of
ground pin current and die size, LP3963/LP3966 achieves
low noise performance and low quiescent current operation.
Applications Information
Input Capacitor Selection
The LP3963 and LP3966 require a minimum input capaci-
tance of 10µF between the input and ground pins to prevent
any impedance interactions with the supply. This capacitor
should be located very close to the VIN pin. This capacitor
can be of any type such as ceramic, tantalum, or low ESR
aluminium. Any good quality capacitor which has good toler-
ance over temperature and frequency is recommended.
The total output noise specification for LP3963/LP3966 is
presented in the Electrical Characteristics table. The Output
noise density at different frequencies is represented by a
curve under typical performance characteristics.
Output Capacitor Selection
The LP3963 and LP3966 require a minimum of 10µF capaci-
tance between the output and ground pins for proper opera-
tion. LP3963 and LP3966 work best with Tantalum or Elec-
trolytic capacitor. The output capacitor should have a good
tolerance over temperature, voltage, and frequency. Larger
capacitance provides better improved load dynamics and
noise performance. The output capacitor should be con-
nected very close to the Vout pin.
Short-Circuit Protection
The LP3963and LP3966 is short circuit protected and in the
event of a peak over-current condition, the short-circuit con-
trol loop will rapidly drive the output PMOS pass element off.
Once the power pass element shuts down, the control loop
will rapidly cycle the output on and off until the average
power dissipation causes the thermal shutdown circuit to re-
spond to servo the on/off cycling to a lower frequency.
Please refer to the section on thermal information for power
dissipation calculations.
Output Adjustment
An adjustable output device has output voltage range of
1.215V to 5.1V. To obtain a desired output voltage, the fol-
lowing equation can be used with R1 always a 10kΩ resistor.
Error Flag Operation
The LP3963/LP3966 produces a logic low signal at the Error
Flag pin when the output drops out of regulation due to low
input voltage, current limiting, or thermal limiting. This flag
has a built in hysteresis. The timing diagram in Figure 1
shows the relationship between the ERROR and the output
voltage. In this example, the input voltage is changed to
demonstrate the functionality of the Error Flag.
For output stability, CF must be between 68pF and 100pF.
Output Noise
Noise is specified in two ways-
Spot Noise or Output noise density is the RMS sum of all
noise sources, measured at the regulator output, at a spe-
cific frequency (measured with a 1Hz bandwidth). This type
of noise is usually plotted on a curve as a function of fre-
quency.
The internal Error flag comparator has an open drain output
stage. Hence, the ERROR pin should be pulled high through
a pull up resistor. Although the ERROR pin can sink current
of 1mA, this current is energy drain from the input supply.
Hence, the value of the pull up resistor should be in the
range of 10kΩ to 1MΩ. The ERROR pin must be con-
nected to ground if this function is not used. It should
also be noted that when the shutdown pin is pulled low, the
ERROR pin is forced to be invalid for reasons of saving
power in shutdown mode.
Total output Noise or Broad-band noise is the RMS sum
of spot noise over a specified bandwidth, usually several de-
cades of frequencies.
Attention should be paid to the units of measurement. Spot
√
√
noise is measured in units µV/ Hz or nV/ Hz and total output
noise is measured in µV(rms).
The primary source of noise in low-dropout regulators is the
internal reference. In CMOS regulators, noise has a low fre-
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Applications Information (Continued)
DS101267-7
FIGURE 1. Error Flag Operation
Sense Pin
tance. For example, in the case of a 3.3V output, if the trace
resistance is 100mΩ, the voltage at the remote load will be
3V with 3A of load current, ILOAD. The LP3966 regulates the
voltage at the sense pin. Connecting the sense pin to the re-
mote load will provide regulation at the remote load, as
shown in Figure 2. If the sense option pin is not required, the
sense pin must be connected to the VOUT pin.
In applications where the regulator output is not very close to
the load, LP3966 can provide better remote load regulation
using the SENSE pin. Figure 2 depicts the advantage of the
SENSE option. LP3963 regulates the voltage at the output
pin. Hence, the voltage at the remote load will be the regula-
tor output voltage minus the drop across the trace resis-
DS101267-8
FIGURE 2. Improving remote load regulation using LP3966
11
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θHA≤ θJA − θCH − θJC
.
Applications Information (Continued)
In this equation, θCH is the thermal resistance from the junc-
tion to the surface of the heat sink and θJC is the thermal re-
sistance from the junction to the surface of the case. θJC is
about 3˚C/W for a TO220 package. The value for θCH de-
pends on method of attachment, insulator, etc. θCH varies
between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,
2˚C/W can be assumed.
Shutdown Operation
A CMOS Logic level signal at the shutdown ( SD) pin will
turn-off the regulator. Pin SD must be actively terminated
through a 10kΩ pull-up resistor for a proper operation. If this
pin is driven from a source that actively pulls high and low
(such as a CMOS rail to rail comparator), the pull-up resistor
is not required. This pin must be tied to Vin if not used.
Heatsinking TO-263 Package
Dropout Voltage
The TO-263 package uses the copper plane on the PCB as
a heatsink. The tab of these packages are soldered to the
copper plane for heat sinking. Figure 3 shows a curve for the
θJA of TO-263 package for different copper area sizes, using
a typical PCB with 1 ounce copper and no solder mask over
the copper area for heat sinking.
The dropout voltage of a regulator is defined as the minimum
input-to-output differential required to stay within 2% of the
output voltage. The LP3963/LP3966 use an internal MOS-
FET with an Rds(on) of 240mΩ (typically). For CMOS LDOs,
the dropout voltage is the product of the load current and the
Rds(on) of the internal MOSFET.
Reverse Current Path
The internal MOSFET in LP3963and LP3966 has an inher-
ent parasitic diode. During normal operation, the input volt-
age is higher than the output voltage and the parasitic diode
is reverse biased. However, if the output is pulled above the
input in an application, then current flows from the output to
the input as the parasitic diode gets forward biased. The out-
put can be pulled above the input as long as the current in
the parasitic diode is limited to 200mA continuous and 1A
peak.
Maximum Output Current Capability
LP3963 and LP3966 can deliver a continuous current of 3A
over the full operating temperature range. A heatsink may be
required depending on the maximum power dissipation and
maximum ambient temperature of the application. Under all
possible conditions, the junction temperature must be within
the range specified under operating conditions. The total
power dissipation of the device is given by:
DS101267-32
FIGURE 3. θJA vs Copper(1 Ounce) Area for TO-263
package
As shown in the figure, increasing the copper area beyond 1
square inch produces very little improvement. The minimum
value for θJA for the TO-263 packag mounted to a PCB is
32˚C/W.
PD = (VIN−VOUT)IOUT+ (VIN)IGND
where IGND is the operating ground current of the device
(specified under Electrical Characteristics).
Figure 4 shows the maximum allowable power dissipation
for TO-263 packages for different ambient temperatures, as-
suming θJA is 35˚C/W and the maximum junction tempera-
ture is 125˚C.
The maximum allowable temperature rise (TRmax) depends
on the maximum ambient temperature (TAmax) of the appli-
cation, and the maximum allowable junction temperature(TJ
max):
-
TRmax = TJmax− TAmax
The maximum allowable value for junction to ambient Ther-
mal Resistance, θJA, can be calculated using the formula:
θJA = TRmax / PD
LP3963 and LP3966 are available in TO-220 and TO-263
packages. The thermal resistance depends on amount of
copper area or heat sink, and on air flow. If the maximum al-
lowable value of θJA calculated above is ≥ 60 ˚C/W for TO-
220 package and ≥ 60 ˚C/W for TO-263 package no heatsink
is needed since the package can dissipate enough heat to
satisfy these requirements. If the value for allowable θJA falls
below these limits, a heat sink is required.
Heatsinking TO-220 Package
DS101267-33
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θJA will
be same as shown in next section for TO263 package.
FIGURE 4. Maximum power dissipation vs ambient
temperature for TO-263 package
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
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Physical Dimensions inches (millimeters) unless otherwise noted
TO220 5-lead, Molded, Stagger Bend Package (TO220-5)
NS Package Number T05D
For Order Numbers, refer to the “Ordering Information” section of this document.
13
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
TO263 5-Lead, Molded, Surface Mount Package (TO263-5)
NS Package Number TS5B
For Order Numbers, refer to the “Ordering Information” section of this document.
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相关型号：
LP3966ET-ADJ/NOPB
IC VREG 1.216 V-5.1 V ADJUSTABLE POSITIVE LDO REGULATOR, 1.2 V DROPOUT, PZFM5, ROHS COMPLIANT, TO-220, 5 PIN, Adjustable Positive Single Output LDO Regulator
NSC
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