MM74C74M/A+ [NSC]
IC,FLIP-FLOP,DUAL,D TYPE,CMOS,SOP,14PIN,PLASTIC;
| 型号： | MM74C74M/A+ |
| 厂家： | 
National Semiconductor |
| 描述： | IC,FLIP-FLOP,DUAL,D TYPE,CMOS,SOP,14PIN,PLASTIC 触发器 |
| 文件： | 总6页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
MM54C74/MM74C74 Dual D Flip-Flop
General Description
Y
Low power
50 nW (typ.)
10 MHz (typ.)
with 10V supply
The MM54C74/MM74C74 dual D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors. Each flip-
flop has independent data, preset, clear and clock inputs
and Q and Q outputs. The logic level present at the data
input is transferred to the output during the positive going
transition of the clock pulse. Preset or clear is independent
of the clock and accomplished by a low level at the preset
or clear input.
Y
Medium speed operation
Applications
Y
Automotive
Y
Data terminals
Y
Instrumentation
Y
Medical electronics
Y
Alarm system
Features
Y
Y
Industrial electronics
Supply voltage range
3V to 15V
2
Drive 2 LPT L loads
Y
Remote metering
Y
Y
Tenth power TTL compatible
High noise immunity
Y
Computers
0.45 V
CC
(typ.)
Logic Diagram
TL/F/5885–1
Truth Table
Connection Diagram
Dual-In-Line Package
Preset
Clear
Q
n
Q
n
0
0
1
1
0
1
0
1
0
0
1
0
0
1
*Q
*Q
n
n
*No change in output from previous state.
Order Number MM54C74 or MM74C74
TL/F/5885–2
Top View
Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’.
A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’.
C
1995 National Semiconductor Corporation
TL/F/5885
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
a
65 C to 150 C
Storage Temperature Range
§
§
Power Dissipation
Dual-In-Line
Small Outline
700 mW
500 mW
b
a
0.3V
Voltage at Any Pin (Note 1)
0.3V to V
CC
Operating Temperature Range
MM54C74
MM74C74
Lead Temperature (Soldering, 10 seconds)
Operating V Range
260 C
§
3V to 15V
18V
b
b
a
a
55 C to 125 C
§
§
40 C to 85 C
CC
§
§
V
(Max)
CC
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
e
e
e
e
e
e
e
e
e
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
5V
3.5
80
V
V
IN(1)
10V
5V
1.5
2.0
V
IN(0)
10V
5V
V
4.5
9.0
V
OUT(1)
OUT(0)
10V
5V
V
0.5
1.0
1.0
V
10V
15V
15V
15V
V
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
mA
mA
mA
IN(1)
IN(0)
CC
b
1.0
0.05
60
CMOS/LPTTL INTERFACE
e
CC
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C, V
74C, V
4.5V
4.75V
IN(1)
b
V
1.5
CC
e
CC
e
e
54C, V
74C, V
4.75V
4.75V
IN(0)
CC
CC
0.8
0.4
V
V
V
e
e
e b
4.5V, I
D
4.75V, I
54C, V
74C, V
360 mA
e b
OUT(1)
OUT(0)
CC
CC
2.4
360 mA
e
360 mA
D
e
e
54C, V
74C, V
4.5V, I
D
4.75V, I
CC
CC
e
360 mA
D
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
e
CC
e
e
I
I
I
I
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
T
5V, V
IN(0)
0V
0V
SOURCE
SOURCE
SINK
b
1.75
mA
mA
mA
mA
e
25 C, V
§
10V, V
A
OUT
e
e
0V
V
CC
IN(0)
b
8.0
1.75
8.0
e
e
T
25 C, V
§
0V
A
OUT
e
e
e
V
T
5V, V
IN(1)
5V
V
CC
e
25 C, V
§
10V, V
A
OUT
CC
e
e
10V
V
CC
SINK
IN(1)
e
e
T
25 C, V
V
CC
§
A
OUT
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
e
e
50 pF, unless otherwise noted
AC Electrical Characteristics* T
25 C, C
§
A
L
Symbol
Parameter
Input Capacitance
Propagation Delay Time to a
Logical ‘‘0’’ t or Logical ‘‘1’’
Conditions
Min
Typ
Max
Units
C
IN
Any Input (Note 2)
5.0
pF
e
e
t
pd
V
V
5V
180
70
300
110
ns
ns
CC
10V
pd0
from Clock to Q or Q
CC
t
pd1
e
e
t
t
t
t
t
t
Propagation Delay Time to a
V
V
5V
180
70
300
110
ns
ns
pd
CC
Logical ‘‘0’’ from Preset or Clear
10V
CC
e
e
Propagation Delay Time to a
V
V
5V
250
100
400
150
ns
ns
pd
CC
Logical ‘‘1’’ from Preset or Clear
10V
CC
e
e
, t
S0 S1
Time Prior to Clock Pulse that
V
V
5V
100
40
50
20
ns
ns
CC
Data Must be Present t
SETUP
10V
CC
e
e
b
20
, t
H0 H1
Time after Clock Pulse that
Data Must be Held
V
V
5V
0
0
ns
ns
CC
b
10V
8.0
CC
e
e
Minimum Clock Pulse
e
V
V
5V
100
40
250
100
ns
ns
PW1
PW2
CC
Width (t
t
)
10V
WL
WH
CC
e
e
Minimum Preset and
Clear Pulse Width
V
V
5V
100
40
160
70
ns
ns
CC
10V
CC
e
e
t , t
r f
Maximum Clock Rise
and Fall Time
V
V
5V
15.0
5.0
ms
ms
CC
10V
CC
e
e
f
Maximum Clock Frequency
V
V
5V
2.0
5.0
3.5
8.0
MHz
MHz
MAX
CC
10V
CC
C
PD
Power Dissipation Capacitance
(Note 3)
40
pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application
PD
NoteÐAN-90.
Switching Time Waveform
CMOS to CMOS
TL/F/5885–3
e
e
t
t
20 ns
r
f
3
AC Test Circuit
TL/F/5885–4
Typical Applications
n
Ripple Counter (Divide by 2 )
TL/F/5885–5
Shift Register
TL/F/5885–6
Guaranteed Noise Margin
as a Function of V
CC
74C Compatibility
TL/F/5885–7
TL/F/5885–8
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C74J or MM74C74J
NS Package Number J14A
5
Physical Dimensions inches (millimeters) (Continued)
Ceramic Dual-In-Line Package (J)
Order Number MM54C74N or MM74C74N
NS Package Number N14A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
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