M36W432T85ZA1T [NUMONYX]
Memory Circuit, 2MX16, CMOS, PBGA66, 0.80 MM PITCH, STACK, LFBGA-66;型号: | M36W432T85ZA1T |
厂家: | NUMONYX B.V |
描述: | Memory Circuit, 2MX16, CMOS, PBGA66, 0.80 MM PITCH, STACK, LFBGA-66 静态存储器 内存集成电路 |
文件: | 总57页 (文件大小:418K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M36W432T
M36W432B
32 Mbit (2Mb x16, Boot Block) Flash Memory
and 4 Mbit (256K x16) SRAM, Multiple Memory Product
PRODUCT PREVIEW
FEATURES SUMMARY
■ SUPPLY VOLTAGE
SRAM
■ 4 Mbit (256K x 16 bit)
■ ACCESS TIME: 70ns
– V
– V
– V
= 2.7V to 3.3V
DDF
DDS
PPF
= V
= 2.7V to 3.3V
DDQF
■ LOW V
DATA RETENTION: 1.5V
DDS
= 12V for Fast Program (optional)
■ POWER DOWN FEATURES USING TWO
■ ACCESS TIME: 70,85ns
CHIP ENABLE INPUTS
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
Figure 1. Packages
– Manufacturer Code: 20h
– Top Device Code, M36W432T: 88BAh
– Bottom Device Code, M36W432B: 88BBh
FLASH MEMORY
■ 32 Mbit (2Mb x16) BOOT BLOCK
FBGA
– 8 x 4 KWord Parameter Blocks (Top or
Bottom Location)
■ PROGRAMMING TIME
– 10µs typical
Stacked LFBGA66 (ZA)
8 x 8 ball array
– Double Word Programming Option
■ BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
■ AUTOMATIC STAND-BY MODE
■ PROGRAM and ERASE SUSPEND
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ SECURITY
– 64 bit user programmable OTP cells
– 64 bit unique device identifier
– One parameter block permanently lockable
February 2002
1/57
This is preliminary information on a new product now in development. Details are subject to change without notice.
M36W432T, M36W432B
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Flash Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Flash Security Block Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SRAM Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Read Block Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 17
Flash Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Flash Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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M36W432T, M36W432B
Figure 10. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12. Flash Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Flash Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13. SRAM Read AC Waveforms, Address Controlled with UBS = LBS = V . . . . . . . . . . . 31
IL
Figure 14. SRAM Read AC Waveforms, E1S, E2S or GS Controlled. . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. SRAM Write AC Waveforms, WS Controlled with GS High . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. SRAM Write AC Waveforms, UBS and LBS Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. SRAM Low V
Figure 21. SRAM Low V
Data Retention AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . 36
Data Retention AC Waveforms, E2S Controlled . . . . . . . . . . . . . . . . 36
Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DDS
DDS
DDS
Table 21. SRAM Low V
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline. . . . 37
Table 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data . . . . . . . 37
Figure 23. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . 38
Figure 24. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)39
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 23. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26. Top Boot Block Addresses, M36W432T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 27. Bottom Boot Block Addresses, M36W432B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 28. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 30. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 31. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
APPENDIX C. FLASH MEMORY FLOWCHARTS and PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . 49
3/57
M36W432T, M36W432B
Figure 25. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 27. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 51
Figure 28. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 30. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
APPENDIX D. FLASH MEMORY COMMAND INTERFACE and PROGRAM/ERASE CONTROLLER
STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. Write State Machine Current/Next, sheet 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 35. Write State Machine Current/Next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4/57
M36W432T, M36W432B
SUMMARY DESCRIPTION
The M36W432 is a low voltage Multiple Memory
Product which combines two memory devices; a
32 Mbit boot block Flash memory and a 4 Mbit
SRAM. Recommended operating conditions do
not allow both the Flash and the SRAM to be ac-
tive at the same time.
Table 1. Signal Names
A0-A17
Address Inputs
A18-A20
DQ0-DQ15
Address Inputs for Flash Chip only
Data Input/Output
The memory is offered in a Stacked LFBGA66 (0.8
mm pitch) package and is supplied with all the bits
erased (set to ‘1’).
V
Flash Power Supply
DDF
V
Flash Power Supply for I/O Buffers
DDQF
Flash Optional Supply Voltage for Fast
Program & Erase
V
PPF
Figure 2. Logic Diagram
V
V
V
Flash Ground
SSF
DDS
SSS
SRAM Power Supply
SRAM Ground
V
V
DDQF
V
DDS
V
DDF
PPF
NC
Not Connected Internally
21
16
Flash control functions
A0-A20
DQ0-DQ15
EF
Chip Enable input
EF
GF
GF
Output Enable input
Write Enable input
Reset input
WF
RPF
WPF
WF
RPF
WPF
M36W432T
M36W432B
Write Protect input
SRAM control functions
E1S
E2S
GS
E1S, E2S
GS
Chip Enable inputs
Output Enable input
Write Enable input
WS
WS
UBS
LBS
UBS
Upper Byte Enable input
Lower Byte Enable input
LBS
V
V
SSS
SSF
AI05200
5/57
M36W432T, M36W432B
Figure 3. LFBGA Connections (Top view through package)
7
8
#3
#4
#1
#2
1
2
3
4
5
6
A15
A10
A14
A9
A
B
C
D
E
F
NC
A20
A16
WF
A11
A8
A13
A12
WS
V
V
NC
NC
NC
SSF
DDQF
DQ15
DQ13
DQ12
DQ14
DQ4
DQ7
NC
DQ6
E2S
DQ10
DQ8
A2
DQ5
RPF
V
V
V
SSS
DDS
DDF
WPF
V
A19
GS
A7
DQ11
DQ2
DQ0
A1
DQ3
PPF
LBS
A18
NC
UBS
DQ9
A3
DQ1
E1S
NC
G
H
A17
A5
A6
A0
NC
A4
EF
V
NC
GF
NC
NC
SSF
AI05201
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Address Inputs (A0-A17). Addresses A0-A17
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (EF) and Write
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V and Reset is at V the device
IL
IH
is in active mode. When Chip Enable is at V the
IH
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
standby level.
Flash Output Enable (GF). The Output Enable
controls the data outputs during the Bus Read op-
eration of the Flash memory.
Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (WF) signals
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memory’s Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable, EF, or Write Enable, WF, whichever oc-
curs first.
6/57
M36W432T, M36W432B
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
V
Supply Voltage (2.7V to 3.3V). V
pro-
DDF
DDF
vides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
for each block. When Write Protect is at V , the
IL
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
V
V
and V
Supply Voltage (2.7V to 3.3V).
DDS
DDQF
is at V , the Lock-Down is disabled and the block
IH
provides the power supply for the Flash
DDQF
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RPF). The Reset input provides a
memory I/O pins and V
supply for the SRAM control pins. This allows all
Outputs to be powered independently from the
Flash core power supply, V
to V
provides the power
DDS
hardware reset of the Flash memory. When Reset
. V
can be tied
DDF DDQF
is at V , the memory is in reset mode: the outputs
IL
DDS
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
V
Program Supply Voltage. V
is both a
PPF
PPF
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt-
Locked state. When Reset is at V , the device is
IH
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
SRAM Chip Enable (E1S, E2S). The Chip En-
able inputs activate the SRAM memory control
age V
and the Program Supply Voltage V
DDF
PPF
can be applied in any order.
If V is kept in a low voltage range (0V to 3.6V)
V
age lower than V
against program or erase, while V
ables these functions (see Table 14, DC Charac-
teristics for the relevant values). V is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
PPF
PPF
is seen as a control input. In this case a volt-
gives an absolute protection
PPLK
logic, input buffers and decoders. E1S at V or
IH
> V
en-
PPF
PPLK
E2S at V deselects the memory and reduces the
IL
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
PPF
SRAM memory array, while WS remains at V It
IL.
is not allowed to set EF at V E1S at V and E2S
IL,
IL
at V at the same time.
IH
SRAM Write Enable (WS). The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is ac-
tive low.
If V
is in the range 11.4V to 12.6V it acts as a
PPF
power supply pin. In this condition V
stable until the Program/Erase algorithm is com-
pleted (see Table 16 and 17).
must be
PPF
V
and V
Ground. V
and V
are the
SSS
SSF
SSS
SSF
ground reference for all voltage measurements in
the Flash and SRAM chips, respectively.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is active low.
Note: Each device in a system should have V
DF DDQF
pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the re-
D-
, V
and V
decoupled with a 0.1µF ca-
PPF
quired V
program and erase currents.
PPF
7/57
M36W432T, M36W432B
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF for the Flash mem-
ory and, E1S and E2S for the SRAM.
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
simultaneous read operations on the Flash and
the SRAM which would result in a data bus con-
tention. Therefore it is recommended to put the
SRAM in the high impedance state when reading
the Flash and vice versa (see Table 2 Main Oper-
ation Modes for details).
Figure 4. Functional Block Diagram
V
V
V
V
PPF
DDQF
DDF
EF
GF
WF
RPF
WPF
Flash Memory
32 Mbit (x16)
A18-A20
A0-A17
DQ0-DQ15
V
SSF
V
DDS
E1S
E2S
SRAM
GS
4 Mbit (x16)
WS
UBS
LBS
V
SSS
AI05202
8/57
M36W432T, M36W432B
Table 2. Main Operation Modes
Operation
(1)
DQ15-DQ0
UBS, LBS
V
PPF
EF
GF WF RPF WPF
E1S E2S GS WS
Mode
Data
Output
V
V
V
V
Read
X
Don't care
or
SRAM must be disabled
IL
IL
IH
IH
IH
V
DDF
V
V
IH
V
V
V
IH
Write
SRAM must be disabled
Data Input
IL
IL
V
PPFH
Block
Locking
V
V
V
V
IL
X
X
Don't care
SRAM must be disabled
X
IL
IH
V
IH
Standby
Reset
X
X
X
X
X
Don't care
Don't care
Any SRAM mode is allowed
Any SRAM mode is allowed
Hi-Z
Hi-Z
IH
V
X
X
X
IL
Output
Disable
V
V
IH
V
IH
V
IH
Don't care
Any SRAM mode is allowed
Hi-Z
IL
Data out
Word Read
V
V
V
V
V
Read
Write
Flash must be disabled
Flash must be disabled
IL
IH
IH
IL
IH
IL
IL
Data in
Word Write
V
V
V
V
V
IL
V
IL
IH
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
Standby/
Power
Down
V
Any Flash mode is allowable
Any Flash mode is allowable
X
X
X
X
X
X
X
X
X
X
X
X
IL
V
X
X
IH
V
X
X
X
IH
Data
Retention
V
X
X
IL
V
X
IH
Output
Disable
V
IL
V
IH
V
V
IH
Any Flash mode is allowable
Note: X = V or V , V = 12V ± 5%.
PPFH
X
Hi-Z
IH
IL
IH
1. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
9/57
M36W432T, M36W432B
Flash Memory Component
The Flash Memory is a 32 Mbit (2 Mbit x 16) de-
vice that can be erased electrically at the block
level and programmed in-system on a Word-by-
Word basis. These operations can be performed
using a single low voltage (2.7 to 3.3V) supply
against program or erase. All blocks are locked at
Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
and the V
for device I/0 operation feature the
DDQF
same voltage range. An optional 12V V
power
PPF
supply is provided to speed up customer pro-
gramming.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divid-
ed into two 64 bit segments, the first one contains
a unique device number written by ST, while the
second one is one-time-programmable by the us-
er. The user programmable segment can be per-
manently protected. The Security Block,
parameter block 0, can be permanently protected
by the user. Figure 6, shows the Flash Security
Block Memory Map.
The device features an asymmetrical blocked ar-
chitecture with an array of 71 blocks: 8 Parameter
Blocks of 4 KWord and 63 Main Blocks of 32
KWord. The M36W432T device has the Flash
Memory Parameter Blocks at the top of the mem-
ory address space while the M36W432B device lo-
cates the Parameter Blocks starting from the
bottom. The memory maps are shown in Figure 5,
Block Addresses.
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
When V
≤ V
all blocks are protected
PPF
PPLK
10/57
M36W432T, M36W432B
Figure 5. Flash Block Addresses
Top Boot Block Addresses
Bottom Boot Block Addresses
1FFFFF
4 KWords
1FF000
1FFFFF
32 KWords
32 KWords
1F8000
1F7FFF
Total of 8
4 KWord Blocks
1F0000
Total of 63
32 KWord Blocks
1F8FFF
4 KWords
1F8000
1F7FFF
32 KWords
1F0000
00FFFF
32 KWords
4 KWords
008000
007FFF
Total of 63
007000
32 KWord Blocks
Total of 8
00FFFF
4 KWord Blocks
32 KWords
008000
007FFF
000FFF
000000
32 KWords
4 KWords
000000
AI05203
Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses.
Figure 6. Flash Security Block Memory Map
88h
User Programmable OTP
85h
84h
Parameter Block # 0
Unique device number
81h
80h
Protection Register Lock
2
1
0
AI05204
SRAM Component
cess time of 70 ns in all conditions. The memory
operations can be performed using a single low
voltage supply, 2.7V to 3.3V, which is the same as
the Flash voltage supply.
The SRAM is an 4 Mbit asynchronous random ac-
cess memory which features a super low voltage
operation and low current consumption with an ac-
11/57
M36W432T, M36W432B
OPERATING MODES
Flash Bus Operations
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 2, Main Operation Modes, for a
summary.
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable
is Low, V , the memory is deselected and the out-
IL
puts are high impedance. The memory is in Reset
mode when Reset is at V . The power consump-
IL
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
able inputs. If Reset is pulled to V
during a Pro-
SSF
gram or Erase, this operation is aborted and the
memory content is no longer valid.
Flash Command Interface
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Pro-
gram/Erase states. See Appendix 29, Table 34,
Write State Machine Current/Next, for a summary
of the Command Interface.
able must be at V in order to perform a read op-
IL
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 9, Read Mode AC Waveforms, and Table
15, Flash Read AC Characteristics, for details of
when the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
set or whenever V
is lower than V
. Com-
DDF
LKO
and Write Enable are at V with Output Enable at
IL
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 3, Commands,
in conjunction with the text descriptions below.
V . Commands, Input Data and Addresses are
IH
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
See Figures 10 and 11, Write AC Waveforms, and
Tables 16 and 17, Flash Write AC Characteristics,
for details of the timing requirements.
Read Memory Array Command. The
Read
command returns the memory to its Read mode.
One Bus Write cycle is required to issue the Read
Memory Array command and return the memory to
Read mode. Subsequent read operations will read
the addressed location and output the data. When
a device Reset occurs, the memory defaults to
Read mode.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at V .
IH
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable is at V and the device is in
IH
Read Status Register Command. The Status
Register indicates when a program or erase oper-
ation is complete and the success or failure of the
operation itself. Issue a Read Status Register
command to read the Status Register’s contents.
Subsequent Bus Read operations read the Status
Register at any address, until another command is
issued. See Table 10, Status Register Bits, for de-
tails on the definitions of the bits.
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con-
tent of the Status Register.
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V
during a program or erase operation, the de-
IH
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, V , and the supply
IL
current is reduced to I
. The data Inputs/Out-
DD1
12/57
M36W432T, M36W432B
Read Electronic Signature Command. The
Read Electronic Signature command reads the
Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protec-
tion and Lock Register. See Tables 4, 5 and 6 for
the valid address.
■ The first bus cycle sets up the Program
command.
■ The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in Table 7, Program, Erase
Times and Program/Erase Endurance Cycles.
Read CFI Query Command. The Read Query
Command is used to read data from the Common
Flash Interface (CFI) Memory Area, allowing pro-
gramming equipment or applications to automati-
cally match their interface to the characteristics of
the device. One Bus Write cycle is required to is-
sue the Read Query Command. Once the com-
mand is issued subsequent Bus Read operations
read from the Common Flash Interface Memory
Area. See Appendix B, Common Flash Interface,
Tables 28, 29, 30, 31, 32 and 33 for details on the
information contained in the Common Flash Inter-
face memory area.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. It sets all the
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the Status Register
will output the error.
Programming aborts if Reset goes to V . As data
IL
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix C, Figure 25, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program Command. This feature
is offered to improve the programming throughput,
writing a page of two adjacent words in paral-
lel.The two words must differ only for the address
A0. Programming should not be attempted when
V
is not at V
. The command can be execut-
but the result is not guar-
PPH
PPF
PPH
ed if V
is below V
PPF
anteed.
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
Two Bus Write cycles are required to issue the
command.
the Data of the first word to be written.
■ The first bus cycle sets up the Erase command.
■ The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
■ The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
ming aborts if Reset goes to V . As data integrity
IL
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 26, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
Erase aborts if Reset turns to V . As data integrity
IL
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table 7, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See Appendix C, Figure 28, Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.
Clear Status Register Command. The
Clear
Status Register command can be used to reset
bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
bus write cycle is required to issue the Clear Sta-
tus Register command.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program Command. The memory array can be
programmed word-by-word. Two bus write cycles
are required to issue the Program Command.
13/57
M36W432T, M36W432B
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command is used to pause
a Program or Erase operation. One bus write cycle
is required to issue the Program/Erase command
and pause the Program/Erase controller.
■ The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron-
ic Signature and Read CFI Query commands. Ad-
ditionally, if the suspend operation was Erase then
the Program, Block Lock, Block Lock-Down or
Protection Program commands will also be ac-
cepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protec-
tion Program commands. When the Program/
Erase Resume command is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.
The segment can be protected by programming bit
1 of the Protection Lock Register. Bit 1 of the Pro-
tection Lock Register protects bit 2 of the Protec-
tion Lock Register. Programming bit 2 of the
Protection Lock Register will result in a permanent
protection of the Security Block (see Figure 6,
Flash Security Block Memory Map). Attempting to
program a previously protected Protection Regis-
ter will result in a Status Register error. The pro-
tection of the Protection Register and/or the
Security Block is not reversible.
The Protection Register Program cannot be sus-
pended.
Block Lock Command. The Block Lock com-
mand is used to lock a block and prevent Program
or Erase operations from changing the data in it.
All blocks are locked at power-up or reset.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Enable to V . Program/Erase is aborted if
IH
Reset turns to V .
IL
See Appendix C, Figure 27, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, and Figure 29, Erase Suspend &
Resume Flowchart and Pseudo Code for flow-
charts for using the Program/Erase Suspend com-
mand.
Two Bus Write cycles are required to issue the
Block Lock command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latches the block
address.
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
The Lock Status can be monitored for each block
using the Read Block Signature command. Table.
9 shows the Lock Status after issuing a Block Lock
command.
The Block Lock bits are volatile, once set they re-
main set until reset or power-down/power-up.
They are cleared by a Blocks Unlock command.
Refer to the section, Block Locking, for a detailed
explanation.
Block Unlock Command. The Blocks Unlock
command is used to unlock a block, allowing the
block to be programmed or erased. Two Bus Write
cycles are required to issue the Blocks Unlock
command.
start the Program/Erase Controller after
a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the com-
mand. Once the command is issued subsequent
Bus Read operations read the Status Register.
See Appendix C, Figure 27, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, and Figure 29, Erase Suspend &
Resume Flowchart and Pseudo Code for flow-
charts for using the Program/Erase Resume com-
mand.
Protection Register Program Command. The
Protection Register Program command is used to
Program the 64 bit user One-Time-Programmable
(OTP) segment of the Protection Register. The
segment is programmed 16 bits at a time. When
shipped all bits in the segment are set to ‘1’. The
user can only program the bits to ‘0’.
■ The first bus cycle sets up the Block Unlock
command.
■ The second Bus Write cycle latches the block
address.
The Lock Status can be monitored for each block
using the Read Block Signature command. Table.
9 shows the Lock Status after issuing a Block Un-
lock command. Refer to the section, Block Lock-
ing, for a detailed explanation.
Two write cycles are required to issue the Protec-
tion Register Program command.
■ The first bus cycle sets up the Protection
Register Program command.
14/57
M36W432T, M36W432B
Block Lock-Down Command. A locked block
cannot be Programmed or Erased, or have its
■ The second Bus Write cycle latches the block
address.
Lock status changed when WP is low, V . When
IL
The Lock Status can be monitored for each block
using the Read Block Signature command.
Locked blocks revert to the protected (and not
locked) state when the device is reset on power-
down. Table. 9 shows the Lock Status after issuing
a Block Lock-Down command. Refer to the sec-
tion, Block Locking, for a detailed explanation.
WP is high, V the Lock-Down function is dis-
IH,
abled and the locked blocks can be individually un-
locked by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock command.
■ The first bus cycle sets up the Block Lock
command.
Table 3. Commands
Bus Write Operations
No. of
Cycles
1st Cycle
2nd Cycle
Addr
3nd Cycle
Addr
Commands
Bus
Op.
Bus
Op.
Bus
Op.
Addr Data
Data
Data
Read
Addr
Read Memory Array
Read Status Register
1+
1+
Write
Write
X
X
FFh
70h
Data
Read
Read
Status
Register
X
Signature
Read Electronic Signature
1+
Write
X
90h
Read
Signature
(1)
Addr
Read CFI Query
Erase
1+
2
Write
Write
55h
X
98h
20h
Read
Write
CFI Addr
Query
D0h
Block
Addr
40h or
10h
Program
2
3
Write
Write
X
X
Write
Write
Addr
Data Input
Data
Input
(2)
30h
Addr 1
Data Input Write
Addr 2
Double Word Program
Clear Status Register
Program/Erase Suspend
Program/Erase Resume
1
1
1
Write
Write
Write
X
X
X
50h
B0h
D0h
Block
Address
Block Lock
2
2
2
2
Write
Write
Write
Write
X
X
X
X
60h
60h
60h
C0h
Write
Write
Write
Write
01h
D0h
Block
Address
Block Unlock
Block Lock-Down
Block
Address
2Fh
Protection Register
Program
Data Input
Address
Note: X = Don't Care.
1. The signature addresses are listed in Tables 4, 5 and 6.
2. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.
15/57
M36W432T, M36W432B
Table 4. Read Electronic Signature
Code
Device
EF GF WF A0 A1 A2-A7
A8-A11
A12-A20 DQ0-DQ7 DQ8-DQ15
Manufacture
Code
V
V
IL
V
IH
V
IL
V
IL
0
Don't Care Don't Care
20h
00h
IL
V
V
V
V
V
V
V
V
V
M36W432T
M36W432B
0
0
Don't Care Don't Care
Don't Care Don't Care
xxh
xxh
88h
88h
IL
IL
IL
IH
IH
IH
IL
Device
Code
V
IL
IH
IL
Note: RPF = V
.
IH
Table 5. Read Block Signature
Block Status
Locked Block
EF
GF WF A0
A1 A2-A7
A8-A20
A12-A20
DQ0 DQ1 DQ2-DQ15
V
IL
V
V
V
V
V
0
0
Don't Care Block Address
Don't Care Block Address
1
0
0
0
00h
00h
IL
IL
IH
IH
IL
IL
IH
IH
V
V
V
V
Unlocked Block
IL
Locked-Down
Block
(1)
V
V
IL
V
V
IL
V
IH
0
Don't Care Block Address
1
00h
IL
IH
X
Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0"; see Block Locking section.
Table 6. Read Protection Register and Lock Register
Word
EF GF WF A0-A7
A8-A20
DQ0
DQ1
DQ2
DQ3-DQ7 DQ8-DQ15
OTP Prot.
data
Security
V
V
V
Lock
80h Don't Care
0
00h
00h
IL
IL
IH
prot. data
ID data
ID data
ID data
ID data
V
V
V
V
V
V
V
V
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
81h Don't Care
82h Don't Care
83h Don't Care
84h Don't Care
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
IL
IL
IL
IL
IL
IL
IL
IL
ID data
ID data
85h Don't Care OTP data
86h Don't Care OTP data
87h Don't Care OTP data
88h Don't Care OTP data
OTP data
OTP data
OTP data
OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP 1
OTP 2
OTP 3
16/57
M36W432T, M36W432B
Table 7. Program, Erase Times and Program/Erase Endurance Cycles
Flash Memory
Parameter
Test Conditions
Unit
Min
Typ
10
Max
200
200
5
V
= V
DDF
Word Program
µs
PPF
V
V
= 12V ±5%
= 12V ±5%
= V
Double Word Program
Main Block Program
10
µs
PPF
0.16
0.32
0.02
0.04
1
s
PPF
V
5
s
PPF
DDF
V
V
V
= 12V ±5%
4
s
PPF
Parameter Block Program
Main Block Erase
V
= V
4
s
PPF
DDF
= 12V ±5%
10
10
10
10
s
PPF
V
= V
1
s
PPF
DDF
= 12V ±5%
0.8
0.8
s
s
PPF
Parameter Block Erase
V
= V
PPF
DDF
Program/Erase Cycles (per Block)
100,000
cycles
Flash Block Locking
Unlocked State. Unlocked blocks (states (0,0,0),
(1,0,0) (1,1,0)), can be programmed or erased. All
unlocked blocks return to the Locked state when
the device is reset or powered-down. The status of
an unlocked block can be changed to Locked or
Locked-Down using the appropriate software
commands. A locked block can be unlocked by is-
suing the Unlock command.
Lock-Down State. Blocks that are Locked-Down
(state (0,1,1))are protected from program and
erase operations (as for Locked blocks) but their
Lock status cannot be changed using software
commands alone. A Locked or Unlocked block can
be Locked-Down by issuing the Lock-Down com-
mand. Locked-Down blocks revert to the Locked
state when the device is reset or powered-down.
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.
■ Lock/Unlock - this first level allows software-
only control of block locking.
■ Lock-Down - this second level requires
hardware interaction before locking can be
changed.
■ V
≤ V
- the third level offers a complete
PPLK
PPF
hardware protection against program and erase
on all blocks.
The locking status of each block can be set to
Locked, Unlocked, and Lock-Down. The following
sections explain the operation of the locking sys-
tem. Table 7, defines all of the possible locking
states (WP, DQ1, DQ0), and Appendix C, Figure
30, shows a flowchart for the locking operations.
The Lock-Down function is dependent on the WPF
input pin. When WPF=0 (V ), the blocks in the
IL
Lock-Down state (0,1,1) are protected from pro-
gram, erase and lock status changes. When
WPF=1 (V ) the Lock-Down function is disabled
Locked State. The default status of all blocks on
power-up or reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase oper-
ations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software com-
mands. An Unlocked block can be Locked by issu-
ing the Lock command.
IH
(1,1,1) and Locked-Down blocks can be individu-
ally unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WPF
remains high. When WPF is low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,1) regardless of any changes made
while WPF was high. Device reset or power-down
resets all blocks, including those in Lock-Down, to
the Locked state.
17/57
M36W432T, M36W432B
Reading a Block’s Lock Status. The lock status
of every block can be read in the Read Electronic
Signature mode of the device. To enter this mode
write 90h to the device. Subsequent reads at Block
Address 00002h will output the lock status of that
block. The lock status is represented by DQ0 and
DQ1. DQ0 indicates the Block Lock/Unlock status
and is set by the Lock command and cleared by
the Unlock command. it is also automatically set
when entering Lock-Down. DQ1 indicates the
Lock-Down status and is set by the Lock-Down
command. It cannot be cleared by software, only
by a device reset or power-down.
To change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After complet-
ing any desired lock, read, or program operations,
resume the erase operation with the Erase Re-
sume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking Operations During Erase Suspend.
Locking operations cannot be performed during a
program suspend. Refer to Appendix D, Com-
mand Interface and Program/Erase Controller
State, for detailed information on which com-
mands are valid during erase suspend.
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
Table 8. Block Lock Status
Item
Address
Data
Block Lock Configuration
Block is Unlocked
xx002
LOCK
DQ0=0
DQ0=1
DQ1=1
Block is Locked
Block is Locked-Down
Table 9. Lock Status
Current
(1)
Next Lock Status
(WPF, DQ1, DQ0)
(1)
Lock Status
(WPF, DQ1, DQ0)
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
Program/Erase
After
WPF transition
Current State
Allowed
1,0,0
yes
no
1,0,1
1,0,1
1,1,1
1,1,1
0,0,1
0,0,1
1,0,0
1,0,0
1,1,0
1,1,0
0,0,0
0,0,0
1,1,1
1,1,1
1,1,1
1,1,1
0,1,1
0,1,1
0,0,0
0,0,1
0,1,1
0,1,1
1,0,0
1,0,1
(2)
1,0,1
1,1,0
1,1,1
0,0,0
yes
no
yes
no
(2)
0,0,1
(3)
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = V and A0 = V
.
IL
IH
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.
3. A WPF transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.
IH
18/57
M36W432T, M36W432B
Flash Status Register
pend command being issued therefore the memo-
ry may still complete the operation rather than
entering the Suspend mode.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
The Status Register provides information on the
current or previous Program or Erase operation.
The various bits convey information and errors on
the operation. To read the Status register the
Read Status Register command can be issued, re-
fer to Read Status Register Command section. To
output the contents, the Status Register is latched
on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
or Output Enable returns to V . Either Chip En-
able or Output Enable must be toggled to update
the latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in
Table 10, Status Register Bits. Refer to Table 10
in conjunction with the following text descriptions.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Pro-
gram/Erase Controller is inactive, and the device
is ready to process a new command.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg-
ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set to ‘1’), the Program/
Erase Controller has applied the maximum num-
ber of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Sta-
tus bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the byte and still failed to ver-
ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new command is issued, otherwise the new
command will appear to fail.
IH
V
Status (Bit 3). The V
Status bit can be
PPF
PPF
used to identify an invalid voltage on the V
pin
PPF
during Program and Erase operations. The V
PPF
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
After the Program/Erase Controller completes its
cur if V
becomes invalid during an operation.
PPF
operation the Erase Status, Program Status, V
PPF
Status and Block Lock Status bits should be tested
for errors.
When the V
voltage on the V
voltage; when the V
Status bit is Low (set to ‘0’), the
PPF
pin was sampled at a valid
PPF
Status bit is High (set to
PPF
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended or is going to be suspended.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro-
gram/Erase Resume command.
The Erase Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30µs of the Program/Erase Sus-
‘1’), the V
pin has a voltage that is below the
PPF
V
Lockout Voltage, V
, the memory is pro-
PPLK
PPF
tected and Program and Erase operations cannot
be performed.
Once set High, the V
Status bit can only be re-
PPF
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
19/57
M36W432T, M36W432B
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command. The Program Suspend Status
should only be considered valid when the Pro-
gram/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set within 5µs of
the Program/Erase Suspend command being is-
sued therefore the memory may still complete the
operation rather than entering the Suspend mode.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Table 10. Status Register Bits
Bit
Name
Logic Level
Definition
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Ready
7
P/E.C. Status
Busy
Suspended
6
5
4
3
2
Erase Suspend Status
Erase Status
In progress or Completed
Erase Error
Erase Success
Program Error
Program Status
Program Success
V
V
Invalid, Abort
OK
PPF
V
PPF
Status
PPF
Suspended
Program Suspend Status
In Progress or Completed
Program/Erase on protected block, Abort
No operation to protected blocks
1
0
Block Protection Status
Reserved
Note: Logic level '1' is High, '0' is Low.
SRAM Operations
V , Chip Enable, E2S, is at V , and Byte Enables,
IL IH
UBS and LBS are at V .
IL
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Valid data will be available on the output pins after
a time of t after the last stable address. If the
AVQV
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
er than the address. Data out may be indetermi-
, t
, or t
) rath-
E1LQV E2HQV
GLQV
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
nate at t , t and t , but data lines
E1LQX E2HQX
GLQX
mode whenever Write Enable, WS, is at V , Out-
IH
will always be valid at t
13 and 14).
(see Table 19, Figures
AVQV
put Enable, GS, is at V , Chip Enable, E1S, is at
IL
20/57
M36W432T, M36W432B
Write. Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
first, and remain valid for t
(see Table 20, Figure 16, 17, 18 and 19).
, t
or t
WHDX E1HAX E2LAX
WS and E1S are at V , and E2S is at V . Either
IL
IH
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 19,
Figure 15). The SRAM is in Standby mode when-
the Chip Enable inputs, E1S and E2S, or the Write
Enable input, WS, must be deasserted during ad-
dress transitions for subsequent write cycles.
A Write operation is initiated when E1S is at V ,
ever either Chip Enable is deasserted, E1S at V
or E2S at V .
IL
IL
IH
E2S is at V and WS is at V . The data is latched
IH
IL
on the falling edge of E1S, the rising edge of E2S
or the falling edge of WS, whichever occurs last.
The Write cycle is terminated on the rising edge of
E1S, the rising edge of WS or the falling edge of
E2S, whichever occurs first.
Data Retention. The SRAM data retention per-
formances as V goes down to V are de-
scribed in Table 21 and Figure 20, 21. In E1S
controlled data retention mode, the minimum
standby current mode is entered when
DDS
DR
If the Output is enabled (E1S=V , E2S=V and
E1S ≥ V
E2S ≥ V
– 0.2V
and
E2S ≤ 0.2V
or
IL
IH
DDS
DDS
GS=V ), then WS will return the outputs to high
– 0.2V. In E2S controlled data reten-
IL
impedance within t
must be taken to avoid bus contention in this type
of its falling edge. Care
tion mode, minimum standby current mode is en-
tered when E2S ≤ 0.2V.
WLQZ
of operation. The Data input must be valid for t
D-
Output Disable. The data outputs are high im-
before the rising edge of Write Enable, for
VWH
t
pedance when the Output Enable, GS, is at V
IH
before the rising edge of E1S or for t
DVE1H
DVE2L
with Write Enable, WS, at V .
IH
before the falling edge of E2S, whichever occurs
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 11. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–40
–40
–55
–0.5
–0.6
–0.6
–0.5
Max
85
(1)
T
°C
°C
°C
V
A
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Flash Supply Voltage
Program Voltage
T
125
155
BIAS
T
STG
V
V
+0.3
IO
DDQF
V
, V
3.9
13
V
DDF DDQF
V
V
PPF
V
DDS
SRAM Supply Voltage
3.9
V
Note: 1. Depends on range.
21/57
M36W432T, M36W432B
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 12,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
SRAM
Flash Memory
70/85
Parameter
70
Units
Min
–
Max
–
Min
2.7
Max
3.3
3.3
85
V
V
Supply Voltage
V
V
DDF
V
Supply Voltage
2.7
– 40
3.3
85
2.7
DDQ F = DDS
Ambient Operating Temperature
– 40
°C
pF
ns
V
Load Capacitance (C )
50
50
L
Input Rise and Fall Times
5
5
0 to V
0 to V
DDQF
Input Pulse Voltages
DDQF
V
/2
DDQF
V
/2
DDQF
Input and Output Timing Ref. Voltages
V
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
V
DDQF
V
DDQ
V
/2
DDQ
V
DDQF
V
0V
DDF
25kΩ
AI05205
DEVICE
UNDER
TEST
Note: V
means V
= V
DDQF DDS
DDQ
C
L
25kΩ
0.1µF
0.1µF
C
includes JIG capacitance
AI05206
L
Table 13. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Typ
12
Max
14
Unit
C
IN
V
= 0V, f=1 MHz
= 0V, f=1 MHz
pF
pF
IN
C
V
OUT
20
22
OUT
Note: Sampled only, not 100% tested.
22/57
M36W432T, M36W432B
Table 14. DC Characteristics
Symbol
Parameter
Device
Test Condition
Min
Typ
Max
Unit
Flash &
SRAM
I
LI
0V ≤ V ≤ V
Input Leakage Current
±2
µA
IN
DDQF
0V ≤ V
SRAM Outputs Hi-Z
≤ V
DDQF,
Flash &
SRAM
OUT
I
Output Leakage Current
±10
50
µA
µA
LO
EF = V ± 0.2V
DDQF
Flash
15
V
DDQF
= V
max
DDF
I
I
V
DD
Standby Current
DDS
DDD
E1S = E2S ≥ V
– 0.2V
DDS
SRAM
Flash
20
15
50
50
µA
µA
or E2S ≤ 0.2V
RPF = V
± 0.2V
Supply Current (Reset)
Supply Current
SSF
V
IN
≤ V
– 0.2V
DDS
or V ≤ 0.2V
= 0 mA, cycle time = 1µs
1
7
2
mA
mA
IN
I
IO
I
SRAM
DD
V
IN
≤ V
– 0.2V
DDS
or V ≤ 0.2V
12
IN
I
IO
= 0 mA, min cycle time
I
EF = V , GF = V f = 5 MHz
IL IH,
Supply Current (Read)
Supply Current (Program)
Supply Current (Erase)
Flash
Flash
Flash
10
10
5
20
20
20
mA
mA
mA
DDR
I
Program in progress
Erase in progress
DDW
I
DDE
Supply Current
(Erase Suspend)
I
Flash
Flash
Erase Suspend in progress
Program Suspend in progress
50
50
µA
µA
DDES
Supply Current
(Program Suspend)
I
DDWS
V
≤ V
DDQF
0.2
100
0.2
5
µA
µA
µA
µA
PPF
Program Current
(Standby)
I
Flash
Flash
PPS
V
> V
400
5
PPF
PPF
DDF
V
≤ V
DDQF
Program Current
(Read)
I
PPR
V
= V
DDF
100
400
PPF
V
= 12V ± 0.6V
Program Current
(Program)
PPF
I
Flash
Flash
5
5
10
10
mA
mA
V
PPW
Program in progress
V
PPF
= 12V ± 0.6V
Program Current
(Erase)
I
PPE
Program in progress
Flash &
SRAM
V
V
= V
= V
≥ 2.7V
≥ 2.7V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
– 0.3
2.2
0.8
IL
DDQF
DDQF
DDS
V
Flash &
SRAM
DDQF
+0.3
V
V
V
IH
DDS
V
V
= V
= V min
DDS DD
Flash &
SRAM
DDQF
V
0.1
3.3
V
OL
I
= 100µA
OL
= V
= V min
DD
V
DDQ
Flash &
SRAM
DDQF
DDS
V
V
OH
I
= –100µA
–0.1
OH
Program Voltage (Program or
Erase operations)
V
Flash
2.7
V
PPL
23/57
M36W432T, M36W432B
Symbol
Parameter
Program Voltage
Device
Test Condition
Min
Typ
Max
Unit
V
PPH
Flash
11.4
12.6
V
(Program or Erase operations)
Program Voltage
(Program and Erase lock-out)
V
Flash
Flash
1
2
V
V
PPLK
V
DDF
Supply Voltage (Program
V
LKO
and Erase lock-out)
Figure 9. Flash Read AC Waveforms
tAVAV
VALID
A0-A20
tAVQV
tAXQX
EF
GF
tELQV
tELQX
tEHQX
tEHQZ
tGLQV
tGHQX
tGHQZ
tGLQX
VALID
DQ0-DQ15
OUTPUTS
ENABLED
ADDR. VALID
CHIP ENABLE
DATA VALID
STANDBY
AI05207
Table 15. Flash Read AC Characteristics
Flash
85
Symbol
Alt
Parameter
Unit
70
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
Max
Min
70
70
0
85
ns
ns
ns
AVAV
RC
t
t
ACC
85
AVQV
(1)
t
Address Transition to Output Transition
0
0
t
OH
AXQX
(1)
(1)
(2)
(1)
(1)
(1)
(2)
t
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
Min
Max
Max
Min
0
20
70
0
ns
ns
ns
ns
ns
ns
ns
t
OH
EHQX
t
20
85
0
t
HZ
EHQZ
t
Chip Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
t
t
CE
ELQV
ELQX
t
LZ
t
Min
0
0
t
t
OH
GHQX
GHQZ
t
Max
Max
20
20
20
20
DF
t
t
OE
GLQV
24/57
M36W432T, M36W432B
Flash
Unit
Symbol
Alt
Parameter
70
85
(1)
t
Output Enable Low to Output Transition
Min
0
0
ns
t
OLZ
GLQX
Note: 1. Sampled only, not 100% tested.
2. GF may be delayed by up to t
- t
after the falling edge of EF without increasing t
.
ELQV
ELQV GLQV
25/57
M36W432T, M36W432B
Figure 10. Flash Write AC Waveforms, Write Enable Controlled
26/57
M36W432T, M36W432B
Table 16. Flash Write AC Characteristics, Write Enable Controlled
Flash
Unit
Symbol
Alt
Parameter
70
70
45
45
0
85
85
45
45
0
t
t
WC
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
Address Valid to Write Enable High
Data Valid to Write Enable High
Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
AVWH
AS
DS
CS
t
t
t
DVWH
t
ELWL
t
70
85
ELQV
(1,2)
Output Valid to V
Low
0
0
0
0
t
PPF
QVVPL
t
Output Valid to Write Protect Low
V High to Write Enable High
PPF
QVWPL
(1)
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
200
0
200
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
VPS
VPHWH
t
t
t
Write Enable High to Address Transition
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Write Enable High to Output Enable Low
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Protect High to Write Enable High
WHAX
AH
t
0
0
WHDX
WHEH
DH
CH
t
t
0
0
t
t
25
20
25
45
45
25
20
25
45
45
WHEL
WHGL
WHWL
t
t
WPH
t
t
WLWH
WP
t
WPHWH
Note: 1. Sampled only, not 100% tested.
2. Applicable if V is seen as a logic input (V
< 3.6V).
PPF
PPF
27/57
M36W432T, M36W432B
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled
28/57
M36W432T, M36W432B
Table 17. Flash Write AC Characteristics, Chip Enable Controlled
Flash
Unit
Symbol
Alt
Parameter
70
70
45
45
0
85
85
45
45
0
t
t
WC
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
Address Valid to Chip Enable High
Data Valid to Chip Enable High
AVEH
AS
DS
AH
DH
t
t
t
t
DVEH
t
Chip Enable High to Address Transition
Chip Enable High to Data Transition
Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Chip Enable Low to Chip Enable High
Chip Enable Low to Output Valid
EHAX
t
0
0
EHDX
t
t
CPH
25
25
0
25
25
0
EHEL
t
EHGL
t
t
WH
EHWH
t
t
CP
45
70
45
85
ELEH
t
ELQV
(1,2)
Output Valid to V
Low
0
0
0
0
t
PPF
QVVPL
t
Data Valid to Write Protect Low
V High to Chip Enable High
PPF
QVWPL
(1)
t
200
200
t
VPS
VPHEH
t
t
CS
Write Enable Low to Chip Enable Low
Write Protect High to Chip Enable High
Min
Min
0
0
ns
ns
WLEL
t
45
45
WPHEH
Note: 1. Sampled only, not 100% tested.
2. Applicable if V is seen as a logic input (V
< 3.6V).
PPF
PPF
29/57
M36W432T, M36W432B
Figure 12. Flash Power-Up and Reset AC Waveforms
WF,EF,GF
tPHWL
tPHWL
tPHEL
tPHGL
tPHEL
tPHGL
RPF
tVDHPH
tPLPH
Reset
VDDF, VDDQF
Power-Up
AI05210
Table 18. Flash Power-Up and Reset AC Characteristics
Flash
Symbol
Parameter
Test Condition
Unit
70
85
50
30
During
t
t
PHWL
Program and
Erase
Min
50
µs
Reset High to Write Enable Low, Chip Enable
Low, Output Enable Low
t
PHEL
PHGL
others
Min
Min
30
ns
ns
(1,2)
(3)
Reset Low to Reset High
100
100
50
t
PLPH
Supply Voltages High to Reset High
Min
50
µs
t
VDHPH
Note: 1. The device Reset is possible but not guaranteed if t
2. Sampled only, not 100% tested.
< 100ns.
PLPH
3. It is important to assert RPF in order to allow proper CPU initialization during power up or reset.
30/57
M36W432T, M36W432B
Figure 13. SRAM Read AC Waveforms, Address Controlled with UBS = LBS = V
IL
tAVAV
VALID
A0-A17
tAVQV
tAXQX
DQ0-DQ15
DATA VALID
DATA VALID
AI05211
Note: E1S = Low, E2S = High, GS = Low, WS = High.
Figure 14. SRAM Read AC Waveforms, E1S, E2S or GS Controlled
tAVAV
A0-A17
E1S
VALID
tAVQV
tE1LQV
tAXQX
tE1HQZ
tE1LQX
tE2HQV
tE2LQZ
tBHQZ
E2S
tE2HQX
tBLQV
UBS, LBS
tBLQX
tGLQV
tGHQZ
GS
tGLQX
DQ0-DQ15
DATA VALID
AI05212
31/57
M36W432T, M36W432B
Figure 15. SRAM Standby AC Waveforms
E1S
E2S
tPU
tPD
I
DD
50%
AI05213
Table 19. SRAM Read AC Characteristics
SRAM
Max
Symbol
Alt
Parameter
Unit
Min
t
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
RC
t
t
Address Valid to Output Valid
70
AVQV
AA
t
t
Address Transition to Output Transition
UBS, LBS Disable to Hi-Z Output
UBS, LBS Access Time
10
10
AXQX
OH
t
t
BHZ
25
70
BHQZ
t
t
BLQV
BA
t
t
UBS, LBS Enable to Low-Z Output
Chip Enable 1 High to Output Hi-Z
Chip Enable 1 Low to Output Valid
Chip Enable 1 Low to Output Transition
Chip Enable 2 High to Output Valid
Chip Enable 2 High to Output Transition
Chip Enable 2 Low to Output Hi-Z
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Chip Enable 1 High or Chip Enable 2 Low to Power Down
BLQX
BLZ
HZ1
t
t
25
70
E1HQZ
t
t
E1LQV
CO1
t
t
10
10
E1LQX
LZ1
t
t
70
E2HQV
CO2
t
t
E2HQX
LZ2
HZ2
OHZ
t
t
25
25
35
E2LQZ
t
t
GHQZ
t
t
GLQV
OE
t
t
OLZ
5
0
GLQX
(1)
70
t
t
PD
PU
(1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
ns
Note: 1. Sampled only. Not 100% tested.
32/57
M36W432T, M36W432B
Figure 16. SRAM Write AC Waveforms, WS Controlled with GS Low
tAVAV
A0-A17
VALID
tAVWH
tE1LWH
tAVE1L
tWHAX
E1S
E2S
tAVE2H
tE2HWH
tBLWH
UBS, LBS
WS
tAVWL
tWLWH
tWLQZ
tWHQX
tWHDX
tDVWH
INPUT VALID
DQ0-DQ15
AI05214
Figure 17. SRAM Write AC Waveforms, WS Controlled with GS High
tAVAV
A0-A17
VALID
tAVWH
tE1LWH
tAVE1L
tWHAX
E1S
E2S
tAVE2H
tE2HWH
tBLWH
UBS, LBS
tAVWL
tWLWH
WS
GS
tWHQX
tWHDX
tGHQZ
tDVWH
INPUT VALID
DQ0-DQ15
AI05215
33/57
M36W432T, M36W432B
Figure 18. SRAM Write AC Waveforms, UBS and LBS Controlled
tAVAV
A0-A17
E1S
VALID
tE1LWH
tE1HAX
tAVWH
E2S
tE2HWH
tBLWH
tAVWL
UBS, LBS
tWLWH
WS
tDVWH
DATA VALID
tWHDX
DQ0-DQ15
AI05216
Figure 19. SRAM Write AC Waveforms, E1S Controlled
tAVAV
A0-A17
E1S
VALID
tE1LWH
tAVE1L
tE1HAX
E2S
tBLWH
UBS, LBS
tAVWL
WS
tDVE1H
INPUT VALID
tWHDX
DQ0-DQ15
AI05217
34/57
M36W432T, M36W432B
Table 20. SRAM Write AC Characteristics
SRAM
Unit
Symbol
Alt
Parameter
Min
Max
t
t
WC
Write Cycle Time
70
ns
ns
ns
ns
ns
AVAV
(1)
t
Address Valid to Chip Enable 1 Low
Address Valid to Chip Enable 2 High
Address Valid to Write Enable High
Address Valid to Write Enable Low
0
0
t
t
AVE1L
AS
(1)
t
AVE2H
AS
t
t
60
0
AVWH
AW
(1)
t
AVWL
t
AS
t
t
UBS, LBS Valid to End of Write
Input Valid to Chip Enable 1 High
Input Valid to Chip Enable 2 Low
Input Valid to Write Enable High
Chip Enable 1 High to Address Transition
60
30
30
30
0
ns
ns
ns
ns
ns
BLWH
BW
t
t
t
t
DVE1H
DW
t
DVE2L
DW
DW
t
DVWH
(2)
(3)
(2)
t
t
E1HAX
WR
t
t
,
E1LWH
Chip Select to End of Write
60
0
ns
t
CW
E2HWH
t
Chip Enable 2 Low to Address Transition
Output Enable High to Output Hi-Z
ns
ns
ns
t
E2LAX
WR
t
t
25
25
GHQZ
WHAX
WHDX
GHZ
(2)
t
Write Enable High to Address Transition
0
t
WR
t
t
t
Write Enable High to Input Transition
Write Enable High to Output Transition
Write Enable Low to Output Hi-Z
0
ns
ns
ns
DH
t
10
WHQX
OW
t
t
WLQZ
WHZ
(4)
t
Write Enable Pulse Width
50
ns
WLWH
t
WP
Note: 1. t is measured from the address valid to the beginning of write.
AS
2. t
3. t
is measured from the end or write to the address change. t
is measured from E1S going low end of write.
applied in case a write ends as E1S or WS going high.
WR
WR
CW
4. A Write occurs during the overlap (t ) of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting
WP
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-
liest transition when E1S goes high and WS goes high. The t
is measured from the beginning of write to the end of write.
WP
35/57
M36W432T, M36W432B
Figure 20. SRAM Low V
Data Retention AC Waveforms, E1S Controlled
DDS
tCDR
DATA RETENTION MODE
tR
V
DDS
2.8 V
V
≥ 1.5V
DR
1.5 V
E1S ≥ V
– 0.2V
DDS
E1S
V
SSS
AI05218
Figure 21. SRAM Low V
Data Retention AC Waveforms, E2S Controlled
DDS
DATA RETENTION MODE
V
DDS
2.8 V
E2S
tCDR
tR
V
≥ 1.5V
DR
1.5 V
E2S ≤ 0.2V
0.4 V
V
SSS
AI05219
Table 21. SRAM Low V
Data Retention Characteristic
DDS
Symbol
Parameter
Test Condition
Min
Max
Unit
V
= 3.3V, E1S ≥ V
– 0.2V,
DDS
DDS
I
Supply Current (Data Retention)
15
µA
DDDR
E2S ≥ V
– 0.2V or E2S ≤ 0.2V
– 0.2V, E2S ≤ 0.2V
DDS
DDS
V
E1S ≥ V
E1S ≥ V
Supply Voltage (Data Retention)
Chip Disable to Power Down
Operation Recovery Time
1.5
0
3.3
V
DR
t
– 0.2V, E2S ≤ 0.2V
DDS
ns
ns
CDR
t
t
R
RC
Note: 1. All other Inputs V ≤ V –0.2V or V ≤ 0.2V.
IH
DD
IL
2. Sampled only. Not 100% tested.
36/57
M36W432T, M36W432B
PACKAGE MECHANICAL
Figure 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline
D
D2
D1
SE
b
E
E1
BALL "A1"
e
ddd
FE
FD
SD
e
A
A2
A1
BGA-Z12
Note: Drawing is not to scale.
Table 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.400
0.0551
0.250
0.0098
1.100
0.0433
0.400
12.000
5.600
8.800
0.350
0.450
0.0157
0.4724
0.2205
0.3465
0.0138
0.0177
D
–
–
–
–
–
–
–
–
D1
D2
ddd
E
–
–
–
–
0.100
0.0039
8.000
5.600
0.800
1.600
1.200
0.400
0.400
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.3150
0.2205
0.0315
0.0630
0.0472
0.0157
0.0157
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E1
e
FD
FE
SD
SE
37/57
M36W432T, M36W432B
Figure 23. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)
#3
#4
#1
#2
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
AI05220
38/57
M36W432T, M36W432B
Figure 24. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)
END
POINT
START
POINT
#3
#4
#1
#2
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
AI05221
39/57
M36W432T, M36W432B
PART NUMBERING
Table 23. Ordering Information Scheme
Example:
M36W432T
70 ZA
6
T
Device Type
M36 = MMP (Flash + SRAM)
Operating Voltage
W = V
= 2.7V to 3.3V, V
= V
= 2.7V to 3.3V
DDQF
DDF
DDS
SRAM Chip Size & Organization
4 = 4 Mbit (256K x 16 bit)
Device Function
32 = 32 Mbit (x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70ns
85 = 85ns
Package
ZA = LFBGA66: 0.8mm pitch
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Option
T = Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
Table 24. Daisy Chain Ordering Scheme
Example:
M36W432
-ZA T
Device Type
M36W432
Daisy Chain
-ZA = LFBGA66: 0.8mm pitch
Option
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
40/57
M36W432T, M36W432B
REVISION HISTORY
Table 25. Document Revision History
Date
Version
Revision Details
19-Jun-2001
-01
First Issue
Flash Commands Table corrections: Protect/Lock, Unprotect/Unlock, Lock/Lock-
Down
16-Jul-2001
11-Feb-2002
-02
-03
Package mechanical data clarified (Table 22)
41/57
M36W432T, M36W432B
APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES
Table 26. Top Boot Block Addresses,
M36W432T
34
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
35
Size
(KWord)
#
Address Range
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
0
4
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
42/57
M36W432T, M36W432B
Table 27. Bottom Boot Block Addresses,
M36W432B
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
Size
#
Address Range
(KWord)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
43/57
M36W432T, M36W432B
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
structure is read from the memory. Tables 28, 29,
30, 31, 32 and 33 show the addresses used to re-
trieve the data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 33, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read
command to return to Read mode.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
Table 28. Query Structure Overview
Offset
00h
Sub-section Name
Description
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Reserved
10h
CFI Query Identification String
System Interface Information
Device Geometry Definition
1Bh
27h
Additional information specific to the Primary
Algorithm (optional)
P
A
Primary Algorithm-specific Extended Query table
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Note: Query data are always presented on the lowest order data outputs.
Table 29. CFI Query Identification String
Offset
Data
Description
Value
00h
0020h
Manufacturer Code
Device Code
ST
88BAh
88BBh
Top
Bottom
01h
02h-0Fh
10h
reserved Reserved
0051h
"Q"
"R"
"Y"
11h
0052h
0059h
0003h
0000h
0035h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII String "QRY"
12h
13h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
Intel
compatible
14h
15h
Address for Primary Algorithm extended Query table (see Table 31)
P = 35h
NA
16h
17h
Alternate Vendor Command Set and Control Interface ID Code second vendor -
specified algorithm supported (0000h means none exists)
18h
19h
Address for Alternate Algorithm extended Query table
(0000h means none exists)
NA
1Ah
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
44/57
M36W432T, M36W432B
Table 30. CFI Query System Interface Information
Offset
Data
Description
Value
V
V
V
V
Logic Supply Minimum Program/Erase or Write voltage
DD
1Bh
0027h
2.7V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
Logic Supply Maximum Program/Erase or Write voltage
DD
1Ch
1Dh
1Eh
0036h
00B4h
00C6h
3.6V
11.4V
12.6V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
[Programming] Supply Minimum Program/Erase voltage
PP
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
[Programming] Supply Maximum Program/Erase voltage
PP
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
n
1Fh
20h
21h
22h
23h
24h
25h
26h
0004h
0004h
000Ah
0000h
0005h
0005h
0003h
0000h
16µs
16µs
1s
Typical timeout per single word program = 2 µs
n
Typical timeout for Double Word Program = 2 µs
n
Typical timeout per individual block erase = 2 ms
n
NA
Typical timeout for full chip erase = 2 ms
n
512µs
512µs
8s
Maximum timeout for word program = 2 times typical
n
Maximum timeout for Double Word Program = 2 times typical
n
Maximum timeout per individual block erase = 2 times typical
n
NA
Maximum timeout for chip erase = 2 times typical
45/57
M36W432T, M36W432B
Table 31. Device Geometry Definition
Offset Word
Data
Description
Value
Mode
n
27h
0016h
4 MByte
Device Size = 2 in number of bytes
28h
29h
0001h
0000h
x16
Async.
Flash Device Interface Code description
2Ah
2Bh
0002h
0000h
n
4
2
Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.
2Ch
0002h
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.
2Dh
2Eh
003Eh
0000h
Region 1 Information
Number of identical-size erase block = 003Eh+1
63
64 KByte
8
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase block = 0007h+1
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
8 KByte
8
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
8 KByte
63
31h
32h
003Eh
0000h
Region 2 Information
Number of identical-size erase block = 003Eh=1
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
64 KByte
46/57
M36W432T, M36W432B
Table 32. Primary Algorithm-Specific Extended Query Table
Offset
Data
Description
Value
(1)
P = 35h
(P+0)h = 35h
(P+1)h = 36h
(P+2)h = 37h
(P+3)h = 38h
(P+4)h = 39h
(P+5)h = 3Ah
(P+6)h = 3Bh
(P+7)h = 3Ch
(P+8)h = 3Dh
0050h
0052h
0049h
0031h
0030h
0066h
0000h
0000h
0000h
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
Major version number, ASCII
Minor version number, ASCII
"1"
"0"
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
Chip Erase supported
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
No
Yes
Yes
No
Suspend Erase supported
Suspend Program supported
Legacy Lock/Unlock supported
Queued Erase supported
No
Instant individual block locking supported (1 = Yes, 0 = No)
Yes
Yes
No
Protection bits supported
Page mode read supported
Synchronous read supported
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
No
bit 31 to 9 Reserved; undefined bits are ‘0’
(P+9)h = 3Eh
0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
bit 0
Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
Yes
(P+A)h = 3Fh
(P+B)h = 40h
0003h
0000h
Block Lock Status : Defines which bits in the Block Status Register section of
the Query are implemented.
Address (P+A)h contains less significant byte
bit 0
bit 1
Block Lock Status bit active
Block Lock-Down Status bit active
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
Yes
Yes
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
(P+C)h = 41h
(P+D)h = 42h
(P+E)h = 43h
0030h
00C0h
0001h
V
V
Logic Supply Optimum Program/Erase voltage (highest performance)
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
3V
12V
01
DD
Supply Optimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
PP
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
(P+F)h = 44h
(P+10)h = 45h
(P+11)h = 46h
(P+12)h = 47h
0080h
0000h
0003h
0003h
Protection Field 1: Protection Description
80h
00h
This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
8 Byte
8 Byte
The following bytes are factory pre-programmed and user-programmable.
bit 0 to 7
Lock/bytes JEDEC-plane physical low address
bit 8 to 15
bit 16 to 23
bit 24 to 31
Lock/bytes JEDEC-plane physical high address
n
"n" such that 2 = factory pre-programmed bytes
n
"n" such that 2 = user programmable bytes
(P+13)h = 48h
Reserved
Note: 1. See Table 29, offset 15 for P pointer definition.
47/57
M36W432T, M36W432B
Table 33. Security Code Area
Offset
80h
81h
82h
83h
84h
85h
86h
87h
88h
Data
00XX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Description
Protection Register Lock
64 bits: unique device number
64 bits: User Programmable OTP
48/57
M36W432T, M36W432B
APPENDIX C. FLASH MEMORY FLOWCHARTS AND PSEUDO CODES
Figure 25. Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
Write 40h or 10h
/*or writeToFlash (any_address, 0x10) ; */
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
V
Invalid
if (status_register.b3==1) /*V
error_handler ( ) ;
invalid error */
PPF
PPF
b3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI05222
Note: 1. Status check of b1 (Protected Block), b3 (V
a sequence.
Invalid) and b4 (Program Error) can be made after each program operation or after
PPF
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
49/57
M36W432T, M36W432B
Figure 26. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 1
& Data 1 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
Read Status
Register
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*V
error_handler ( ) ;
invalid error */
PPF
PPF
b3 = 0
YES
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI05223
Note: 1. Status check of b1 (Protected Block), b3 (V
a sequence.
Invalid) and b4 (Program Error) can be made after each program operation or after
PPF
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
50/57
M36W432T, M36W432B
Figure 27. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
Read Status
Register
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
b2 = 1
YES
Program Complete
if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
}
Read data from
another address
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
Write FFh
Read Data
}
}
Program Continues
AI05224
51/57
M36W432T, M36W432B
Figure 28. Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
NO
b7 = 1
} while (status_register.b7== 0) ;
YES
NO
YES
NO
NO
V
Invalid
if (status_register.b3==1) /*V
error_handler ( ) ;
invalid error */
PPF
Error (1)
PPF
b3 = 0
YES
if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
Command
Sequence Error (1)
b4, b5 = 1
NO
error_handler ( ) ;
if ( (status_register.b5==1) )
/* erase error */
b5 = 0
YES
Erase Error (1)
error_handler ( ) ;
Erase to Protected
Block Error (1)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI05225
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
52/57
M36W432T, M36W432B
Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
{
Read Status
Register
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
NO
NO
b7 = 1
YES
} while (status_register.b7== 1) ;
if (status_register.b6==1) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;
b6 = 1
YES
Erase Complete
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
}
else
{ read_program_data ( );
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
Write D0h
Write FFh
Read Data
}
}
Erase Continues
AI05226
53/57
M36W432T, M36W432B
Figure 30. Locking Operations Flowchart and Pseudo Code
Start
locking_operation_command (address, lock_operation) {
Write 60h
writeToFlash (any_address, 0x60) ; /*configuration setup*/
if (lock_operation==PROTECT) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNPROTECT) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
Write
01h, D0h or 2Fh
else if (lock_operation==LOCK) /*to lock the block*/
writeToFlash (address, 0x2F) ;
writeToFlash (any_address, 0x90) ;
Write 90h
Read Status
Register
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
NO
Locking
change
/*Check the locking state (see Read Block Signature table )*/
confirmed?
YES
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/
Write FFh
}
End
AI05227
54/57
M36W432T, M36W432B
APPENDIX D. FLASH MEMORY COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER
STATE
Table 34. Write State Machine Current/Next, sheet 1 of 2
Command Input (and Next State)
Data
When
Read
Current
State
SR
bit 7
Read
Array
(FFh)
Program
Setup
(10/40h)
Erase
Setup
Erase
Confirm
(D0h)
Prog/Ers
Suspend
(B0h)
Prog/Ers
Resume
(D0h)
Read
Status
(70h)
Clear
Status
(50h)
(10/40h)
Read Array “1”
Array
Read Array Prog.Setup Ers. Setup
Read Array
Read Sts. Read Array
Read
“1”
Program
Setup
Erase
Setup
Read
Status
Read Array
Read Array
Read Array
Read Array
Read Array
Status
Status
Read
“1”
Electronic
Signature
Program
Setup
Erase
Setup
Read
Read Array
Read Array
Read Array
Status
Elect.Sg.
Read CFI
“1”
Program
Setup
Erase
Setup
Read
CFI
Read Array
Status
Query
Lock
(complete)
Lock Cmd
Error
Lock
(complete)
Lock Setup “1”
Status
Status
Status
Status
Status
Lock Command Error
Lock Command Error
Lock Cmd
“1”
Program
Setup
Erase
Setup
Read
Read Array
Read Array
Read Array
Read Array
Read Array
Status
Error
Lock
“1”
Program
Setup
Erase
Setup
Read
Read Array
Status
(complete)
Prot. Prog.
“1”
Protection Register Program
Protection Register Program continue
Setup
Prot. Prog.
“0”
(continue)
Prot. Prog.
“1”
Program
Setup
Erase
Setup
Read
Status
Status
Status
Read Array
Read Array
Program
Read Array
Status
(complete)
Prog. Setup “1”
Program
“0”
Prog. Sus
Read Sts
Program (continue)
Program (continue)
(continue)
Prog. Sus
“1”
Prog. Sus
Read Array
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
Status
Array
Status
(continue) Read Array (continue)
Program Prog. Sus Program
(continue) Read Array (continue)
Prog. Sus
“1”
Prog. Sus
Read Array
Program Suspend to
Read Array
Prog. Sus Prog. Sus
Read Sts Read Array
Read Array
Prog. Sus
Read
Elect.Sg.
Electronic Prog. Sus
Signature Read Array
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
“1”
(continue) Read Array (continue)
Prog. Sus
Read CFI
Prog. Sus
CFI
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
“1”
“1”
“1”
“1”
“0”
“1”
“1”
Read Array
(continue) Read Array (continue)
Program
(complete)
Program
Setup
Erase
Setup
Read
Status
Status
Status
Status
Status
Array
Read Array
Read Array
Read Array
Status
Erase
Setup
Erase
Erase
Erase
Erase Command Error
Erase Command Error
(continue) CmdError (continue)
Erase
Cmd.Error
Program
Setup
Erase
Setup
Read
Read Array
Read Array
Read Array
Status
Erase
(continue)
Erase Sus
Read Sts
Erase (continue)
Erase (continue)
Erase Sus
Read Sts
Erase Sus
Read Array
Program Erase Sus
Erase
Erase Sus
Erase
Erase
Erase Sus Erase Sus
Read Sts Read Array
Setup
Read Array (continue) Read Array (continue)
Erase Sus
Read Array
Erase Sus
Read Array
Program
Setup
Erase Sus
Erase
Erase Sus
Erase Sus Erase Sus
Read Sts Read Array
Read Array (continue) Read Array (continue)
Erase Sus
Read
Elect.Sg.
Electronic Erase Sus
Signature Read Array
Program
Setup
Erase Sus
Erase
Erase Sus
Erase
Erase Sus Erase Sus
Read Sts Read Array
“1”
Read Array (continue) Read Array (continue)
Erase Sus
Read CFI
Erase Sus
CFI
Program
Setup
Erase Sus
Erase
Erase Sus
Erase
Erase Sus Erase Sus
Read Sts Read Array
“1”
“1”
Read Array
Read Array (continue) Read Array (continue)
Erase
(complete)
Program
Setup
Erase
Read
Status
Read Array
Read Array
Setup
Read Array
Status
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
55/57
M36W432T, M36W432B
Table 35. Write State Machine Current/Next, sheet 2 of 2
Command Input (and Next State)
Read CFI
Query
(98h)
Unlock
Confirm
(D0h)
Current State
Read Elect.Sg.
(90h)
Lock Setup
(60h)
Prot. Prog.
Setup (C0h)
Lock Confirm
(01h)
Lock Down
Confirm (2Fh)
Prot. Prog.
Setup
Read Array
Read Status
Read Elect.Sg. Read CFI Query
Read Elect.Sg. Read CFI Query
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Read Array
Read Array
Read Array
Prot. Prog.
Setup
Prot. Prog.
Setup
Read Elect.Sg. Read Elect.Sg. Read CFI Query
Read CFI Query Read Elect.Sg. Read CFI Query
Prot. Prog.
Setup
Read Array
Lock (complete)
Read Array
Lock Setup
Lock Command Error
Prot. Prog.
Setup
Lock Cmd Error Read Elect.Sg. Read CFI Query
Lock Setup
Lock Setup
Prot. Prog.
Setup
Lock (complete) Read Elect.Sg. Read CFI Query
Read Array
Prot. Prog.
Setup
Protection Register Program
Prot. Prog.
(continue)
Protection Register Program (continue)
Prot. Prog.
Prot. Prog.
Lock Setup
Read Elect.Sg. Read CFI Query
(complete)
Read Array
Setup
Prog. Setup
Program
Program
(continue)
Program (continue)
Prog. Suspend Prog. Suspend Prog. Suspend
Program
(continue)
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Read Status
Prog. Suspend Prog. Suspend Prog. Suspend
Read Array Read Elect.Sg. Read CFI Query
Read Elect.Sg. Read CFI Query
Program
(continue)
Prog. Suspend Prog. Suspend Prog. Suspend
Read Elect.Sg. Read Elect.Sg. Read CFI Query
Program
(continue)
Prog. Suspend Prog. Suspend Prog. Suspend
Program
(continue)
Read CFI
Read Elect.Sg. Read CFI Query
Program
(complete)
Prot. Prog.
Lock Setup
Read Elect.Sg. Read CFIQuery
Read Array
Read Array
Setup
Erase
(continue)
Erase Setup
Erase Command Error
Erase
Cmd.Error
Prot. Prog.
Lock Setup
Read Elect.Sg. Read CFI Query
Setup
Erase (continue)
Erase (continue)
Erase Suspend Erase Suspend Erase Suspend
Read Ststus Read Elect.Sg. Read CFI Query
Erase
(continue)
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Erase Suspend Erase Suspend
Read Array Read Elect.Sg. Read CFI Query
Erase
(continue)
Erase Suspend Erase Suspend Erase Suspend
Read Elect.Sg. Read Elect.Sg. Read CFI Query
Erase
(continue)
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Erase Suspend Erase Suspend
Read CFI Query Read Elect.Sg. Read CFI Query
Erase
(continue)
Erase
Prot. Prog.
Setup
Read Elect.Sg. Read CFI Query
(complete)
Read Array
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
56/57
M36W432T, M36W432B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
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57/57
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