N9H20K5N [NUVOTON]
32-bit Microprocessor;
| 型号： | N9H20K5N |
| 厂家： | 
NUVOTON |
| 描述： | 32-bit Microprocessor |
| 文件： | 总60页 (文件大小：1838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N9H20
ARM® ARM926EJ-S Based
32-bit Microprocessor
N9H20 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ARM926EJ-S based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Sept., 11, 2018
Page 1 of 60
Rev 1.10
N9H20
TABLE OF CONTENTS
LIST OF FIGURES............................................................................................... 5
LIST OF TABLES ................................................................................................ 6
1 GENERAL DESCRIPTION.............................................................................. 7
1.1 Applications.....................................................................................................................7
2 FEATURES...................................................................................................... 8
3 PARTS INFORMATION LIST AND PIN CONFIGURATION..........................13
3.1 N9H20 Series Part Number Naming Guide.............................................................13
3.2 N9H20 Series Part Selection Guide..........................................................................14
3.3 Pin Configuration..........................................................................................................15
3.3.1 N9H20K series Pin Diagram ........................................................................................ 15
3.3.2 N9H20R11N Pin Diagram............................................................................................. 16
3.4 Pin Description .............................................................................................................17
3.4.1 N9H20K series LQFP128 pin list................................................................................. 17
3.4.2 N9H20R11N TQFP64 pin list ....................................................................................... 25
4 BLOCK DIAGRAM.........................................................................................30
4.1 N9H20 Series Block Diagram ....................................................................................30
5 FUNCTIONAL DESCRIPTION .......................................................................31
5.1 ARM® ARM926EJ-S CPU Core.................................................................................31
5.1.1 Overview ......................................................................................................................... 31
5.2 System Manager..........................................................................................................32
5.2.1 Overview ......................................................................................................................... 32
5.3 Clock Controller (CLK_CTL) ......................................................................................32
5.3.1 Overview ......................................................................................................................... 32
5.4 SDRAM Interface Controller (SDIC) .........................................................................32
5.4.1 Overview ......................................................................................................................... 32
5.5 2D Blitting Accelerator.................................................................................................32
5.5.1 Overview ......................................................................................................................... 32
5.6 JPEG Codec (JPEG)...................................................................................................33
5.6.1 Overview ......................................................................................................................... 33
5.7 LCD Display Interface Controller (VPOST)..............................................................33
5.7.1 Overview ......................................................................................................................... 33
5.8 Sound Processing Unit (SPU)....................................................................................33
5.8.1 Overview ......................................................................................................................... 33
5.9 I2S Controller (I2S)........................................................................................................33
5.9.1 Overview ......................................................................................................................... 33
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5.10 Storage Interface Controller .................................................................................33
5.10.1Overview ......................................................................................................................... 33
5.11 USB 2.0 Device Controller (USBD).....................................................................34
5.11.1Overview ......................................................................................................................... 34
5.12 USB Host Controller (USBH)................................................................................34
5.12.1Overview ......................................................................................................................... 34
5.13 Enhanced DMA Controller ....................................................................................34
5.13.1Overview ......................................................................................................................... 34
5.14 Advanced Interrupt Controller (AIC)....................................................................34
5.14.1Overview ......................................................................................................................... 34
5.15 General Purpose I/O (GPIO)................................................................................35
5.15.1Overview ......................................................................................................................... 35
5.16 Timer Controller (TMR) .........................................................................................35
5.16.1Overview ......................................................................................................................... 35
5.17 Watchdog Timer (WDT).........................................................................................35
5.17.1Overview ......................................................................................................................... 35
5.18 Real Time Clock (RTC) .........................................................................................35
5.18.1Overview ......................................................................................................................... 35
5.19 I2C Synchronous Serial Interface Controller (I2C).............................................36
5.19.1Overview ......................................................................................................................... 36
5.20 Pulse Width Modulation (PWM)...........................................................................36
5.20.1Overview ......................................................................................................................... 36
5.21 UART Interface Controller (UART)......................................................................36
5.21.1Overview ......................................................................................................................... 36
5.22 SPI Interface Controller (SPI Master/Slaver).....................................................36
5.22.1Overview ......................................................................................................................... 36
5.23 Analog to Digital Converter (ADC) ......................................................................37
5.23.1Overview ......................................................................................................................... 37
5.24 Keypad Interface (KPI)..........................................................................................37
5.24.1Overview ......................................................................................................................... 37
6 ELECTRICAL CHARACTERISTICS..............................................................38
6.1 Absolute Maximum Ratings........................................................................................38
6.2 DC Electrical Characteristics......................................................................................39
6.2.1 N9H20 Series DC Electrical Characteristics.............................................................. 39
6.2.2 ADC Characteristics ...................................................................................................... 40
6.2.3 Audio DAC Characteristics........................................................................................... 40
6.3 AC Electrical Characteristics......................................................................................41
6.3.1 External 12 MHz Crystal ............................................................................................... 41
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6.3.2 Power-on Sequence & RESET.................................................................................... 42
6.3.3 I2C Interface ................................................................................................................... 43
6.3.4 I2S Interface ................................................................................................................... 44
6.3.5 LCD/ Display Interface .................................................................................................. 45
6.3.6 SPI Interface................................................................................................................... 47
6.3.7 NAND Interface .............................................................................................................. 48
6.3.8 SD Card Interface .......................................................................................................... 49
6.3.9 USB PHY Specifications............................................................................................... 50
6.3.10Specification of Low Voltage Reset............................................................................. 51
6.4 Thermal Characteristics of N9H20K Package.........................................................52
7 PACKAGE DIMENSIONS ..............................................................................53
7.1 128L LQFP (14x14x1.4mm footprint)........................................................................53
7.2 TQFP-64 (10X10X1.0mm footprint, 0.5mm pitch) ..............................................54
7.3 PCB Reflow Profile Suggestion .................................................................................57
7.3.1 Profile Setting Consideration........................................................................................ 57
7.3.2 Profile Suggestion for N9H20 series........................................................................... 58
8 REVISION HISTORY......................................................................................59
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Rev 1.10
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LIST OF FIGURES
Figure 3-1 N9H20 Series Part Number Naming Guide ..................................................................13
Figure 3.3-1 N9H20K Series LQFP 128 Pin Diagram ....................................................................15
Figure 3.3-2 N9H20R11N TQFP 64 Pin Diagram ..........................................................................16
Sept., 11, 2018
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Rev 1.10
N9H20
LIST OF TABLES
No table of figures entries found.
Sept., 11, 2018
Page 6 of 60
Rev 1.10
N9H20
1
GENERAL DESCRIPTION
The N9H20 seies is built on the ARM926EJ-S CPU@200MHz, synchronous DRAM, 2D BitBLT
accelerator, LCD panel interface, USB 1.1 Host & USB2.0 HS Device core and integrated with JPEG
codec, 32-channel SPU (Sound Processing Unit), ADC, DAC, for meeting various kinds of application
needs for saving the BOM cost and makes the best choice for LCD application of cost/performance
products.
Maximum resolution is XVGA (1,024x768)@TFT LCD panel. The 2D BitBLT accelerator accelerates
the graphic compution to make the rendering smooth and off-load CPU to save power consumption.
The open source code environment provides the product development more flexibility. For reducing
system complexity while cutting the BOM cost, the N9H20 series provides MCP (Multi-Chip Package)
to ensure higher performance and to minimize the system design efforts. Total BOM cost could be cut
by employing 2-layer PCB along with the elimination of external parts, EMI prevention components and
saving board design space.
1.1
Applications
HMI
Home Appliance
Advertisement
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2
FEATURES
CPU
ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache
Frequency up to 200MHz@1.8V core power operation voltage
JTAG interface supported for development and debugging
Internal SRAM & ROM
8KB internal SRAM and 16KB IBR internal booting ROM supported
IBR booting messages displayed by UART console for debugging supported
Different system booting modes supported:
Memory card
SD card or eMMC Flash device
SD-to-NAND flash bridge
Raw NAND Flash
SPI Flash
USB
EDMA (Enhanced DMA)
Totally 5 DMA channels supported
4 peripheral DMA channels for transfer between memory and on-chip peripherals,
such as ADC, UART and SPI
One dedicated channel for memory-to-memory transfer
Byte, half-word and word data width types supported
Single and burst transfer modes supported
Block transfer supported in memory-to-memory transfer channel
Color format transformation supported in memory-to-memory transfer channel
Source color format could be RGB555, RGB565 and YCbCr422
Destination color format could be RGB555, RGB565 and YCbCr422
Auto reload supported for continuous data transfer
Interrupt generation supported in the half-of-transfer or end-of-transfer
JPEG Codec
Baseline Sequential mode JPEG codec function compliant with ISO/IEC 10918-1
international JPEG standard supported.
Planar Format
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format
image
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y
only) format image
Support to decode YCbCr 4:2:2 transpose format
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for
decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function for encode and decode modes
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode
mode
Support rotate function in encode mode
Packet Format
Support to encode interleaved YUYV format input image, output bitstream 4:2:2
and 4:2:0 format
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image
Support decoded output image RGB555, RGB565 and RGB888 formats.
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The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF
standards
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for
decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for
decode mode
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode
mode
2D Accelerator
BitBLT operation
2x2 transform matrix with effects:
Scale
Translate
Rotate
Shear
Fill
Alpha blending and color transformation supported
Source format for operations: supported color format of source bitmap
Rectangle Fill with single color – ARGB8888
Fill with blending effect supported
Supported color formats
Source
16 bits/pixel – RGB565
32 bits/pixel – ARGB8888
1 bit/pixel, 2 bits/pixel, 4 bits/pixel, 8 bits/pixel with RGB color palette
Destination
16 bits/pixel – RGB565
32 bits/pixel – ARGB8888
VPOST
8/16/18/24-bit SYNC type and 8/9/16/18/24-bit MPU type TFT LCD supported
Color format supported:
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data in
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data out
XGA (1024x768), SVGA (800x600), WVGA (800x480), D1 (720X480), VGA (640x480),
WQVGA (480x272), QVGA (320x240) and HVGA (640x240) resolution supported
The maximum resolution is up to 1024X768 for TFT LCD panel for still image
displaying
The maximum resolution is up to 480x272 for TFT LCD panel for MJPEG video
displaying up to 25fps.
Display scaler – to fit different size of LCD panels
Horizontal: At most 4.0x scale
Vertical: At most 3.0x scale
For SYNC type LCD:
For 8-bit bus
CCIR601 YCbCr422 packet mode (NTSC/PAL) supported
CCIR601 RGB Dummy mode (NTSC/PAL) supported
CCIR656 interface supported
RGB Through mode supported
For 16/18/24-bit bus
Parallel pixel data output mode (1-pixel/1-clock)
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N9H20
NTSC/PAL interlace & non-interlace output supported
Color format transform supported:
Color format transform between YCbCr422 and RGB565
Color format transform from YCbCr422 to RGB888
Support OSD function to overlap system information like battery life, brightness tuning,
volume tuning or muting, etc.
Frame Switch Controller
Frame relation controlled between VPOST and Capture supported
2 modes supported to switch Frame Buffer Base
Frame Ratio Mode (16 selectable ratio)
Frame sync mode
Double/triple buffers supported
SPU (Sound Processing Unit)
32 stereo channels supported
PCM8/PCM16/4-bit MDPCM/TONE source format supported
7-bit volume control supported for each of 32 channels
5-bit pan control supported for each L/R of 32 channels
10-band equalizer supported
Special code supported for loop playing and event detection
Audio DAC
16-bit stereo DAC supported with headphone driver output
H/W volume control supported
I2S Controller
I2S interface supported to connect external audio codec
16/18/20/24-bit data format supported
Storage Interface Controller
Interface to NAND Flash:
8-bit data bus width supported
SLC and MLC type NAND Flash supported
512B, 2KB, 4KB, and 8KB page size NAND Flash supported
ECC4, ECC8, ECC12 and ECC15 algorithm supported for ECC generation, error
detection and error correction
PBA-NAND flash supported
Interface to SD/MMC/SDIO/SDHC/micro-SD cards/ eMMC Flash device supported
SD-to-NAND flash bridge supported
DMA function supported to accelerate the data transfer between system memory and
NAND Flash or SD/MMC/SDIO/SDHC/micro-SD/eMMC Flash device
USB Device Controller
USB2.0 HS (High-Speed) x 1 port
6 configurable endpoints supported
Control, Bulk, Interrupt and Isochronous transfers supported
Suspend and remote wakeup supported
USB Host Controller
USB1.1 Host one H/W Engine, two pin locations.
Fully compliant with USB Revision 1.1 specification
Open Host Controller Interface (OHCI) Revision 1.0 compatible
Full-speed (12Mbps) and low-speed (1.5Mbps) USB devices supported
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Control, Bulk, Interrupt and Isochronous transfers supported
Timer & Watch-Dog Timer
Two 32-bit with 8-bit pre-scalar timers supported
One programmable 24-bit Watch-Dog Timer supported
PWM
4 PWM channel outputs supported
16-bit counter supported for each PWM channel
Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM channels
Two clock-dividers supported and each divider shared by two PWM channels
Two Dead-Zone generators supported and each generator shared by two PWM
channels
Auto reloaded mode and one-shot pulse mode supported
Capture function supported
UART
A high speed UART supported:
Baud rate is up to 1M bps
4 signals TX, RX, CTS and RTS supported
A normal UART supported:
Baud rate is up to 115.2K bps
2 signals TX and RX supported only
SPI
Two SPI controller is supported
Both master and slave mode are supported in SPI interface
Two chip selection signals for two SPI devices
I2C
One I2C channel supported
Compatible with Philips’s I2C standard and only master mode supported
Multi-master operation supported
Advanced Interrupt Controller
Total 32 interrupt source supported
Configurable interrupt type:
Low-active level triggered interrupt
High-active level triggered interrupt
Low-active edge (falling edge) triggered interrupt
High-active edge (rising edge) triggered interrupt
Individual interrupt mask bit for each interrupt source
8 different priority levels supported
Daisy-chain priority mechanism supported for interrupts with same priority level
Low priority interrupt automatic masking supported for interrupt nesting
RTC
Independent power plane supported
32.768 KHz crystal oscillation circuit supported
Time counter (second, minute, hour) and Calendar counter (day, month, year)
supported
Alarm supported (second, minute, hour, day, month and year)
12/24-hour mode and Leap year supported
Alarm to wake chip up from Standby mode or from Power-down mode supported
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Wake chip up from Power-down mode by input pin supported
Power-off chip by register setting supported
Power-on timeout is supported for low battery protection
GPIO
70 programmable general purpose I/Os supported and separated into 5 groups
Individual configuration supported for each I/O signal
Configurable interrupt control functions supported
Configurable de-bounce circuit supported for interrupt function
ADC
Multi-channel, 10-bit ADC supported
2 channels dedicated for 4-wire resistive touch sensor inputs
2 channels dedicated for Audio ADC with Microphone pre-Amp & AGC
3 channels reserved for various purposes, like LVD (Low Voltage Detection),
keypad input, and light sensor
Input voltage range from 0V ~ 3.3V supported
Maximum 25MHz input clock supported
Maximum 400K/s conversion rate supported
LVR (Low Voltage Reset) supported
Power Management
Advanced power management including Power Down, Deep Standby, CPU Standby,
and Normal Operating modes
Normal Operating Mode
Core power is 1.8V and chip is in normal operation
CPU Standby Mode
Core power is 1.8V and only ARM CPU clock is turned OFF
Deep Standby Mode
Core power is 1.8V and all IP clocks are turned OFF
Power Down Mode
Only the RTC power is ON. Other 3.3V and 1.8V power are OFF
Operating Voltage
I/O: 3.3V
Core: 1.8V
Package
LQFP-128 MCP
TQFP-64 MCP
Sept., 11, 2018
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3
PARTS INFORMATION LIST AND PIN CONFIGURATION
N9H20 Series Part Number Naming Guide
3.1
Figure 3-1 N9H20 Series Part Number Naming Guide
Sept., 11, 2018
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Rev 1.10
N9H20
3.2
N9H20 Series Part Selection Guide
N9H20 series
Core
USB H/W Accelerator
LCD
Analog
Peripheral
Power
Memory
PKG
Part No.
JPEG
TQFP-
MP
N9H20R11N
N9H20K51N
N9H20K31N
N9H20K11N
200 926
8
8
8
8
8
8
8
8
8
8
8
8
2MB
√
√
√
√
-
1
3
3
3
1
1
1
1
HS
HS
HS
HS
√
√
√
√
√
√
√
√
16 QVGA
-
-
-
√
√
√
√
44
70
70
70
2
2
2
2
1
1
1
1
√
√
√
√
1
2
2
2
-
4
4
4
4
-
1.8 3.3 3.3
1.8 1.8 3.3
1.8 1.8 3.3
1.8 3.3 3.3
64
JPEG
JPEG
LQFP-
128
XGA3
24
200 926
200 926
200 926
32MB
8MB
2MB
15
15
15
10 4W
10 4W
√
√
√
√
√
√
√
√
√
MP
LQFP-
128
XGA3
24
MP
LQFP-
128
JPEG
24 QVGA 10 4W
MP
1 Resoltion: QVGA (320x240), VGA (640x480), SVGA (800x600), XGA (1024 x 768).
2 Status: MP - Mass Production, ES - Engineering Sample, UD - Under Development.
3 XGA is for still image only.
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3.3
Pin Configuration
3.3.1
N9H20K series Pin Diagram
Figure 3.3-1 N9H20K Series LQFP 128 Pin Diagram
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3.3.2
N9H20R11N Pin Diagram
Figure 3.3-2 N9H20R11N TQFP 64 Pin Diagram
Sept., 11, 2018
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N9H20
3.4
Pin Description
3.4.1
N9H20K series LQFP128 pin list
Pin No
Name
GPB[2]
Type
Group
Description
IOU GPIOB
OU I²S
GPIO Port B Bit 2
1
2
3
I2S_MCLK
SD1_CLK
GPB[1]
Clock to I2S Codec, Output
SD Port 1 Clock, Output
GPIO Port B Bit 1
OU SD1
IOU GPIOB
IOU SD1
IOU USB
IOU JTAG
IOU SD1
IOU USB
IOU I2C
SD1_DAT[0]
UHL_DM1
GPB[0]
SD Port 1 Data Bit 0
USB Host 1.0 Lite Port 1, D-E154
GPIO Port B Bit 0
SD1_DAT[1]
UHL_DP1
ISDA
SD Port 1 Data Bit 1
USB Host 1.0 Lite Port 1, D+
I2C Interface Data
GPB[14]
LFMARK
LMVSYNC
ISCK
IOU GPIOB
IU LCD
GPIO Port B Bit 14
4
MPU LCD Interface Frame Mark, Input
MPU LCD Interface Mode VSYNC, Output
I2C Interface Clock, Output
GPIO Port B Bit 13
OU LCD
OU I2C
5
6
GPB[13]
IOU GPIOB
SPI Port 0 Clock;Output in Master Mode;Input in Slave
Mode
SPI0_CLK
GPD[12]
IOU SPI0
IOU GPIOD
IOU SPI0
GPIO Port D Bit 12
SPI Port 0 Device Select 0, Low Active;Output in Master
Mode;Input in Slave Mode
GPIO Port D Bit 13
SPI0_CS0_
7
GPD[13]
SPI0_DI
IOU GPIOD
IU SPI0
SPI Port 0 Data Input
8
GPD[14]
SPI0_DO
GPD[15]
SD0_DAT[2]
GPE[4]
IOU GPIOD
OU SPI0
GPIO Port D Bit 14
SPI Port 0 Data Output
GPIO Port D Bit 15
9
IOU GPIOD
IOU SD0
SD Port 0 Data Bit 2
10
11
12
13
IOU GPIOE
IOU SD0
GPIO Port E Bit 4
SD0_DAT[3]
GPE[5]
SD Port 0 Data Bit 3
IOU GPIOE
IOU SD0
GPIO Port E Bit 5
SD0_CMD
GPE[6]
SD Port 0 Command/Response
GPIO Port E Bit 6
IOU GPIOE
OU SD0
SD0_CLK
GPE[7]
SD Port 0 Clock, Output
GPIO Port E Bit 7
IOU GPIOE
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Pin No
14
Name
SD0_DAT[0]
GPE[2]
Type
Group
Description
IOU SD0
SD Port 0 Data Bit 0
GPIO Port E Bit 2
IOU GPIOE
IOU SD0
SD0_DAT[1]
GPE[3]
SD Port 0 Data Bit 1
GPIO Port E Bit 3
15
IOU GPIOE
16 XIN
I
XTAL
XTAL
Core
12MHz Crystal Input
12MHz Crystal Output
Core Logic Power (1.8V)
SDRAM I/F Ground (0V)
SDRAM I/F Power
SDRAM Ground (0V)
SDRAM Power
17 XOUT
18 VDD18
19 VSSQ
20 VDDQ
21 VSSQ
22 MVDD
23 VSS
O
P
G
P
G
P
G
--
P
P
G
MVDD
MVDD
MVDD
MVDD
GND
Ground (0V)
NC
24
NC
when N9H20K11N is installation
1/2 MVDD (0.9V) for DDR_VREF
MVREF
MVDD
25 PLL_UD_VDD18
26 UD_VSS
PLL & USB PLL & USB2.0 Device Core Power (1.8V)
USB
USB2.0 Device Ground (0V)
USB 2.0 Device D-.
27 UD_DM
I/O USB
I/O USB
28 UD_DP
USB 2.0 Device D+.
29 UD_VDD33
30 UD_REXT
P
USB
USB
USB 2.0 Device PHY 3.3V
O
External Resistor 12.1K resistor connected to ground
SYNC/MPU LCD Interface Data Bit 17
GPIO Port E Bit 1
LVDATA[17]
IOU LCD
IOU GPIOE
IOU LCD
IOU GPIOE
IOU LCD
IOU GPIOC
IU KPI
31
GPE[1]
LVDATA[16]
SYNC/MPU LCD Interface Data Bit 16
GPIO Port E Bit 0
32
GPE[0]
LVDATA[15]
33 GPC[15]
KPI_SI[7]
SYNC/MPU LCD Interface Data Bit 15
GPIO Port C Bit 15
KPI Scan In Bit 7
LVDATA[14]
34 GPC[14]
KPI_SI[6]
IOU LCD
IOU GPIOC
IU KPI
SYNC/MPU LCD Interface Data Bit 14
GPIO Port C Bit 14
KPI Scan In Bit 6
LVDATA[13]
35 GPC[13]
KPI_SI[5]
IOU LCD
IOU GPIOC
IU KPI
SYNC/MPU LCD Interface Data Bit 13
GPIO Port C Bit 13
KPI Scan In Bit 5
LVDATA[12]
IOU LCD
IOU GPIOC
SYNC/MPU LCD Interface Data Bit 12
GPIO Port C Bit 12
36
GPC[12]
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N9H20
Pin No
Name
KPI_SI[4]
LVDATA[11]
37 GPC[11]
Type
Group
Description
IU KPI
KPI Scan In Bit 4
IOU LCD
SYNC/MPU LCD Interface Data Bit 11
GPIO Port C Bit 11
IOU GPIOC
IU KPI
KPI_SI[3]
KPI Scan In Bit 3
LVDATA[10]
IOU LCD
SYNC/MPU LCD Interface Data Bit 10
GPIO Port C Bit 10
38 GPC[10]
IOU GPIOC
IU KPI
KPI_SI[2]
KPI Scan In Bit 2
LVDATA[9]
IOU LCD
SYNC/MPU LCD Interface Data Bit 9
GPIO Port C Bit 9
39 GPC[9]
IOU GPIOC
IU KPI
KPI_SI[1]
KPI Scan In Bit 1
LVDATA[8]
IOU LCD
SYNC/MPU LCD Interface Data Bit 8
GPIO Port C Bit 8
40 GPC[8]
IOU GPIOC
IU KPI
KPI_SI[0]
LVDATA[7]
GPC[7]
KPI Scan In Bit 0
IOU LCD
SYNC/MPU LCD Interface Data Bit 7
GPIO Port C Bit 7
41
IOU GPIOC
IOU LCD
LVDATA[6]
SYNC/MPU LCD Interface Data Bit 6
GPIO Port C Bit 6
42 GPC[6]
IOU GPIOC
IU SYSTEM
IOU LCD
CFG[10]
Chip Power-On Configuration Bit [10], Input
SYNC/MPU LCD Interface Data Bit 5
GPIO Port C Bit 5
LVDATA[5]
43 GPC[5]
IOU GPIOC
IU SYSTEM
IOU LCD
CFG[9]
Chip Power-On Configuration Bit [9], Input
GPIO Port C Bit 4
LVDATA[4]
44 GPC[4]
IOU GPIOC
IU SYSTEM
IOU LCD
GPIO Port C Bit 4
CFG[8]
Chip Power-On Configuration Bit [8], Input
SYNC/MPU LCD Interface Data Bit 3
GPIO Port C Bit 3
LVDATA[3]
GPC[3]
45
46
47
48
IOU GPIOC
IOU LCD
LVDATA[2]
GPC[2]
SYNC/MPU LCD Interface Data Bit 2
GPIO Port C Bit 2
IOU GPIOC
IOU LCD
LVDATA[1]
GPC[1]
SYNC/MPU LCD Interface Data Bit 1
GPIO Port C Bit 1
IOU GPIOC
IOU LCD
LVDATA[0]
GPC[0]
SYNC/MPU LCD Interface Data Bit 0
GPIO Port C Bit 0
IOU GPIOC
OU LCD
LVDE
SYNC LCD Interface Data Enable, Output, High Active
MPU LCD Interface Register Select
GPIO Port D Bit 11
49 LRS
GPD[11]
OU LCD
IOU GPIOD
Sept., 11, 2018
Page 19 of 60
Rev 1.10
N9H20
Pin No
Name
Type
Group
Description
Note. By design limitation, GPD[11] function will be disable
when SPI1 engine is used.
SYNC LCD Interface VSYNC, Output, High Active
MPU I80 mode LCD Interface Read, active low
MPU M68 mode LCD Interface Read Write Enable/Disable ,
High Enable
LVSYNC
OU LCD
OU LCD
LRD
50
LEN
OU LCD
GPD[10]
IOU GPIOD
LCD Interface Data Enable, High Active.
Ground (0V)
51 VSS
G
GND
LHSYNC
LWR
OU LCD
OU LCD
SYNC LCD Interface HSYNC, Output, High Active
MPU I80 mode LCD Interfacer Write, active low
MPU M68 mode LCD interface R/W, High is read command
and Low is write instruction
GPIO Port D Bit 9
52
LR/W
OU LCD
GPD[9]
IOU GPIOD
53 VDD18
P
Core
Core Logic Power (1.8V)
LPCLK
OU LCD
OU LCD
SYNC LCD Interface Pixel Clock, Output
MPU LCD Interface Chip Enable, active low
GPIO Port B Bit 15
54 LCS
GPB[15]
IOU GPIOB
55 VDD33
P
G
I
I/O
I/O Power (3.3V)
56 ADC_VSS33
57 ADC_TP_YM
58 ADC_TP_XM
59 ADC_TP_XP
60 ADC_TP_YP
61 ADC_VDD33
62 ADC_AIN[2]
63 ADC_AIN[3]
64 ADC_AIN[4]
65 RTC_XOUT
66 RTC_XIN
67 RTC_VDD1.8V
68 VDD33
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
RTC
RTC
RTC
I/O
ADC Ground (0V)
Touch Panel YM
I
Touch Panel XM
I
Touch Panel XP
I
Touch Panel YP
P
I
ADC Power (3.3V)
ADC Analog Input Channel 2
ADC Analog Input Channel 3
ADC Analog Input Channel 4
32768Hz Crystal Output
I
I
O
I
32768Hz Crystal Input
P
P
RTC Power (1.8V)
I/O Power (3.3V)
GPA[6]
IOU GPIOA
OU SPI1
OU KPI
GPIO Port A Bit 6
69 SPI1_CS1_
KPI_SO[4]
SPI Port 1 Device Select 1, Output, Low Active
KPI Scan Out Bit 4
70 GPA[5]
IOU GPIOA
GPIO Port A Bit 5
Sept., 11, 2018
Page 20 of 60
Rev 1.10
N9H20
Pin No
Name
SPI0_CS1_
KPI_SO[3]
GPA[4]
Type
Group
Description
SPI Port 0 Device Select 1, Output, Low Active
KPI Scan Out Bit 3
OU SPI0
OU KPI
IOU GPIOA
IOU USB
OU KPI
GPIO Port A Bit 4
71 UHL_DM1
KPI_SO[2]
GPA[3]
USB Host 1.0 Lite Port 1, D-
KPI Scan Out Bit 2
IOU GPIOA
IOU USB
OU KPI
GPIO Port A Bit 3
72 UHL_DP1
KPI_SO[1]
GPA[2]
USB Host 1.0 Lite Port 1, D+
KPI Scan Out Bit 1
IOU GPIOA
OU LCD
GPIO Port A Bit 2
LMVSYNC
73
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
KPI Scan Out Bit 0
LFMARK
IU LCD
KPI_SO[0]
OU KPI
GPA[1]
74
IOU GPIOA
IU SD
GPIO Port A Bit 1
SD_CD_
SD Card Detect, Input, Low Active
GPIO Port A Bit 0
75 GPA[0]
IOU GPIOA
IU SYSTEM
OU SYSTEM
ID JTAG
IOD GPIOD
OD SPI1
OD PWM
IU JTAG
IOU GPIOD
OU UART
OU PWM
IU JTAG
IOU GPIOD
IU UART
OU PWM
OU JTAG
IOU GPIOD
IU UART
OU PWM
IU JTAG
IOU GPIOD
RST_
76
System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
JTAG Interface Test Clock, Input
GPIO Port D Bit 0
WDT_RST_
TCK
GPD[0]
77
SPI1_CS1_
SPI Port 1 Device Select 1, Output, Low Active
PWM Channel 0
PWM0
TMS
JTAG Interface Test Mode Select, Input
GPIO Port D Bit 1
GPD[1]
78
HUR_TXD
High-Speed UART TX Data, Output
PWM Channel 1
PWM1
TDI
JTAG Interface Test Data In, Input
GPIO Port D Bit 2
GPD[2]
79
HUR_RXD
High-Speed UART RX Data, Input
PWM Channel 2
PWM2
TDO
JTAG Interface Test Data Out, Output
GPIO Port D Bit 3
GPD[3]
80
HUR_CTS
High-Speed UART Clear-To-Send, Input, Low Active
PWM Channel 3
PWM3
TRST_
81
JTAG Interface Test Reset, Input, Low Active
GPIO Port D Bit 4
GPD[4]
Sept., 11, 2018
Page 21 of 60
Rev 1.10
N9H20
Pin No
Name
HUR_RTS
SPI0_CS1_
Type
Group
Description
OU UART
OU SPI0
High-Speed UART Reset-To-Send, Output, Low Active
SPI Port 0 Device Select 1, Output, Low Active
USB Device Connect Detect, Input, High Active
Core Logic Power (1.8V)
82 UD_CDET
83 VDD18
84 MVDD
85 MVSS
I
USB
P
P
G
P
--
G
P
P
G
P
O
O
G
Core
MVDD
MVDD
MVDD
NC
SDRAM I/O Power
SDRAM I/F Ground (0V)
MVREF
1/2 MVDD (0.9V) for DDR_VREF
when N9H20K11N is installation
SDRAM Ground (0V)
86
NC
87 VSSQ
MVDD
MVDD
I/O
88 VDDQ
SDRAM Power
89 VDD33
I/O Power (3.3V)
90 ADAC_HPVSS33
91 ADAC_HPVDD33
92 ADAC_HPOUT_L
93 ADAC_HPOUT_R
94 ADAC_AVSS33
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
Audio DAC Headphone Driver Ground (0V)
Audio DAC Headphone Driver Power (3.3V)
Audio Headphone Left Channel Output
Audio Headphone Right Channel Output
Audio DAC Ground (0V)
Audio DAC Reference Voltage Output, please connect 1uF
capacitor to DAC ground
95 ADAC_VREF
O
AUDIO
96 ADAC_AVDD33
97 VDD18
P
P
AUDIO
Core
Audio DAC Power (3.3V)
Core Logic Power (1.8V)
GPA[7]
98
IOU GPIOA
OU KPI
GPIO Port A Bit 7
KPI_SO[5]
KPI Scan Out Bit 5
ND[0]
99
IOU NAND
IU SYSTEM
IOU NAND
IU SYSTEM
IOU NAND
IU SYSTEM
IOU NAND
IU SYSTEM
IOU NAND
IU SYSTEM
IOU NAND
IU SYSTEM
IOU NAND
NAND Interface Data Bit [0]
CFG[0]
Chip Power-On Configuration Bit [0], Input
NAND Interface Data Bit [1]
ND[1]
100
CFG[1]
Chip Power-On Configuration Bit [1], Input
NAND Interface Data Bit [2]
ND[2]
101
CFG[2]
Chip Power-On Configuration Bit [2], Input
NAND Interface Data Bit [3]
ND[3]
102
CFG[3]
Chip Power-On Configuration Bit [3], Input
NAND Interface Data Bit [4]
ND[4]
103
CFG[4]
Chip Power-On Configuration Bit [4], Input
NAND Interface Data Bit [5]
ND[5]
104
CFG[5]
Chip Power-On Configuration Bit [5], Input
NAND Interface Data Bit [6]
105 ND[6]
Sept., 11, 2018
Page 22 of 60
Rev 1.10
N9H20
Pin No
106
Name
CFG[6]
Type
Group
Description
Chip Power-On Configuration Bit [6], Input
NAND Interface Data Bit [7]
IU SYSTEM
IOU NAND
IU SYSTEM
IU NAND
IOU GPIOD
IOU SD2
ND[7]
CFG[7]
NBUSY1_
Chip Power-On Configuration Bit [7], Input
NAND Interface Busy 1, Input, Low Active
GPIO Port D Bit 6
107 GPD[6]
SD2_DAT[2]
NBUSY0_
108 GPD[5]
SD Port 2 Data Bit 2
IU NAND
IOU GPIOD
IOU SD2
NAND Interface Busy 0, Input, Low Active
GPIO Port D Bit 5
SD2_DAT[3]
NWR_
SD Port 2 Data Bit 3
OU NAND
IOU GPIOD
IOU SD2
NAND Interface Write Enable, Output, Low Active
GPIO Port D Bit 8
109 GPD[8]
SD2_CMD
NRE_
SD Port 2 Command/Response
NAND Interface Read Enable, Output, Low Active
GPIO Port D Bit 7
OU NAND
IOU GPIOD
OU SD2
110 GPD[7]
SD2_CLK
SD Port 2 Clock, Output
NAND Interface Command-Latch-Enable, Output, High
Active
NCLE
OU NAND
111
112
GPE[11]
NALE
IOU GPIOE
OU NAND
IOU GPIOE
OU NAND
IOU GPIOE
IOU SD2
GPIO Port E Bit 11
NAND Interface Address-Latch-Enable, Output, High Active
GPIO Port E Bit 10
GPE[10]
NCS1_
NAND Interface Chip Select 1, Output, Low Active
GPIO Port E Bit 9
113 GPE[9]
SD2_DAT[0]
114 VSS
NCS0_
115 GPE[8]
SD2_DAT[1]
SD Port 2 Data Bit 0
G
GND
Ground (0V)
IU NAND
IOU GPIOE
IOU SD2
NAND Interface Chip Select 0, Output, Low Active
GPIO Port E Bit 8
SD Port 2 Data Bit 1
116 VDD33
URTXD
P
I/O
I/O Power (3.3V)
OU UART
IOU GPIOA
OU SPI1
IU UART
IOU GPIOA
OU LCD
UART TX Data, Output
117 GPA[10]
GPIO Port A Bit 10
SPI1_CS1_
SPI Port 1 Device Select 1, Output, Low Active
UART RX Data, Input
URRXD
GPA[11]
LMVSYNC
LFMARK
GPIO Port A Bit 11
118
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
IU LCD
Sept., 11, 2018
Page 23 of 60
Rev 1.10
N9H20
Pin No
Name
GPB[12]
119 SPI1_DO
LVDATA[23]
Type
Group
Description
IOU GPIOB
OU SPI1
IOU LCD
IOU GPIOB
IU SPI1
GPIO Port B Bit 12
SPI Port 1 Data Output
SYNC/MPU LCD Interface Data Bit 23
GPIO Port B Bit 11
GPB[11]
120 SPI1_DI
SPI Port 1 Data Input
LVDATA[22]
IOU LCD
IOU GPIOB
SYNC/MPU LCD Interface Data Bit 22
GPIO Port B Bit 10
GPB[10]
SPI Port 1 Device Select 0, Low Active;Output in Master
Mode;Input in Slave Mode
SYNC/MPU LCD Interface Data Bit 21
GPIO Port B Bit 9
121 SPI1_CS0_
IOU SPI1
LVDATA[21]
GPB[9]
IOU LCD
IOU GPIOB
SPI Port 1 Clock;Output in Master Mode;Input in Slave
Mode
122 SPI1_CLK
IOU SPI1
LVDATA[20]
IOU LCD
IOU GPIOB
IOU LCD
IOU GPIOB
IOU LCD
IOU GPIOB
IU I²S
SYNC/MPU LCD Interface Data Bit 20
GPIO Port B Bit 8
GPB[8]
123
LVDATA[19]
SYNC/MPU LCD Interface Data Bit 19
GPIO Port B Bit 7
GPB[7]
124
LVDATA[18]
SYNC/MPU LCD Interface Data Bit 18
GPIO Port B Bit 6
GPB[6]
125
I2S_DIN
I2S Interface Data Input
GPB[5]
126 I2S_DOUT
SD1_DAT[2]
GPB[4]
IOU GPIOB
OU I2S
GPIO Port B Bit 5
I2S Interface Data Output
SD Port 1 Data Bit 2
IOU SD1
IOU GPIOB
OU I²S
GPIO Port B Bit 4
127 I2S_WS
SD1_DAT[3]
GPB[3]
I2S Interface Word Select, Output
SD Port 1 Data Bit 3
IOU SD1
IOU GPIOB
IU I²S
GPIO Port B Bit 3
128 I2S_BCLK
SD1_CMD
I2S Interface Clock, Input
SD Port 1 Command/Response
IOU SD1
Sept., 11, 2018
Page 24 of 60
Rev 1.10
N9H20
3.4.2
N9H20R11N TQFP64 pin list
Name Type Group
SPI0_CLK
Pin No
Description
SPI Port 0 Clock;Output in Master Mode;Input in Slave
Mode
IOU SPI0
IOU GPIOD
IOU SPI0
1
2
GPD[12]
GPIO Port D Bit 12
SPI Port 0 Device Select 0, Low Active;Output in Master
Mode;Input in Slave Mode
GPIO Port D Bit 13
SPI0_CS0_
GPD[13]
SPI0_DI
GPD[14]
SPI0_DO
GPD[15]
XIN
IOU GPIOD
IU SPI0
SPI Port 0 Data Input
3
4
IOU GPIOD
OU SPI0
GPIO Port D Bit 14
SPI Port 0 Data Output
IOU GPIOD
GPIO Port D Bit 15
5
6
7
8
9
I
XTAL
XTAL
Core
12MHz Crystal Input
XOUT
O
P
P
P
12MHz Crystal Output
VDD18
Core Logic Power (1.8V)
SDRAM Power (3.3V)
MVDD
MVDD
PLL_UD_VDD18
PLL & USB PLL & USB2.0 Device Core Power (1.8V)
10 UD_DM
I/O USB
I/O USB
USB 2.0 Device D-.
11 UD_DP
USB 2.0 Device D+.
12 UD_VDD33
13 UD_REXT
P
USB
USB
USB 2.0 Device PHY 3.3V
O
External Resistor 12.1K resistor connected to ground
SYNC/MPU LCD Interface Data Bit 15
GPIO Port C Bit 15
LVDATA[15]
IOU LCD
14
GPC[15]
IOU GPIOC
IOU LCD
LVDATA[14]
SYNC/MPU LCD Interface Data Bit 14
GPIO Port C Bit 14
15
GPC[14]
IOU GPIOC
IOU LCD
LVDATA[13]
SYNC/MPU LCD Interface Data Bit 13
GPIO Port C Bit 13
16
GPC[13]
IOU GPIOC
IOU LCD
LVDATA[12]
SYNC/MPU LCD Interface Data Bit 12
GPIO Port C Bit 12
17
GPC[12]
IOU GPIOC
IOU LCD
LVDATA[11]
SYNC/MPU LCD Interface Data Bit 11
GPIO Port C Bit 11
18
GPC[11]
IOU GPIOC
IOU LCD
LVDATA[10]
SYNC/MPU LCD Interface Data Bit 10
GPIO Port C Bit 10
19
GPC[10]
IOU GPIOC
IOU LCD
LVDATA[9]
SYNC/MPU LCD Interface Data Bit 9
GPIO Port C Bit 9
20
GPC[9]
IOU GPIOC
IOU LCD
21 LVDATA[8]
SYNC/MPU LCD Interface Data Bit 8
Sept., 11, 2018
Page 25 of 60
Rev 1.10
N9H20
Pin No
Name
GPC[8]
Type
Group
Description
IOU GPIOC
IOU LCD
GPIO Port C Bit 8
LVDATA[7]
GPC[7]
SYNC/MPU LCD Interface Data Bit 7
GPIO Port C Bit 7
22
23
24
25
26
27
28
29
IOU GPIOC
IOU LCD
LVDATA[6]
GPC[6]
SYNC/MPU LCD Interface Data Bit 6
GPIO Port C Bit 6
IOU GPIOC
IOU LCD
LVDATA[5]
GPC[5]
SYNC/MPU LCD Interface Data Bit 5
GPIO Port C Bit 5
IOU GPIOC
IOU LCD
LVDATA[4]
GPC[4]
GPIO Port C Bit 4
IOU GPIOC
IOU LCD
GPIO Port C Bit 4
LVDATA[3]
GPC[3]
SYNC/MPU LCD Interface Data Bit 3
GPIO Port C Bit 3
IOU GPIOC
IOU LCD
LVDATA[2]
GPC[2]
SYNC/MPU LCD Interface Data Bit 2
GPIO Port C Bit 2
IOU GPIOC
IOU LCD
LVDATA[1]
GPC[1]
SYNC/MPU LCD Interface Data Bit 1
GPIO Port C Bit 1
IOU GPIOC
IOU LCD
LVDATA[0]
GPC[0]
SYNC/MPU LCD Interface Data Bit 0
GPIO Port C Bit 0
IOU GPIOC
OU LCD
LVDE
SYNC LCD Interface Data Enable, Output, High Active
MPU LCD Interafec Register Select
GPIO Port D Bit 11
30 LRS
OU LCD
GPD[11]
LVSYNC
IOU GPIOD
OU LCD
SYNC LCD Interface VSYNC, Output, High Active
MPU I80 mode LCD Interface Read, active low
LCD Interface Data Enable, High Active.
SYNC LCD Interface HSYNC, Output, High Active
MPU I80 mode LCD Interface Write, active low
GPIO Port D Bit 9
31 LRD
OU LCD
GPD[10]
LHSYNC
IOU GPIOD
OU LCD
32 LWR
OU LCD
GPD[9]
LPCLK
IOU GPIOD
OU LCD
SYNC LCD Interface Pixel Clock, Output
MPU LCD Interface Chip Enable, active low
GPIO Port B Bit 15
33 LCS
GPB[15]
OU LCD
IOU GPIOB
34 ADC_VDD33
35 RTC_VDD1.8V
36 VDD33
P
P
P
ADC
RTC
I/O
ADC Power (3.3V)
RTC Power (1.8V)
I/O Power (3.3V)
GPA[5]
37
IOU GPIOA
OU SPI0
GPIO Port A Bit 5
SPI0_CS1_
SPI Port 0 Device Select 1, Output, Low Active
GPIO Port A Bit 4
38 GPA[4]
IOU GPIOA
Sept., 11, 2018
Page 26 of 60
Rev 1.10
N9H20
Pin No
39
Name
UHL_DM1
Type
Group
Description
USB Host 1.0 Lite Port 1, D-
IOU USB
GPA[3]
IOU GPIOA
IOU USB
GPIO Port A Bit 3
UHL_DP1
GPA[2]
USB Host 1.0 Lite Port 1, D+
GPIO Port A Bit 2
IOU GPIOA
OU LCD
40 LMVSYNC
LFMARK
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
JTAG Interface Test Clock, Input
GPIO Port D Bit 0
IU LCD
RST_
41
IU SYSTEM
OU SYSTEM
ID JTAG
IOD GPIOD
OD SPI1
WDT_RST_
TCK
GPD[0]
42
SPI1_CS1_
SPI Port 1 Device Select 1, Output, Low Active
PWM Channel 0
PWM0
TMS
OD PWM
IU JTAG
IOU GPIOD
OU UART
OU PWM
IU JTAG
IOU GPIOD
IU UART
OU PWM
OU JTAG
IOU GPIOD
OU PWM
IU JTAG
IOU GPIOD
OU SPI0
JTAG Interface Test Mode Select, Input
GPIO Port D Bit 1
GPD[1]
43
HUR_TXD
High-Speed UART TX Data, Output
PWM Channel 1
PWM1
TDI
JTAG Interface Test Data In, Input
GPIO Port D Bit 2
GPD[2]
44
HUR_RXD
High-Speed UART RX Data, Input
PWM Channel 2
PWM2
TDO
JTAG Interface Test Data Out, Output
GPIO Port D Bit 3
45 GPD[3]
PWM3
PWM Channel 3
TRST_
JTAG Interface Test Reset, Input, Low Active
GPIO Port D Bit 4
46 GPD[4]
SPI0_CS1_
47 UD_CDET
48 VDD18
49 MVDD
50 VDDQ
51 AVDD33
52 VDD18
SPI Port 0 Device Select 1, Output, Low Active
USB Device Connect Detect, Input, High Active
Core Logic Power (1.8V)
I
USB
P
P
P
P
P
Core
MVDD
MVDD
AUDIO
Core
SDRAM I/O Power (3.3V)
SDRAM Power (3.3V)
Audio DAC Power (3.3V)
Core Logic Power (1.8V)
GPA[7]
53
IOU GPIOA
OU SYSTEM
IOU GPIOD
GPIO Port A Bit 7
CFG[0]
Chip Power-On Configuration Bit [0], Input
GPIO Port D Bit 6
54 GPD[6]
Sept., 11, 2018
Page 27 of 60
Rev 1.10
N9H20
Pin No
Name
SD2_DAT[2]
GPD[5]
Type
Group
Description
IOU SD2
SD Port 2 Data Bit 2
GPIO Port D Bit 5
SD Port 2 Data Bit 3
GPIO Port D Bit 8
IOU GPIOD
IOU SD2
55
56
57
58
59
SD2_DAT[3]
GPD[8]
IOU GPIOD
IOU SD2
SD2_CMD
GPD[7]
SD Port 2 Command/Response
GPIO Port D Bit 7
IOU GPIOD
OU SD2
SD2_CLK
GPE[9]
SD Port 2 Clock, Output
GPIO Port E Bit 9
IOU GPIOE
IOU SD2
SD2_DAT[0]
GPE[8]
SD Port 2 Data Bit 0
IOU GPIOE
IOU SD2
GPIO Port E Bit 8
SD2_DAT[1]
SD Port 2 Data Bit 1
60 VDD33
URTXD
61 GPA[10]
SPI1_CS1_
P
I/O
I/O Power (3.3V)
OU UART
IOU GPIOA
OU SPI1
IU UART
IOU GPIOA
OU LCD
IU LCD
UART TX Data, Output
GPIO Port A Bit 10
SPI Port 1 Device Select 1, Output, Low Active
UART RX Data, Input
URRXD
GPA[11]
LMVSYNC
LFMARK
ISDA
GPIO Port A Bit 11
62
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
I2C Interface Data
IOU I2C
GPB[14]
LFMARK
LMVSYNC
ISCK
IOU GPIOB
IU LCD
GPIO Port B Bit 14
63
64
MPU LCD Interface Frame Mark, Input
MPU LCD Interface Mode VSYNC, Output
I2C Interface Clock, Output
GPIO Port B Bit 13
OU LCD
OU I2C
GPB[13]
IOU GPIOB
E-PAD VSS
P
GND
Ground (0V)
Note:
TYPE
I
DESCRIPTION
Input
O
Output
I/O
IU
Input / Output
Input with internal pull high (50K)
Output with internal pull high (50K)
OU
IOU
Bi-direction with internal pull high (50K)
Sept., 11, 2018
Page 28 of 60
Rev 1.10
N9H20
TYPE
ID
DESCRIPTION
Input with internal pull low (50K)
Output with internal pull low (50K)
Bi-direction with internal pull low (50K)
Analog Power or Digital Power
Analog GND or Digital GND
OD
IOD
P
G
Sept., 11, 2018
Page 29 of 60
Rev 1.10
N9H20
4
BLOCK DIAGRAM
4.1
N9H20 Series Block Diagram
ICE_CTRL
MMU, I/D
Cache
8KB/8KB
ARM926EJ-S
M
PLLX2
CLKGEN
S
GCR
S
AHB – 1
M
S
S
S
S
Display
Controller
EDMA/
APB
SRAM
Controller
(8KB)
SDR/DDR/
DDR2 SDRAM
Controller
AHB
Bridge
ROM
(16KB)
M
S
Bridge
M
M
S
S
S
S
AHB – 4
AHB – 2
M
S
M
S
IIS
Controller
SPU
AHB – 3
M
S
M
S
M
S
M
S
M
S
BitBLT
SIC
JPEG
UHC
UDC
Timer/
WDT
AIC
S
RTC
S
S
APB
S
S
S
S
S
S
Audio
DAC
USB 2.0
PHY
ADC
UART X
2
SPI X 2
I2C
GPIO
PWM X
4
USB1.1
Figure 4.1 N9H20 Series Block Diagram
Sept., 11, 2018
Page 30 of 60
Rev 1.10
N9H20
5
FUNCTIONAL DESCRIPTION
ARM® ARM926EJ-S CPU Core
5.1
5.1.1
Overview
The ARM926EJ-S CPU core is a member of the ARM9 family of general-purpose
microprocessors. The ARM926EJ-S CPU core is targeted at multi-tasking applications where full
memory management, high performance, and low power are all important.
The ARM926EJ-S CPU core supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling
the user to choose between high performance and high code density.
The ARM926EJ-S processor provides support for external coprocessor enabling floating-point or
other application-specific hardware acceleration to be added. The ARM926EJ-S CPU core
implements ARM architecture version 5TEJ.
The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-
performance processor subsystem, including:
An ARM9EJ-S integer core.
A Memory Management Unit (MMU).
Separate instruction and data cache.
Separate instruction and data AMBA AHB bus interfaces.
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Rev 1.10
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5.2
System Manager
Overview
5.2.1
The system management describes following information and functions.
System Memory Map
Power-On Setting
Bus Arbitration Mode
Power Management
IBR (Internal Boot ROM) Sequence
System management registers for product ID, functional reset and multi-function pin control.
5.3
Clock Controller (CLK_CTL)
Overview
5.3.1
The clock controller generates the clocks for the whole chip, it include all of IPs on AHB, APB and
engine clock like USB, UART and so on. There are a PLL in this chip, and the PLL clock source is from
the external crystal input. It also implements the power control function, include the individually clock
on or off control register, clock source selector and divider. These functions minimize the extra power
consumption and the chip run on the only just condition. On the power down mode the controller turn
off the crystal oscillator to minimize the chip power consumption.
5.4
SDRAM Interface Controller (SDIC)
Overview
5.4.1
The SDRAM Controller support SDR, DDR, Low-Power DDR and DDR2 type SDRAM. The memory
device size type can be from 16M bit and up to 1G bits. Only 16-bit data bus width is supported. The
total system memory size can be from 2M-byte and up to 32M-byte for different SDRAM configuration.
5.5
2D Blitting Accelerator
Overview
5.5.1
The 2D blitting accelerator features are built on top of the FlashLite Bitmap rendering feature. It
improves rendering performance of bitmap objects (source image) onto the frame buffer (destination
image).
There are two functions support. First is BitBLT function with effects of Scale, Rotate, Shear and
Reflect. The second is Fill function to fill a rectangle in the frame buffer.
Sept., 11, 2018
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Rev 1.10
N9H20
5.6
JPEG Codec (JPEG)
Overview
5.6.1
The JPEG Codec supports Baseline Sequential Mode JPEG still image compression and
decompression that is fully compliant with ISO/IEC International Standard 10918-1 (T.81).
5.7
LCD Display Interface Controller (VPOST)
Overview
5.7.1
The main purpose of Display Controller is used to display the video/image data to LCD device or
connect with external TV-encoder. The video/image data source may come from the JPEG decoder
and the OSD pattern which have been stored in system memory (SDRAM). The input data format of
the display controller can be packet YUV422, packet YUV444, packet RGB444, packet RGB565,
packet RGB666, and packet RGB888. The OSD (On Screen Display) function supports packet
YUV422 and 8/16/24-bit direct-color mode. The LCD controller supports both sync-type and MPU-type
LCDM. This LCD Controller is a bus master and can transfer display data from system memory
(SDRAM) without CPU intervention.
5.8
Sound Processing Unit (SPU)
Overview
5.8.1
The SPU performs 32 channels audio input and 16-bit stereo output to DAC and I2S. SPU support 3
data-types (E-MDPCM (4bit), PCM16, LP8) with event and raw PCM16 mono/stereo and Tone.
5.9
I2S Controller (I2S)
Overview
5.9.1
The audio controller consists of I2S protocols to interface with external audio CODEC. The I2S
interface supports 16, 18, 20 and 24-bit left/right precision in record and playback. When operating in
18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word. Each left/right-channel
sample has 24/20/18 MSB bits of valid data and other LSB bits are the padding zeros. When operating
in 16-bit precision, right-channel sample is stored in MSB of a 32-bit word and left-channel sample is
stored in LSB of a 32-bit word.
5.10 Storage Interface Controller
5.10.1 Overview
The Storage Interface Controller (SIC) has SIC_DMA unit and SIC_FMI unit. The SIC_DMAC unit
provides a DMA (Direct Memory Access) function for FMI to exchange data between system memory
(ex. SDRAM) and shared buffer (128 bytes), and the SIC_FMI unit control the interface of
SD/SDHC/SDIO/MMC or NAND/SM. The serial interface controller can support SD/SDHC/SDIO/MMC
card and NAND-type flash and the FMI is cooperated with DMAC to provide a fast data transfer
between system memory and cards.
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5.11 USB 2.0 Device Controller (USBD)
5.11.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains
both the AHB master interface and AHB slave interface. CPU programs the USB controller registers
through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data
to memory or read data from memory through the AHB master interface. The USB device controller is
complaint with USB 2.0 specification and it contains four configurable endpoints in addition to control
endpoint.These endpoints could be configured to BULK, INTERRUPT or ISO. The USB device
controller has a built-in DMA to relieve the load of CPU.
5.12 USB Host Controller (USBH)
5.12.1 Overview
The Universal Serial Bus (USB) is a low-cost, low-to mid-speed peripheral interface standard intended
for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a high-bandwidth
parallel interface. The USB is a 4-wire serial cable bus that supports serial data exchange between a
Host Controller and a network of peripheral devices. The attached peripherals share USB bandwidth
through a host-scheduled, token-based protocol. Peripherals may be attached, configured, used, and
detached, while the host and other peripherals continue operation (i.e. hot plug and unplug is
supported).
5.13 Enhanced DMA Controller
5.13.1 Overview
The N9H20 contains an enhanced direct memory access (EDMA) controller that transfers data to and
from memory or transfer data to and from APB. The EDMA controller has five-channel DMA that
include a one channel VDMA (Video-DMA, Memory-to-Memory) and four channels PDMA (Peripheral-
to-Memory or Memory-to-Peripheral). For channel0 VDMA mode, it also support color format transform
and stripe mode transfer. For PDMA channel (EDMA CH1~CH4), it can transfer data between the
Peripherals APB IP (ex: UART, SPI, ADC….) and Memory.
The N9H20 also support hardware scatter-gather function, software can set CSRx [SG_EN] to enable
scatter-gather function.
5.14 Advanced Interrupt Controller (AIC)
5.14.1 Overview
An interrupt temporarily changes the execution sequence of a program to react to a particular event
such as power failure, watchdog timer timeout, and engine complete, system events, external event
trigger and so on. The ARM9 processor provides two modes of interrupts, the Fast Interrupt (FIQ)
mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception mode is
occurred when the NIRQ input is asserted. Similarly, the FIQ exception mode is occurred when the
NFIQ input is asserted. The FIQ mode has privilege over the IRQ mode and can preempt an ongoing
IRQ mode. It is possible to ignore the NFIQ and the NIRQ by setting the F-bit and I-bit in the current
program status register (CPSR).
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N9H20
5.15 General Purpose I/O (GPIO)
5.15.1 Overview
General Purpose I/O are shared with special feature functions.
Supported Features of these I/O are: input or output facilities, pull-up resistors.
All these general purpose I/O functions are achieved by software programming setting and I/O cells
selected from SMIC universal standard I/O Cell Library. And the following figures illustrate the control
mechanism to achieve the GPIO functions.
5.16 Timer Controller (TMR)
5.16.1 Overview
The timer module includes four channels, TIMER0~TIMER3, which allow you to easily implement a
counting scheme for use. The timer can perform functions like frequency measurement, event
counting, interval measurement, clock generation, delay timing, and so on. The timer possesses
features such as adjustable resolution, programmable counting period, and detailed information. The
timer can generate an interrupt signal upon timeout, or provide the current value of count during
operation.
5.17 Watchdog Timer (WDT)
5.17.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
5.18 Real Time Clock (RTC)
5.18.1 Overview
Real Time Clock (RTC) block can be operated by independent power supply while the system power is
off. The RTC uses a 32.768 KHz external crystal. It can transmit data to CPU with BCD values. The
data includes the time by (second, minute and hour), the day by (day, month and year). In addition, to
achieve better frequency accuracy, the RTC counter can be adjusted by software.
The built in RTC is designed to generate the alarm interrupt and periodic interrupt signals. The period
interrupt can be 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second. The alarm interrupt indicates that
time counter and calendar counter have counted to a specified time recorded in TAR and CAR.
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N9H20
5.19 I2C Synchronous Serial Interface Controller (I2C)
5.19.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
Serial, 8-bit oriented bi-directional data transfers can be made up to100 Kbit/s in Standard-mode, and
400 Kbit/s in the Fast-Mode. or up to 3.4 Mbit/s in the High-speed mode. Only 100kbps and 400kbps
modes are supported directly. For High-speed mode special IOs are needed. If these IOs are available
and used, then High-speed mode is also supported.
5.20 Pulse Width Modulation (PWM)
5.20.1 Overview
There are 4 PWM-Timers. The 4 PWM-Timers has 2 Pre-scale, 2 clock divider, 4 clock selectors, 4 16-
bit counters, 4 16-bit comparators, 2 Dead-Zone generators. They are all driven by system clock. Each
can be used as a timer and issues interrupt independently.
5.21 UART Interface Controller (UART)
5.21.1 Overview
The N9H20K provides two channels of Universal Asynchronous Receiver/Transmitters (UART).
UART0 supports High Speed UART and UART1 perform Normal Speed UART, besides, only UART0
support flow control function.
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on
data characters received from the peripheral, and a parallel-to-serial conversion on data characters
received from the CPU. Each UART channel supports six types of interrupts including transmitter FIFO
empty interrupt(Int_THRE), receiver threshold level reaching interrupt (Int_RDA), line status interrupt
(overrun error or parity error or framing error or break interrupt) (Int_RLS) , time out interrupt
(Int_Tout), MODEM status interrupt (Int_Modem) and Wake up status interrupt (Int_WakeUp).
5.22 SPI Interface Controller (SPI Master/Slaver)
5.22.1 Overview
The MICROWIRE/SPI Synchronous Serial Interface performs a serial-to-parallel conversion on data
characters received from the peripheral, and a parallel-to-serial conversion on data characters
received from CPU. This interface can drive up to 2 external peripherals and is seen as the master or
can be driven as the slave.
It can generate an interrupt signal when data transfer is finished and can be cleared by writing 1 to the
interrupt flag. The active level of device/slave select signal can be chosen to low active or high active,
which depends on the peripheral it’s connected. Writing a divisor into DIVIDER register can program
the frequency of serial clock output when it is as the master. This master/slave core contains four 32-
bit transmit/receive buffers, and can provide burst mode operation. The maximum bits can be
transmitted/received is 32 bits, and can transmit/receive data up to four times successively.
There is EDMA mode for transmit or received data access by enable the EDMA bit in SPI_EDMA[0]
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N9H20
5.23 Analog to Digital Converter (ADC)
5.23.1 Overview
The 10-bit analog to digital converter (ADC) in this chip is a successive approximation type ADC with
3-channel inputs. It needs 34 cycles to convert one sample, the maximum conversion rate is 500K/sec,
so the maximum input clock to ADC is 17MHz, so and the operating voltage range is 3.3V +/- 10%.
The power down mode is supported in the ADC.
The touch screen interfaces are supported in this chip, it contains 4-wire resistive touch screen. The
four switches to bias XP, XM, YP, YM are embedded in this chip. The CPU could access the ADC
control register by APB bus, and the ADC output an interrupt signal to AIC to represent the completion
of conversion.
5.24 Keypad Interface (KPI)
5.24.1 Overview
The KPI supports release multiple keys, press multiple keys scan interrupt and specified INT_3KEYs
interrupt for chip reset. If the 3 pressed keys matches with the 3 keys defined in KPI3KCONF, it will
generate an interrupt and chip reset (ENRST must setting) depend on the ENRST setting. The
interrupt is generated whenever it detects any key in the keypad pressing or releasing or waking up
from IDLE or three-key reset. User can know the interrupt source by querying KPISTATUS register.
Sept., 11, 2018
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N9H20
6
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
6.1
Parameters
Values
Ambient Temperature
-20 °C ~ 85 °C
-40 °C ~ 125 °C
-0.3V ~ 3.6V
-0.5V ~ 1.5V
-0.5V ~ 4.6V
100mA
Storage Temperature
Voltage On Any Pin
Power Supply Voltage (Core Logic)
Power Supply Voltage (I/O Buffer)
Injection Current (Latch-Up Testing)
Crystal Frequency
1MHz ~ 27MHz
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of
the device.
Sept., 11, 2018
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Rev 1.10
N9H20
6.2
DC Electrical Characteristics
6.2.1
N9H20 Series DC Electrical Characteristics
(VDD-VSS=3.3 V, TA = 25C, FOSC = 12 MHz unless otherwise specified.)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDD33
I/O Buffer Post-Driver
Voltage
3.0
3.3
3.6
V
MVDD33 SDRAM Operation Voltage
(for N9H20K11N)
SDRAM_CLK=96MHz
DDR_CLK=96MHz
3.0
1.7
1.7
3.3
1.8
1.8
3.6
1.9
1.9
V
DDR Operation Voltage
MVDD18
(for N9H20K31N or
N9H20K51N)
Core Logic and I/O Buffer
Pre-Driver Voltage
CPU_CLK=192MHz
VDD18
V
RTC_VDD
IRTC_VDD
-
RTC Power Supply
RTC Supply Current
1.2
-
1.8
-
V
uA
V
RTC_VDD≦1.8V
4
-
-
VIH
VIL
VT
Input High Voltage
Input Low Voltage
Threshold Point
2.0
-0.3
1.45
5.5
0.8
1.74
V
1.58
V
Schmitt Trigger Low to High
Threshold Point
VT+
VT-
1.44
0.89
1.50
0.94
1.56
0.99
V
V
Schmitt Trigger High to Low
Threshold Point
FCPU = 192MHz,
MCLK = 96Hz,
VDD18 = 1.8V
-
140
ICC
Core Power Supply Current
-
mA
-
-
IL
Input Leakage Current
-10
-10
10
10
uA
uA
Tri-State Output Leakage
Current
IOZ
RPU
RPD
VOL
VOH
Pull-Up Resistor
39
40
-
65
56
-
116
108
0.4
-
k
k
V
Pull-Down Resistor
Output Low Voltage
Output High Voltage
-
2.4
V
Low Level Output 4mA I/O VOL = 0.4V
Current
-
-
-
-
IOL
IOH
4.0
5.9
mA
mA
High Level Output 4mA I/O VOH = 2.4V
Sept., 11, 2018
Page 39 of 60
Rev 1.10
N9H20
Current
6.2.2
ADC Characteristics
Parameter
Min.
Typ.
Max.
Unit
SAR ADC Input Voltage Range
Resolution of ADC
3.0
-
-
-
3.6
10
V
bit
Signal-to-Noise Plus Distortion of ADC from Line In
-
-
TBD
±2.0
-
-
dB
Integral Non-Linearity of ADC
LSB
Differential Non-Linearity of ADC
-
-
-
±0.8
10
-
-
-
LSB
bit
No Missing Code
AD Conversion Rate=ADCCLK/16
400
KHz
6.2.3
Audio DAC Characteristics
Parameter
Min
Typ
Max
Unit
V
Operating Voltage
3.0
3.3
3.6
Reference Voltage
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DAC_VDD/2
0.1
-
-
Reference Capacitor
uF
Full Scale output voltage
Full Scale output voltage
Maximum Output Power
Maximum Output Power @ 32ohm load
Maximum Output Power @ 16ohm load
L-Channel SNR
0.74
Vrms
Vpp
mW
mW
mW
dBV
dBV
dB
-
2.08
-
52
46
41
-
-
-
86
85
-64
-64
-63
-63
-62
-62
-
-
-
-
-
-
-
-
R-Channel SNR
L-Channel THD+N
R-Channel THD+N
dB
L-Channel THD+N @ 32ohm load
R-Channel THD+N @ 32ohm load
L-Channel THD+N @ 16ohm load
R-Channel THD+N @ 16ohm load
dB
dB
dB
dB
Test conditions: RL = 10K / 50pF, BW = 20Hz ~ 20KHz, Freq.= 1KHz, Sample Rate = 48KHz.
Sept., 11, 2018
Page 40 of 60
Rev 1.10
N9H20
6.3
AC Electrical Characteristics
External 12 MHz Crystal
6.3.1
t
CLCL
t
t
CLCH
CLCX
t
t
CHCL
CHCX
Note: Duty cycle is 50%.
PARAMETER
Clock High Time
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITION
tCHCX
tCLCX
tCLCH
tCHCL
20
20
-
-
-
-
-
125
125
10
nS
nS
nS
nS
Clock Low Time
Clock Rise Time
Clock Fall Time
-
10
Symbol
FXIN
Parameter
Min.
-
Typ.
12
Max.
Unit
MHz
%
Clock Input Frequency
Clock Input Duty Cycle
-
XINDUTY
45
50
55
Sept., 11, 2018
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Rev 1.10
N9H20
6.3.2
Power-on Sequence & RESET
6.3.2.1 Power up sequence
Higher Voltage IO (3.3V) First
Sequence: T33 ≥ T18 (The time of delay gap between < 500uS is prefer)
6.3.2.2 Power down Sequence
The lower voltage (1.8V) should be powered down first
Sequence: T18 ≥ T33
Note.
-
-
T18 represents 1.8V powered time for Core power
T33 represents 3.3V powered time for I/O power
Sept., 11, 2018
Page 42 of 60
Rev 1.10
N9H20
6.3.3
I2C Interface
Sept., 11, 2018
Page 43 of 60
Rev 1.10
N9H20
6.3.4
I2S Interface
FABCLK
TAWL
TAWH
I2S_BCLK
TAISU
TAIH
Input Mode
I2S_DIN
Output Mode
I2S_WS
I2S_DOUT
TAODLY
TAOH
Symbol
FABCLK
TAWL
Parameter
Min.
-
Typ.
Max.
Unit
I2S_BCLK Clock Frequency
I2S_BCLK Clock Low Time
I2S_BCLK Clock High Time
I2S_DIN Setup Time
-
-
-
-
-
16
-
MHz
ns
31.25
31.25
10
TAWH
-
ns
TAISU
-
ns
TAIH
I2S_DIN Hold Time
10
-
ns
I2S_DOUT Output Delay
Time
ns
TAODLY
TAOH
-
-
-
0.5
-
I2S_DOUT Output Hold Time
0.1
ns
Sept., 11, 2018
Page 44 of 60
Rev 1.10
N9H20
6.3.5
LCD/ Display Interface
SYNC Type LCD
LPCLK
FLPCLK
TLWL
TLWH
LHSYNC
LVSYNC
LVDE
LVDATA[15:0]
TLODLY
TLOH
Symbol
FLPCLK
TLWL
Parameter
LPCLK Clock Frequency
LPCLK Clock Low Time
LPCLK Clock High Time
Min.
Typ.
Max.
Unit
MHz
ns
-
-
-
-
27
-
18.5
18.5
TLWH
-
ns
LHSYNC, LVSYNC, LVDE and
LVDATA Output Delay Time
ns
TLODLY
-
-
-
1.3
-
LHSYNC, LVSYNC, LVDE and
LVDATA Output Hold Time
ns
TLOH
0.67
Sept., 11, 2018
Page 45 of 60
Rev 1.10
N9H20
MPU Type LCD
LPCLK (CS_)
TLAS
TLAH
LVDE (RS)
TLCSS
TLCSH
TLWR
80 Mode:
LHSYNC (WR_)
TLDODLY
TLDOH
LVDATA[15:0]
TLEN
68 Mode:
LVSYNC (EN)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
TLCSS
TLCSH
TLAS
CS_ to WR_ Setup Time
CS_ to WR_ Hold Time
RS to WR_ Setup Time
RS to WR_ Hold Time
LVDATA Output Delay Time
LVDATA Output Hold Time
WR_ Pulse Width
2
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
-
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
TLAH
TLDODLY
TLDOH
TLWR
TLEN
1
1
1
80 Mode
68 Mode
EN Pulse Width
Note: Where PCLK is APB bus clock.
Sept., 11, 2018
Page 46 of 60
Rev 1.10
N9H20
6.3.6
SPI Interface
FSPCLK
TSPWL
TSPWH
SPI0_CLK
TSPISU
TSPIH
Input Mode
SPI0_DI
Output Mode
SPI0_DO
TSPODLY
TSPOH
Symbol
FSPCLK
TSPWL
Parameter
Min.
Typ.
Max.
Unit
MHz
ns
SPI0_CLK Clock Frequency
SPI0_CLK Clock Low Time
SPI0_CLK Clock High Time
SPI0_DI Setup Time
-
-
-
-
-
-
-
-
25
-
20
20
10
10
-
TSPWH
TSPISU
TSPIH
-
ns
-
ns
SPI0_DI Hold Time
-
ns
TSPODLY
TSPOH
SPI0_DO Output Delay Time
SPI0_DO Output Hold Time
1
-
ns
0.2
ns
Sept., 11, 2018
Page 47 of 60
Rev 1.10
N9H20
6.3.7
NAND Interface
NCS0_
NCS1_
NALE
NCLE
TNWL
TNWH
NWR_
TNODLY
TNOH
ND[7:0]
(write)
NRE_
TNISU
TNIH
ND[7:0]
(Read)
Symbol
TNWL
Parameter
Min.
10
10
-
Typ.
Max.
Unit
ns
Write Pulse Low Width
NWR_ High Hold Time
-
-
-
-
-
-
-
-
TNWH
ns
TNODLY
TNOH
ND[7:0] Output Delay Time
ND[7:0] Output Hold Time
ND[7:0] Data in Setup Time
ND[7:0] Data in hold time
2.5
-
ns
10
3.2
1
ns
TNISU
TNIH
-
ns
-
ns
Sept., 11, 2018
Page 48 of 60
Rev 1.10
N9H20
6.3.8
SD Card Interface
FSDCLK
TSDWL
TSDWH
SDCLK
TSDISU
TSDIH
Input Mode
SDCMD,
SDDAT[3:0]
Output Mode
SDCMD,
SDDAT[3:0]
TSDODLY
TSDOH
Symbol
Clock SDCLK
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency in Data
Transfer Mode
FSDCLK
-
-
-
24
MHz
KHz
Clock Frequency in
Identification Mode
FSDCLK
100
400
TSDWL
TSDWH
Clock Low Time
Clock High Time
10
10
-
-
-
-
ns
ns
Input SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDISU
TSDIH
Input Setup Time
Input Hold Time
6
2
-
-
-
-
ns
ns
Output SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDODLY
TSDOH
Output Delay Time
Output Hold Time
-
-
-
14
-
ns
ns
2.5
Sept., 11, 2018
Page 49 of 60
Rev 1.10
N9H20
6.3.9
USB PHY Specifications
6.3.9.1 USB DC Electrical Characteristics
Symbol
VIH
Parameter
Input high (driven)
Conditions
Min.
2.0
-
Typ
Max.
Unit
V
-
-
-
-
0.8
-
Input low
V
VIL
VDI
Differential input sensitivity
|PADP-PADM|
0.2
V
Differential
Includes VDI range
0.8
-
2.5
V
VCM
VSE
common-mode range
Single-ended receiver threshold
Receiver hysteresis
Output low (driven)
0.8
-
-
2.0
-
V
mV
V
400
0
-
-
-
-
-
0.3
VOL
Output high (driven)
Output signal cross voltage
Pull-up resistor
2.8
1.3
1.425
14.25
3.6
V
VOH
VCRS
RPU
2.0
V
1.575
15.75
kΩ
kΩ
Pull-down resistor
VTRM
Termination Voltage for upstream port
pull up (RPU)
3.0
-
3.6
V
ZDRV
Driver output resistance
Transceiver capacitance
Steady state drive*
Pin to VSS
28
-
-
-
49.5
20
Ω
CIN
VIH
pF
Note: Driver output resistance does not include series resistor resistance.
6.3.9.2 USB Full-Speed Driver Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ
Max.
Unit
Rising time
Falling time
CL = 50p
CL = 50p
4
4
-
-
20
20
ns
ns
TFR
TFF
6.3.9.3 USB High-Speed Driver Electrical Characteristics
Symbol
Parameter
Rising time
Falling time
Conditions
CL = 5p
Min.
500
500
Typ
Max.
Unit
ps
TFR
TFF
CL = 5p
ps
Sept., 11, 2018
Page 50 of 60
Rev 1.10
N9H20
6.3.10 Specification of Low Voltage Reset
Parameter
Operation voltage
Conditions
Min.
2
Typ
3.3
Max.
3.6
Unit
-20℃ ~ +85℃
VDD rises
V
V
V
2.16
2.115
2.4
2.64
2.585
LVR Detect Levels
VDD falls
2.35
Sept., 11, 2018
Page 51 of 60
Rev 1.10
N9H20
6.4
Thermal Characteristics of N9H20K Package
Thermal Performance of LQFP-128 under Forced Convection
Sept., 11, 2018
Page 52 of 60
Rev 1.10
N9H20
7
PACKAGE DIMENSIONS
7.1
128L LQFP (14x14x1.4mm footprint)
Sept., 11, 2018
Page 53 of 60
Rev 1.10
N9H20
7.2 TQFP-64 (10X10X1.0mm footprint, 0.5mm pitch)
Sept., 11, 2018
Page 54 of 60
Rev 1.10
N9H20
Sept., 11, 2018
Page 55 of 60
Rev 1.10
N9H20
UNIT: mm
Sept., 11, 2018
Page 56 of 60
Rev 1.10
N9H20
7.3
PCB Reflow Profile Suggestion
Profile Setting Consideration
7.3.1
Sept., 11, 2018
Page 57 of 60
Rev 1.10
N9H20
7.3.2
Profile Suggestion for N9H20 series
Sept., 11, 2018
Page 58 of 60
Rev 1.10
N9H20
8
REVISION HISTORY
Date
Revision
Description
2018, 05, 16
2018, 09, 11
1.00
1.
2.
Preliminary version.
Added N9H20R series
1.10
Sept., 11, 2018
Page 59 of 60
Rev 1.10
N9H20
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Sept., 11, 2018
Page 60 of 60
Rev 1.10
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