NAU8315 [NUVOTON]
Pin Selectable Gain Setting;
| 型号： | NAU8315 |
| 厂家： | 
NUVOTON |
| 描述： | Pin Selectable Gain Setting |
| 文件： | 总43页 (文件大小：1051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAU8315 Datasheet
Revision 1.5
NAU8315 Datasheet Rev1.5
Page 1 of 43
Mar 30, 2020
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NAU8315 Datasheet Rev1.5
Page 2 of 43
Mar 30, 2020
1 Contents
1
CONTENTS.................................................................................................................................... 3
1.1
1.2
List of Figures.........................................................................................................................................5
List of Tables ..........................................................................................................................................5
GENERAL DESCRIPTION ............................................................................................................ 6
PIN CONFIGURATIONS................................................................................................................ 7
PIN DESCRIPTIONS ................................................................................................................... 10
SYSTEM DIAGRAM..................................................................................................................... 11
Reference System Diagram..................................................................................................................11
BLOCK DIAGRAM ....................................................................................................................... 12
ELECTRICAL CHARACTERISTICS............................................................................................ 13
Absolute Maximum Ratings..................................................................................................................13
Operating Conditions............................................................................................................................13
Electrical Parameters............................................................................................................................13
Digital Input Parameters.......................................................................................................................15
Typical Operating Plots.........................................................................................................................16
FUNCTIONAL DESCRIPTION..................................................................................................... 20
Inputs....................................................................................................................................................20
Outputs.................................................................................................................................................21
Digital Interfaces...................................................................................................................................22
Power Supply .......................................................................................................................................22
Power-On-and-Off Reset......................................................................................................................23
Power Up & Down Sequence ...............................................................................................................23
Clocking and Sample Rates .................................................................................................................24
2
3
4
5
5.1
6
7
7.1
7.2
7.3
7.4
7.5
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.7.1
Clock Control and Detection..........................................................................................................24
Automatic Power Control and Mute...............................................................................................24
Input Clock Rates..........................................................................................................................25
Sample and Over Sampling Rates ................................................................................................26
Automatic Level Control........................................................................................................................28
ALC Operation...............................................................................................................................28
ALC Parameter Definitions............................................................................................................28
Device Protection .................................................................................................................................30
Power-up and Power-Down Control .....................................................................................................30
Bypass Capacitors................................................................................................................................30
Printed Circuit Board Layout Considerations........................................................................................30
8.7.2
8.7.3
8.7.4
8.8
8.8.1
8.8.2
8.9
8.10
8.11
8.12
8.12.1
PCB Layout Notes.........................................................................................................................31
8.13
Filters....................................................................................................................................................31
8.13.1
Class D without Filters...................................................................................................................31
NAU8315 Datasheet Rev1.5
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Mar 30, 2020
8.13.2
Class D with Filters........................................................................................................................31
9
CONTROL.................................................................................................................................... 34
Digital Audio Interface...........................................................................................................................34
9.1
9.1.1
9.1.2
9.2
I2S Audio Data ..............................................................................................................................34
PCM Time Slot Audio Data............................................................................................................34
Digital Audio Interface Timing Diagrams...............................................................................................35
I2S Audio Interface........................................................................................................................35
PCM Audio ....................................................................................................................................35
9.2.1
9.2.2
10
11
12
PACKAGE SPECIFICATION ....................................................................................................... 38
ORDERING INFORMATION........................................................................................................ 41
REVISION HISTORY................................................................................................................... 42
IMPORTANT NOTICE........................................................................................................................... 43
NAU8315 Datasheet Rev1.5
Page 4 of 43
Mar 30, 2020
1.1 List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Pin Configuration of WLCSP12 NAU8315 (TOP VIEW).......................................................................7
Pin Configuration of WLCSP9 NAU8315 (TOP VIEW).........................................................................8
Pin Configuration of QFN20 NAU8315.................................................................................................9
NAU8315 Simplified System Diagram................................................................................................11
NAU8315 Block Diagram ...................................................................................................................12
NAU8315 Power Up & Down Sequence ............................................................................................23
NAU8315 Clock Detection Circuit ......................................................................................................24
PWRUPEN startup sequence. ...........................................................................................................25
ALC Control Loop Block Diagram ......................................................................................................28
Figure 10 NAU8315 Speaker Connections without Filter...................................................................................31
Figure 11 NAU8315 Speaker Connections with Ferrite Bead Filters..................................................................32
Figure 12 NAU8315 Speaker Connections with LC Filters.................................................................................32
Figure 13 NAU8315 Speaker Connections with Low-Pass Filters......................................................................32
Figure 14 I2S Audio Data...................................................................................................................................34
Figure 15 PCM Time Slot Audio Data ................................................................................................................35
Figure 16 I2S Audio Interface.............................................................................................................................35
Figure 17 PCM Audio Interface..........................................................................................................................36
1.2 List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Pin Descriptions for the NAU8315.......................................................................................................10
GAIN Configurations for the NAU8315................................................................................................20
Audio Interface Configurations for the NAU8315.................................................................................21
Range of Input Clocks .........................................................................................................................25
BCLK/FS ratios and Over Sampling Rates..........................................................................................26
Ranges of Sampling Frequencies and BCLK Rates............................................................................26
Digital Audio Interface Timing Parameter..........................................................................................36
NAU8315 Datasheet Rev1.5
Page 5 of 43
Mar 30, 2020
2 GENERAL DESCRIPTION
The NAU8315 is a mono high efficiency filter-free Class-D audio amplifier, which is capable of driving a
4Ω load with up to 3.2W output power. This device provides Enable control and I2S audio input with low
standby current and fast start-up time.
The NAU8315 is ideal for the portable applications, as it has advanced features like 80dB PSRR, 91%
efficiency, ultra-low quiescent current and superior EMI performance. NAU8315 is available in a 12 ball
Miniature WLCSP package, a 9 ball Miniature WLCSP package and a 20-pin QFN package.
Key Features
3.2W (4Ω @ 5V, 10% THD+N)
1.76W (4Ω @ 4.2V, 1% THD+N)
1.8W (8Ω @ 5V, 10% THD+N)
1.0W (8Ω @ 4.2V, 1% THD+N)
Pin Selectable Gain Setting
Pin Selectable I2S Left or Right Channel
selection
Pin Selectable PCM time slot
Low Output Noise: 12 µVRMS
80dB PSRR @217Hz
Low Current Shutdown and Standby Modes
Click-and Pop Suppression: 26 µVRMS
Sampling rate from 8K to 96 KHz
Package: 9 or 12 ball WLCSP & 20-pin QFN
Powerful Mono Class-D Amplifier:
Applications
Gaming Controllers
Wireless (VR) Headset
Smart Remote Controller
Notebooks / Tablet PCs
Personal Media Players
Ultrasonic speakers
NAU8315 Datasheet Rev1.5
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Mar 30, 2020
3 PIN CONFIGURATIONS
The NAU8315 12 Ball WLCSP package is shown in Figure 1.
TOP VIEW
3
1
2
VSS
OUTN
OUTP
A
B
C
VDD
GAIN
FSL
EN
FSR
VDD
VDD
BCLK
DACIN
D
Package
Material
Part Number
Dimension
Package
12-bump
WLCSP
1.18mm x
1.95mm
NAU8315B31VG
Green
(0.4 mm pitch)
Figure 1
Pin Configuration of WLCSP12 NAU8315 (TOP VIEW)
NAU8315 Datasheet Rev1.5
Page 7 of 43
Mar 30, 2020
The NAU8315 9 Ball WLCSP package is shown in Figure 1.
TOP VIEW
3
1
2
VSS
OUTN
OUTP
A
B
C
FSL
FSR
VDD
NC
BCLK
DACIN
Package
Material
Part Number
Dimension
Package
9-bump
WLCSP
1.18mm x
1.95mm
NAU8315A31VG
Green
(0.4 mm pitch)
Figure 2
Pin Configuration of WLCSP9 NAU8315 (TOP VIEW)
NAU8315 Datasheet Rev1.5
Page 8 of 43
Mar 30, 2020
The NAU8315 20-pin QFN package is shown in Figure 1.
QFN exposed thermal pad must be connected to VSS
Package
Material
Part Number
Dimension
Package
QFN-20
NAU8315YG
4mm x 4mm
Green
Figure 3
Pin Configuration of QFN20 NAU8315
NAU8315 Datasheet Rev1.5
Page 9 of 43
Mar 30, 2020
4 PIN DESCRIPTIONS
Pin descriptions for the NAU8315 are provided in Table 1.
Table 1
Pin Descriptions for the NAU8315
12 Ball
9 Ball**
20-pin
Name
Type
Description
WLCSP#
WLCSP#
QFN* #
D1
C1
B1
A1
B2
C2
D2
A2
C1
B1
NA
A1
B2
NA
NA
A2
9
DACIN
FSL
Digital Input
Digital Input
Analog IO
Analog Output
Supply
I2S I/F DAC digital audio data
I2S I/F Left Channel Frame clock
Gain Selection
8
13
16
2
GAIN
OUTN
VDD
Speaker negative output
Power Supply
11
14
VDD
Supply
Power Supply
VDD
Supply
Power Supply
4,12,17,
18,19
VSS
Supply
Ground
D3
C3
B3
A3
C3
B3
NA
A3
6
7
BCLK
FSR
Digital Input
Digital Input
Digital Input
Analog Output
I2S I/F bit clock
I2S I/F Right Channel Frame clock
Device Enable Input
3
EN
20
OUTP
Speaker positive output
**Note: For WLCSP9 the NC ball C2 can be tied to VDD for convenient PCB layout.
*Note: For 20 pin QFN the NC pins can be tied to VSS for convenient PCB layout.
NAU8315 Datasheet Rev1.5
Page 10 of 43
Mar 30, 2020
5 SYSTEM DIAGRAM
5.1 Reference System Diagram
A basic system reference diagram for stereo I2S is provided in Figure 4.
Figure 4
NAU8315 Simplified System Diagram
NAU8315 Datasheet Rev1.5
Page 11 of 43
Mar 30, 2020
6 BLOCK DIAGRAM
A Block Diagram for the NAU8315 is provided in Figure 5.
Talarm
UVLO
Bandgap
EN
Shutdown
Control
VDD
FSL
Digital Core Supply
FSR
BCLK
Clock
Detection
Clock
Doubler
GAIN
VDD
ADC
Clip
Soft-
unmute
& Gain
DACIN
Slew
Rate
Control
Interpolation
Filter
Class-D
Modulator
OUTP
DAC
Short
Circuit
Protection
VSS
VDD
pseudo
random
Slew
Rate
Ramp
OUTN
VSS
Control
Analog
Short
Circuit
Protection
Digital
Figure 5
NAU8315 Block Diagram
NAU8315 Datasheet Rev1.5
Page 12 of 43
Mar 30, 2020
7 Electrical Characteristics
The tables in this chapter provide the various electrical parameters for the NAU8315 and their values.
7.1
Absolute Maximum Ratings
Parameter
Min
Max
Units
VDD Battery Supply Range
Voltage Input I/O Range
Junction Temperature, TJ
Storage Temperature
-0.3
VSS - 0.3
-40
6.0
VDD + 0.3
+150
V
V
°C
°C
-65
+150
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure
to such conditions may adversely influence product reliability and result in failures not
covered by the warranty.
7.2 Operating Conditions
Recommended Operating Conditions
Condition
Symbol
Min
Typical
Max
Units
Battery Supply Range
Digital IO Range
VDD
2.50
1.8
4.2
5.25
VDD
V
Ground
VSS
0
V
Industrial Operating Temperature
-40
+85
°C
7.3 Electrical Parameters
Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, gain=12dB, unless
otherwise specified. Limits apply for TA = 25°C
Symbol
Parameter
Conditions
Typical
Limit
Units
ISD
ISB
IDD
Shutdown Supply Current
VDD, all clocks off
0.3
0.3
4.0
16
µA
µA
Standby Mode Supply Current
Operating Mode Supply Current
VDD, clocks off, EN=VDD
VDD, idle Channel
Class-D Channel
mA
VDD=4.2V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 1%, Gain=12dB, QFN-20
0.98
1.0
W
W
PO
Output Power
VDD=4.2V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 1%, Gain=12dB, WLCSP-
12
NAU8315 Datasheet Rev1.5
Page 13 of 43
Mar 30, 2020
Symbol
Parameter
Conditions
Typical
Limit
Units
VDD=5V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 10%, Gain=12dB, QFN-20
1.73
W
VDD=5V RL = 8 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 10%, Gain=12dB, WLCSP-
12
1.8
1.69
1.76
3.03
3.2
W
W
W
W
W
VDD=4.2V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 1%, Gain=12dB, QFN-20
VDD=4.2V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 1%, Gain=12dB, WLCSP-
12
VDD=5V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 10%, Gain=12dB, QFN-20
VDD=5V RL = 4 Ohm + 33 µH and
Total Harmonic Distortion+Noise
(THD+N) = 10%, Gain=12dB, WLCSP-
12
Total Harmonic Distortion +
Noise
RL = 8 Ω + 33 µH, f=1kHz, PO = 0.15
W, Gain=12dB
THD+N
eOS
0.017
11.8
85
%
µVrms
dB
A-Weighted, 20Hz-20kHz, no DAC
input signal
Output Noise
DC, VDD = 3.2V – 4.2V, amplifier
voltage GAIN = 6dB
Power Supply Rejection Ratio
(Note 1)
fRIPPLE = 1020Hz, VRIPPLE = 100mVP_P
amplifier voltage GAIN = 6dB
PSRR
82
60
dB
fRIPPLE = 4kHz, VRIPPLE = 100mVP_P
amplifier voltage GAIN = 6dB
77
dB
+0.06/
-0.06
F = 20Hz ~ 20KHz, 1Watt, RL = 8 Ω +
33 µH
Fres
VOS
Frequency Response
Output Offset Voltage
dB
Idle Channel, Gain= 6dB
±1
±5
mV
A-weighted, Idle DAC input, toggling
clocks on/off, Gain= 6dB
0.026
mVrms
Kpop
Fsw
Neff
Pop and Click Noise
Switching Frequency
Power Efficiency
A-weighted, Idle DAC input, toggling
EN pin with clocks running, Gain= 6dB
0.019
300
mVrms
kHz
Average
400
Class-D
Output Power = 1.48W, VDD = 4.2 V
91
%
NAU8315 Datasheet Rev1.5
Page 14 of 43
Mar 30, 2020
Note 1 : PSRR = 20 x LOG10(GAIN x ∆VDD/∆(SPKP-SPKN)) dB
7.4 Digital Input Parameters
Digital Inputs FS, BCLK, DACIN & EN.
Parameter
Input LOW level
Symbol
VIL
Comments/Conditions
VDD = 2.5V – 5.25V
VDD = 2.5V – 5.25V
VDD = 2.5V – 5.25V
Min
Max
Units
V
0.4
Input HIGH level
VIH
1.4*
V
Input Leakage Current
IIL
-0.001
+0.001
mA
Note: I2S signals can be 1.8V
NAU8315 Datasheet Rev1.5
Page 15 of 43
Mar 30, 2020
7.5 Typical Operating Plots
Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.
Normalised Frequency Response
Normalised Frequency Response Sample
Rate=96kHz
1
0.5
0
1
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
3.7V
4.2V
5V
3.7V
4.2V
5V
-2.5
-3
-2.5
-3
10
100
1000
10000
100000
10
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
THDN vs Frequency Vdd=5.0V Rl=8 Ohms
THDN vs Frequency Vdd=5.0V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100mW
500mW
100mW
500mW
10
100
1000
10000
100000
10
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
THDN vs Frequency Vdd=4.2V Rl=8 Ohms
THDN vs Frequency Vdd=4.2V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100mW
500mW
100mW
500mW
10
100
1000
10000
100000
10
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.
NAU8315 Datasheet Rev1.5
Page 16 of 43
Mar 30, 2020
THDN vs Frequency Vdd=3.7V Rl=8 Ohms
THDN vs Frequency Vdd=3.7V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100mW
500mW
100mW
500mW
10
100
1000
10000
100000
10
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
QFN package
QFN package
THDN vs Output Power Vdd=5.0V Rl=8 Ohms
THDN vs Output Power Vdd=5.0V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100Hz
100Hz
1kHz
6kHz
1kHz
6kHz
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Power (W)
Output Power (W)
QFN package
QFN package
THDN vs Output Power Vdd=4.2V Rl=8 Ohms
THDN vs Output Power Vdd=4.2V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100Hz
100Hz
1kHz
6kHz
1kHz
6kHz
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Power (W)
Output Power (W)
Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.
NAU8315 Datasheet Rev1.5
Page 17 of 43
Mar 30, 2020
QFN package
QFN package
THDN vs Output Power Vdd=3.7V Rl=8 Ohms
THDN vs Output Power Vdd=3.7V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100Hz
1kHz
6kHz
100Hz
1kHz
6kHz
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Power (W)
Output Power (W)
QFN package
QFN package
Efficiency vs Output Power Rl=8 Ohms
Efficiency vs Output Power Rl=4 Ohms
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
3V7
4V2
5V0
3V7
4V2
5V0
0
0.5
1
1.5
2
0
1
2
3
4
Output Power (W)
Output Power (W)
WLCSP package
WLCSP package
THDN vs Output Power 5.0V 8 Ohms
THDN vs Output Power 5.0V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100Hz
1kHz
6kHz
100Hz
1kHz
6kHz
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Power (W)
Output Power (W)
Conditions: VDD= 4.2V. RL = 8 Ω + 33 µH, f = 1kHz, 48kHz sample rate, BCLK=12.288MHz, TA = 25°C,
gain=12dB, unless otherwise specified.
NAU8315 Datasheet Rev1.5
Page 18 of 43
Mar 30, 2020
WLCSP package
WLCSP package
THDN vs Output Power 4.2V Rl=8 Ohms
THDN vs Output Power 4.2V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100Hz
1kHz
6kHz
100Hz
1kHz
6kHz
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Power (W)
Output Power (W)
WLCSP package
WLCSP package
THDN vs Output Power 3.7V Rl=8 Ohms
THDN vs Output Power 3.7V Rl=4 Ohms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100Hz
1kHz
6kHz
100Hz
1kHz
6kHz
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Power (W)
Output Power (W)
WLCSP package
WLCSP package
Efficiency vs Output Power Rl=8 Ohms
Efficiency vs Output Power Rl=4 Ohms
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
3V7
4V2
5V0
3V7
4V2
5V0
0
0.5
1
1.5
2
0
1
2
3
4
Output Power (W)
Output Power (W)
NAU8315 Datasheet Rev1.5
Page 19 of 43
Mar 30, 2020
8 FUNCTIONAL DESCRIPTION
This chapter provides detailed descriptions of the major functions of the NAU8315 Amplifier.
8.1 Inputs
The NAU8315 provides digital inputs to acquire and process audio signals with high fidelity and flexibility.
The audio input path is from an I2S/PCM Interface, using the FSL, FSR, BCLK & DACIN pins.
The device is enabled by setting the EN pin high and disabled by setting EN to 0V. The EN, FSL, FSR,
BCLK & DACIN pins all have a low input threshold voltage to allow for operation from a host with low IO
supply voltage.
The GAIN input pin is a special input pin which essentially is an ADC input. The ADC tied to this pin has
5 decision levels and can therefore select 5 modes of operation each.
The GAIN input pin can be configured as shown in the table below. The GAIN set represents the signal
voltage gain of the differential DAC outputs to the differential modulator outputs or speaker outputs. The
differential DAC full scale reference is 1.8Vpk. Note that on the 9-Ball WLCSP package the gain is set
to 12dB fixed.
Table 2
GAIN Configurations for the NAU8315
-6dBFs
GAIN (dB)
MODE
Gain Mode #
Output
(Vpk)
GAIN Pin Configuration
1
2
3
4
9
3
2.535
1.265
3.595
3.595
GAIN pin tied to VSS
GAIN pin tied to VSS through 100 kOhm +/- 5% resistor
GAIN pin tied to VDD
12
Max. 12
GAIN pin tied to VDD through 100 kOhm +/- 5% resistor
CLIP ALC
(no clipping)
1.795
5
6
GAIN pin floating
The GAIN input ADC converts the input levels set by the external pin configuration and internal voltage
dividers into a digital representation that sets the internal GAIN mode. There are a total of 5 modes
having different gains as shown above. Gain mode 4 also enables the CLIP detection ALC, which then
allows the gain to be reduced automatically as the supply voltage decreases.
The FSR & FSL input pins are used to set the I2S and PCM interface modes. The table below shows
the modes supported.
NAU8315 Datasheet Rev1.5
Page 20 of 43
Mar 30, 2020
Table 3
Interface
Audio Interface Configurations for the NAU8315
FSL Pin Configuration
Interface
Mode #
FSR Pin Configuration
MODE
1
2
Power Down or Standby
tied to VDD or VSS
tied to VDD or VSS
tied to VDD or VSS
Left Channel I2S
Right Channel I2S
I2S (L+R)/2
Toggling with valid BCLK/FSL ratio
and FSL is high for more than 2 BCLK
rising edges
3
4
tied to VDD or VSS
Toggling with valid BCLK/FSR ratio
and FSL is high for more than 2 BCLK
rising edges
Toggling with valid BCLK/FSL ratio
Toggling with valid BCLK/FSR ratio
and FSL is high for more than 2 BCLK and FSL is high for more than 2 BCLK
rising edges. FSL & FSR signals are
the same.
rising edges. FSL & FSR signals are
the same.
5
6
7
8
9
16 bit PCM Timeslot 0
16 bit PCM Timeslot 1
16 bit PCM Timeslot 2
16 bit PCM Timeslot 3
Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges
tied to VSS
tied to VSS
Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges
Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges
tied to VDD
tied to VDD
Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges
16 bit PCM
(Timeslot0+Timeslot1)/2
Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges. FSL & FSR signals are
the same.
Toggling with valid BCLK/FSL ratio
and FSL is high for less than 2 BCLK
rising edges. FSL & FSR signals are
the same.
I2S data is 24-bit by default. For the PCM Timeslot interface modes the host can also sent 24 bit or 32
bit data. However, only the 16 MSB bits will be used to process the audio in this mode.
Internal mask options can be used to select other timeslots or 24-bit data or 32-bit PCM data upon
special request.
8.2 Outputs
The NAU8315 Mono Class-D PWM Amplifier has a gain range from 3dB to 12dB, and is powered by a
separate power supply VDD, which can go up to 5V. This amplifier is capable of delivering up to 3.2W
into a 4Ω load with a 5V supply.
NAU8315 Datasheet Rev1.5
Page 21 of 43
Mar 30, 2020
8.3 Digital Interfaces
Audio data is passed to the device through a serial data interface compatible with industry standard I2S
and PCM devices, using the FSL, FSR, BCLK & DACIN pins. The NAU8315 has no serial interface for
control input. Operating modes are defined by the external pin configurations.
8.4 Power Supply
This NAU8315 has been designed to operate reliably under a wide range of power supply conditions
and Power-On/Power-Off sequences. However, the Electro Static Detection (ESD) protection diodes
between the supplies and the IO pins impact the application of the supplies.
NAU8315 Datasheet Rev1.5
Page 22 of 43
Mar 30, 2020
8.5 Power-On-and-Off Reset
The NAU8315 includes a Power-On-and-Off Reset circuit on-chip. The circuit resets the internal logic
control at VDD supply power-up and this reset function is automatically generated internally when power
supply is too low for reliable operation. Typical reset thresholds are 1.88 V for VDD during a power-on
ramp, and 1.61 V for VDD during a power-down ramp. It should be noted that these values are much
lower than the required voltage for normal operation of the chip.
The reset is held ON while the power level for VDD is below the threshold. Once the power level rises
above the threshold, the reset is released. Once the reset is released, the device will respond to control
from external inputs.
An additional internal RC filter-based circuit is added which helps the circuit to respond for fast ramp
rates (~3 µsec) and to generate the desired reset period width (~3 µsec at typical corner). This filter is
also used to eliminate supply glitches which can generate a false reset condition, typically 50 nsec.
In addition setting the enable pin ‘EN’ low will reset the internal logic.
8.6 Power Up & Down Sequence
A diagram of the typical power up sequence is shown in the figure below. At first, the power supply is
ramped up.
VDD
EN
FS,BCLK,DACIN
2048 DACIN zeros
recommended
MUTE
ENABLED
OFF
OUTP,OUTN
status
Soft
UnMUTE
OFF
Figure 6
NAU8315 Power Up & Down Sequence
Once the supply is powered up, the enable pin ‘EN’ can be set high in order to set the device in
standby state. Note that the ‘EN’ pin can also ramp up the same time as the supply voltage. During the
standby state the outputs OUTN & OUTP are still off. After enabling VDD & EN ,the BCLK detection
circuit is activated. External clocks and data can be applied right away if needed. Once the FS & BCLK
are applied the clock detection module will validate the BCLK/FS ratio and set the internal clock
dividers. When a valid BCLK/FS ratio is detected and the clock dividers are set, a 4 millisecond mute
period is enabled during which all circuits are powered up and the DAC digital volume control is in the
muted state. The mute period is followed by a soft-unmute, which gradually increases the DAC digital
volume to full scale. After this event the signal path is fully active and the outputs are fully enabled. At
the end of playback it is recommended to add 2048 zero samples to the DACIN input for a pop-less
shutdown. When either one or both of the FS & BCLK clocks is stopped the clock detection circuit will
power down the device. The detection time depends on the clock frequency used, but is approximately
50usec. Once detected, the output drivers will shut down.
NAU8315 Datasheet Rev1.5
Page 23 of 43
Mar 30, 2020
8.7 Clocking and Sample Rates
The internal clocks for the NAU8315 are derived from the external BCLK clock source. This master
system clock can set directly by the BCLK input or it can be generated from a clock multiplier using the
BCLK as a reference.
8.7.1 Clock Control and Detection
The NAU8315 includes a Clock Detection circuit that is used to enable and disable the audio paths. The
actual power up/down is gated by the clock detection circuit. The block diagram of the clock detection
circuit is shown in Figure 7.
BCLK
BCLKDET
DETECTION
1/N1
50 %
DUTYCYCLE
x N2
Clock
Multiplier
1,2,4,8x
Delay
MCLKSEL
Multiplexer
MCLK_SRC
PWRUPEN
FSL
FSR
BCLK
BCLK/FS
Detection
I2SPCM
Mode
Detection
CHANNEL
CLOCK
DETECTION
EN
Figure 7
NAU8315 Clock Detection Circuit
Clock Detection by the NAU8315 uses the BCLK FSL, FSR and EN to control the internal PWRUPEN
signal and set the clock divider ratios.
8.7.2 Automatic Power Control and Mute.
Clock detection and automatic power control in the NAU8315 is enabled by meeting two conditions,
depending on the configuration. If all conditions are met, the PWRUPEN signal will be asserted to 1. If
any of the conditions are not met, the PWRUPEN signal is set to 0.
The conditions for generating the PWRUPEN signal are:
NAU8315 Datasheet Rev1.5
Page 24 of 43
Mar 30, 2020
1) The NAU8315 has custom logic clock detection circuits that detect if BCLK is present. Upon
BCLK detection, the detector output BCLKDET goes to 1. When the BCLK disappears,
BCLKDET goes back to 0. Up to 1 µsec is required to detect BCLK and the BCLK release time
is about 50 µsec.
2) The clock detection logic also needs to detect the ratio BCLK /FS of 32, 50, 64, 100, 125, 128,
200, 250, 256, 400, 500.
The PWRUPEN signal is capable of controlling all the analog power consuming blocks.
A Mode Detection circuit also determines one of the I2S/PCM operating mode and channel (as shown
in Table 3) once a valid BCLK/FS ratio is detected.
When PWRUPEN goes high an internal sequence is triggered to bring up analog functions. This includes
an analog MUTE to allow stabilization of internal analog blocks, followed by a soft unmute of the DAC.
The analog MUTE time is 4ms. The soft unmute then ramps the gain 512 MCLK_SRC periods per gain
step. For the 512 setting, the soft unmute takes 256 * 512 * Tmclk_src seconds to reach 0dB (10ms for
12.288MHz MCLK_SRC). This ensures pop free startup of the amplifier. An example of this startup is
shown in figure below.
Figure 8
PWRUPEN startup sequence.
Before reaching the DAC the incoming PCM signal is processed by a digital signal path. To ensure
complete flushing and transient free audio of this path it is recommended that 2048 zero samples are
sent to the device before stopping clocks. The DAC soft unmute function is also beneficial for eliminating
any audio transients from audio path
8.7.3 Input Clock Rates
The range of the input clocks is shown in Table 4.
Table 4
Range of Input Clocks
NAU8315 Datasheet Rev1.5
Page 25 of 43
Mar 30, 2020
Signal
Min
8
Max
96
Frame Synch (FS) (kHz)
Bit Clock BCLK (MHz)
1.4112
24.576
8.7.4 Sample and Over Sampling Rates
Possible BCLK/FS ratios are shown in Table 5 and Table 6. Table 4 shows the relation between the
BCLK/FS ratio and the internal OSR and MCLK_SRC/FS ratio. The divider and multiplier N1 & N2 are
set accordingly by the clock detection logic. Table 5 shows the possible FS & BCLK ranges for each
BCLK/FS ratio.
Table 5
BCLK/FS ratios and Over Sampling Rates
Lower
BCLK/FS Decision
Upper
Decision
N1
N2
MCLK_SRC/FS
OSR
ratio
Threshold Threshold
32
50
64
31
49
63
33
51
65
1
1
2
2
2
2
2
2
1
1
1
8
8
8
8
8
4
4
4
1
1
1
256
400
256
400
500
256
400
500
256
400
500
64
100
64
100
100
64
100
100
64
100
100
100
125
128
200
250
256
400
500
99
101
126
129
201
251
257
401
501
124
127
199
249
255
399
499
Table 6
Ranges of Sampling Frequencies and BCLK Rates
BCLK/FS
Ratio
FS (kHz)
Min Max
BCLK (MHz)
Min Max
NAU8315 Datasheet Rev1.5
Page 26 of 43
Mar 30, 2020
32
44.1
32
44.1
32
24
24
16
12
8
96
48
96
48
48
96
48
48
96
48
48
1.4112
1.600
2.8224
3.200
3.000
3.072
3.200
3.000
2.048
3.200
4.000
3.072
2.400
50
64
6.144
100
125
128
200
250
256
400
500
4.800
6.000
12.288
9.600
12.000
24.576
19.200
24.000
8
8
The MCLK_SRC frequency is defined as:
F_MCLK_SRC = N2 x F_BCLK / N1
For BCLK/FS ratios of 32 & 50 a low jitter BCLK source with accurate duty cycle must be used.
NAU8315 Datasheet Rev1.5
Page 27 of 43
Mar 30, 2020
8.8 Automatic Level Control
The digital Automatic Level Control (ALC) function supports the DAC digital audio path of the NAU8315.
It can be enabled as by setting the GAIN pin to 12dB gain with ALC. This function can be used to manage
the gain to optimize the signal level at the output of the Class-D Amplifier by automatically amplifying
input signals that are too small or automatically decreasing the amplitude signals that are too loud. The
ALC is designed such that it adjusts the output level in order to prevent clipping. This may be use-full in
battery operated applications, where the battery supply voltage decreases as the battery discharges. At
lower supply voltages the outputs will more likely clip at higher output levels. In such case, the ALC
would decrease the output level just below the clipping level and maintain high quality sound as well as
decreasing the peak power drain from the battery.
The Figure below illustrates the relationship of the ALC to other major functions of the NAU8315.
Digital
Programmable Gain
VDDSPK
Amplifier
Class-D
Modulator
From
DACIN
DAC
NuvoClip
Detection
ALC
Control
CLIP
AND
ALCEN
Figure 9
ALC Control Loop Block Diagram
8.8.1 ALC Operation
A clip detection signal is provided by the clip detection circuit as soon as the input signal is clipping at
its peak levels. The ALC block then ramps down the gain at the pre-programmed ALC Attack Time
rate. This continues until the clipping detection no longer detects a clipping signal or until the
maximum gain decrement per clipping event is reached. When the clipping is no longer occurring, the
ALC gain is held for the hold time. The ALC gain is then ramped up to the target following the pre-
programmed ALC Release Time rate
8.8.2 ALC Parameter Definitions
ALC Minimum Gain (ALCMIN): This sets the minimum allowed gain during all modes of ALC
operation. This is useful to keep the ALC operating range close to the desired range for a given
application scenario.
ALC Attack Time (ALCATK): Attack time refers to how quickly a system responds to a clipping event.
Typically, attack time is much faster than decay time.
NAU8315 Datasheet Rev1.5
Page 28 of 43
Mar 30, 2020
ALC Decay Time (ALCDCY): Decay time refers to how quickly a system responds after the hold time.
Typically, decay time is much slower than attack time. When no more clipping events occur, the
gain will increase at a rate determined by this parameter.
ALC Hold Time (ALCHLD): Hold time refers to the duration of time when no action is taken. This is
typically to avoid undesirable sounds that can happen when an ALC responds too quickly to a
changing input signal. In the NAU8315, the hold time value is the duration from the last clipping
event before there is an actual gain increase during the decay time.
CLIP_GAINADJUST sets the maximum gain decrease per clipping event. During a clipping even the
gain decreases by 0.250dB (1-1/64) per attack time step until the clipping event no longer occurs
or the maximum gain reduction limit set in CLIP_GAINADJUST has been reached or the ALC
Minimum Gain is reached.
NAU8315 Datasheet Rev1.5
Page 29 of 43
Mar 30, 2020
8.9
Device Protection
The NAU8315 includes the following types of device protection:
Over Current Protection (OCP)
Under Voltage Lock Out (UVLO)
Over Temperature Protection (OTP)
Clock Termination Protection (CTP)
Over Current Protection is provided in the NAU8315. If a short circuit is detected on any of the pull-up
or pull-down devices on the output drivers for at least 14µs, the output drivers will be disabled for 100ms.
The output drivers will then be re-enabled and checked for a short circuit again. If the short circuit is
still present for another 14µs, the cycle will repeat until the short circuit has been fixed. The short circuit
threshold is set at 2.1A.
Under Voltage Lock Out (UVLO) provides Supply Under Voltage Protection in the NAU8315 If the
VDD drops under 2.1V, the output drivers are disabled, however, the NAU8315 control circuitry will still
operate. This is useful to help avoid the battery supply voltage dropping before the host processor can
safely shutdown the devices on the system. If the VDD drops below 1.61V, the internal power-on-
reset will activate and put the class-D driver in power down state.
Over Temperature Protection (OTP) is provided in the event of thermal overload. When the device
internal junction temperature reaches 143°C, the NAU8315 will disable the output drivers. Once the
device cools down to a safe operating temperature (123°C) for at least 100us, the output drivers will
be re-enabled.
Clock Termination Protection (CTP) is provided in the NAU8315. If the FS and/or BCLK clock stops
running, the NAU8315 automatically shuts down the Class-D driver and therefore prevents DC voltages
to remain at the outputs.
8.10 Power-up and Power-Down Control
When the supply voltage ramps up, the internal power on reset circuit is triggered. At this time, all internal
circuits will be set to the power-down state. The device can be enabled by setting EN to VDD and starting
the clocks. Upon starting the clocks, the device will go through an internal power-up sequence in order
to minimize ‘pops’ on the speaker output. The complete power-up sequence requires about 14 msec.
The device will typically power down in about 22 µsec, when the clocks are stopped.
NOTE: It is important to keep the input signal at zero amplitude or enable the mute condition in order
to minimize ‘pops’ when the clocks are stopped.
8.11 Bypass Capacitors
Bypass capacitors are required to remove the AC ripple on the VDD pins. The value of these
capacitors depends on the length of the VDD trace. In most cases, 2 x 4.7 µF and 0.1 µF are sufficient
to achieve good performance.
8.12 Printed Circuit Board Layout Considerations
Good Printed Circuit Board (PCB) layout and grounding techniques are essential to achieve good audio
performance. It is better to use low-resistance traces as these devices are driving low impedance loads.
The resistance of the traces has a significant effect on the output power delivered to the load. In order
to dissipate more heat, use wide traces for the power and ground lines.
NAU8315 Datasheet Rev1.5
Page 30 of 43
Mar 30, 2020
8.12.1 PCB Layout Notes
The Class-D Amplifier is a high power switching circuits that can cause Electro Magnetic Interference
(EMI) when poorly connected. Therefore, care must be taken to design the PCB eliminate Electro
Magnetic Interference (EMI), reduce IR drops, and maximize heat dissipation.
The following notes are provided to assist product design and enhance product performance:
Use a VSS plane, preferably on both sides, to shield clocks and reduce EMI
Maximize the copper to the VSS pins and have solid connections to the plane
Planes on VDD are optional
The VDD connection needs to be a solid piece of copper
Use thick copper options on the supply layers if cost permits
Keep the speaker connections short and thick. Do not use VIAs
Use a small speaker connector like a wire terminal block (Phoenix Contact)
For better heat dissipation, use VIAs to conduct heat to the other side of the PCB
Do not use VIA’s to connect OUTP & OUTN. Use a direct top layer copper connection to the pins.
Thick copper is preferred.
Use large or multiple parallel VIAs to decoupling capacitors when connecting to a ground plane
The digital IO lines can be shielded between power planes
8.13 Filters
The NAU8315 is designed for use without any filter on the output line. However, the NAU8315 may be
used with or without various types of filters, depending on the needs of the application.
8.13.1 Class D without Filters
The NAU8315 is designed for use without any filter on the output line. That means the outputs can be
directly connected to the speaker in the simplest configuration. This type of filter-less design is suitable
for portable applications where the speaker is very close to the amplifier. In other words, this is preferable
in applications where the length of the traces between the speaker and amplifier is short. Figure 10
illustrates this simple configuration.
SPKP
SPKN
Figure 10
NAU8315 Speaker Connections without Filter
8.13.2 Class D with Filters
In some applications, shorter trace lengths are not possible because of speaker size limitations and
other layout reasons. In these applications, long traces will cause EMI issues. Several types of filter
circuits are available to reduce the EMI effects. These are Ferrite Bead Filters, LC filters, Low-Pass LCR
Filters, and High-Pass Filters.
Ferrite Bead Filters are used to reduce high-frequency emissions. The characteristic of a Ferrite Bead
Filter is such that it offers higher impedance at high frequencies. For better EMI performance, select a
Ferrite Bead Filter which offers the highest impedance at high frequencies, so that it will attenuate the
signals at higher frequencies. The typical circuit diagram using a Ferrite Bead Filter for each output to
the speaker is shown Figure 11.
NAU8315 Datasheet Rev1.5
Page 31 of 43
Mar 30, 2020
NOTE: Usually, the ferrite beads have low impedance in the audio range, so they will act as pass-
through filters in the audio frequency range.
Ferrite Bead
VOUTP
1nF
Ferrite Bead
VOUTN
1 nF
Figure 11
NAU8315 Speaker Connections with Ferrite Bead Filters
LC Filters are used to suppress low-frequency emissions. The diagram in Figure 12 shows the
NAU8315 outputs connected to the speaker with an LC Filter circuit. RL is the resistance of the speaker
coil.
VOUTP
VOUTN
L
RL
C
L
C
Figure 12
NAU8315 Speaker Connections with LC Filters
Low-Pass LCR Filters may also be useful in some applications where long traces or wires to the
speakers are used. Figure 13 shows the speaker connections using standard Low-Pass LCR Filters.
L
Output
Input
R
C
Figure 13
NAU8315 Speaker Connections with Low-Pass Filters
The following equations apply for critically damped (ζ = 0.707) standard Low-Pass LCR Filters:
NAU8315 Datasheet Rev1.5
Page 32 of 43
Mar 30, 2020
1
2ꢀꢁꢂ
=
ꢁꢂ is the cut-off frequency
(
)
√ ꢃꢄ
1
ꢇ
ꢅ = 0.707 =
∗ √
2ꢆ
ꢈ
NOTE: The L and C values for differential configuration can be calculated by duplicating the single-
ended configuration values and substituting RL = 2R.
NAU8315 Datasheet Rev1.5
Page 33 of 43
Mar 30, 2020
9 Control
The NAU8315 Audio Interface is set to default I2S and PCM time slot modes as described in the
FSL & FSR operating mode table. Other modes may be feasible through metal mask option changes
upon special request.
9.1 Digital Audio Interface
The NAU8315 is an I2S or PCM Timeslot slave device. In I2S Slave Mode, an external controller
supplies BCLK (bit clock) and the frame synchronization or FS signal. Data is latched on the rising edge
of BCLK.
The NAU8315 reads 24 bit I2S data on DACIN. For the BCLK/FS rate of 32, only the 16 MSB bits are
read.
9.1.1 I2S Audio Data
In I2S Mode, the MSB is clocked on the second BCLK rising edge after the FS transitions. When FS is
LOW, Left Channel data is received; when FS is HIGH, Right Channel data is received. This can be
seen in Figure 14.
FS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
1
DATA
N-1
0
N-1
1
0
MSB
LSB
MSB
LSB
Figure 14
I2S Audio Data
9.1.2 PCM Time Slot Audio Data
PCM Time Slot Mode is used to delay the time at which the DAC data is clocked into the device. This
can be useful when multiple NAU8315 chips or other devices share the same audio bus. This will allow
the audio from the chips to be delayed around each other without interference.
Normally, the DAC data is clocked immediately after the Frame Sync (FS); however, in PCM Time Slot
Mode, the audio data can be delayed. These delays can be seen before the MSB in Figure 15.
NAU8315 Datasheet Rev1.5
Page 34 of 43
Mar 30, 2020
CHANNEL 2 … 7
FS
CHANNEL 0
CHANNEL 1
BCLK
DATA
N-1 N-2
MSB
0
N-1 N-2
MSB
1
0
1
N-1 N-2
MSB
1
0
LSB
LSB
LSB
Figure 15
PCM Time Slot Audio Data
9.2 Digital Audio Interface Timing Diagrams
9.2.1 I2S Audio Interface
TBCK
TRISE
TFALL
BCLK
(Slave)
TFSH
TBCKH
TFSH
TBCKL
TFSS
TFSS
FS
(Slave)
TDIS
TDIH
DACIN
TDOD
ADCOUT
Figure 16
I2S Audio Interface
9.2.2 PCM Audio
NAU8315 Datasheet Rev1.5
Page 35 of 43
Mar 30, 2020
Figure 17
PCM Audio Interface
Table 7
Digital Audio Interface Timing Parameter
BCLK=3.072MHz, Fs=48KHz, 64Bit, VDD 2.5 -5.25V, Room Temperature
Description
Symbol
Min
35
Typ
---
Max
Unit
ns
BCLK Cycle Time (Slave Mode)
TBCK
---
---
---
---
---
BCLK High Pulse Width (Slave Mode)
BCLK Low Pulse Width (Slave Mode)
TBCKH
TBCKL
20
50
20
40
---
---
15
15
---
---
---
---
---
---
---
---
---
---
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fs to CLK Rising Edge Setup Time (Slave Mode) TFSS
BCLK Rising Edge to Fs Hold Time (Slave Mode) TFSH
Rise Time for All Audio Interface Signals
Fall Time for All Audio Interface Signals
ADCIN to BCLK Rising Edge Setup Time
BCLK Rising Edge to DACIN Hold Time
Delay Time from SCLK Falling Edge to ADCOUT
TRISE
TFALL
TDIS
TBD
TBD
---
TDIH
---
TDOD
TBD
NAU8315 Datasheet Rev1.5
Page 36 of 43
Mar 30, 2020
NAU8315 Datasheet Rev1.5
Page 37 of 43
Mar 30, 2020
10 Package Specification
The NAU8315 Mono Class-D Amplifier is available in a small, 20 pin QFN package, using 0.5 mm
pitch, as shown below.
TOP VI EW
BOTTOM VI EW
15
11
11
15
10
10
16
16
20
20
6
6
1
5
5
1
NAU8315 20 pin QFN Package Specification
NAU8315 Datasheet Rev1.5
Page 38 of 43
Mar 30, 2020
The NAU8315 Mono Class-D Amplifier is also available in a small, 12 Ball WLCSP package, using 0.4
mm pitch, as shown below.
NAU8315 12 Ball WLCSP Package Specification
NAU8315 Datasheet Rev1.5
Page 39 of 43
Mar 30, 2020
The NAU8315 Mono Class-D Amplifier is also available in a small, 9 Ball WLCSP package, using 0.4
mm pitch, as shown below.
NAU8315 9 Ball WLCSP Package Specification
NAU8315 Datasheet Rev1.5
Page 40 of 43
Mar 30, 2020
11 Ordering Information
Part Number
Dimension
Package
Package Material
4mm x 4mm
NAU8315YG
NAU8315A31VG
NAU8315B31VG
QFN-20
Green
Green
Green
1.95mm x 1.18mm
1.95mm x 1.18mm
9 Ball WLCSP
12 Ball WLCSP
NAU8315 _ _
Package Material:
Pb-free Package
G
=
Package Type:
Y
=
20-Pin QFN Package
WLCSP-9 Package
WLCSP-12 Package
A31V =
B31V =
NAU8315 Datasheet Rev1.5
Page 41 of 43
Mar 30, 2020
12 Revision History
Version
Description
#
Date
Page(s)
1.0
Sept 23, 2019
Preliminary
Draft 1
1.1
Sept 23, 2019
Updated WLCSP 9 pinout and package drawing
Preliminary
Draft 1
1.2
Updated VIL & VIH conditions. Add WLCSP & QFN20 charts and
WLCSP parameters
Oct 25, 2019
Jan 29, 200
Preliminary
Draft 1
1.3
Preliminary
Move electrical characteristic section
1.4
Part number change
Feb 18,2020
Preliminary
P.15
Adding more information for I2S
1.5
March 30, 2020
Added Section 9.2
NAU8315 Datasheet Rev1.5
Page 42 of 43
Mar 30, 2020
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types
of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims
to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and
liabilities thus incurred by Nuvoton.
NAU8315 Datasheet Rev1.5
Page 43 of 43
Mar 30, 2020
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