NAU8812RG [NUVOTON]
Mono Audio Codec with Speaker Driver;
| 型号： | NAU8812RG |
| 厂家： | 
NUVOTON |
| 描述： | Mono Audio Codec with Speaker Driver |
| 文件： | 总110页 (文件大小：2692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAU8812
Mono Audio Codec with Speaker Driver
emPowerAudio™
1. GENERAL DESCRIPTION
The NAU8812 is a cost effective and low power wideband MONO audio CODEC. It is designed for voice
telephony related applications. Functions include Automatic Level Control (ALC) with noise gate, PGA, standard
audio interface I2S, PCM with time slot assignment, and on-chip PLL. The device provides one differential
microphone input and one single ended auxiliary input (multi purpose). There are few variable gain control stages
in the audio path. It also includes MONO line output and integrated BTL speaker driver.
The analog inputs have PGA on the front end, allowing dynamic range optimization with a wide range of input
sources. The microphone amplifiers have a programmable gain from -12dB to +35.25dB to handle both amplified
microphones. In addition to a digital high pass filter to remove DC offset voltages, the ADC also features voice
band digital filtering. Voice-band data is accepted by the audio interface (I2S). The DAC converter path includes
filtering and mixing, programmable-gain amplifiers (PGA), and soft muting. The digital interfaces, 2-Wire or SPI,
have independent supply voltage to allow integration into multiple supply systems. The NAU8812 operates at
supply voltages from 2.5V to 3.6V, although the digital core can operate at voltage as low as 1.71V to save power.
The NAU8812 is specified for operation from -40°C to +85°C. AEC-Q100 & TS16949 compliant device is
available upon request.
2. FEATURES
24-bit signal processing linear Audio CODEC
Audio DAC: 93dB SNR and -84dB THD
Audio ADC: 91dB SNR and -79dB THD
Support variable sample rates from 8 - 48kHz
Integrated BTL Speaker Driver 800mW (8Ω / 5V)
Integrated Headset Driver 40mW (16Ω / 3.3V)
Analog I/O
Integrated programmable Microphone Amplifier
Integrated Line Input and Line Output
Earphone / Speaker / Line Output selection
Microphone / Line Inputs selection
Low Noise bias supplied for microphone
On-chip PLL
Interfaces
I2S digital interface PCM time slot assignment
SPI & 2-Wire serial control Interface (I2C style; Read/Write capable)
Low Power, Low Voltage
Analog Supply: 2.5V to 3.6V
Digital Supply: 1.71V to 3.6V
Nominal Operating Voltage: 3.3V
Additional features
Programmable ALC
ADC Notch Filter
Programmable High Pass Filter
Digital A/D-D/A Passthrough
AEC-Q100 & TS16949 compliant device available upon request
Industrial temperature: range: –40C to +85C
Applications
VoIP Telephones]
Conference speaker-phone
emPowerAudio™
Datasheet Revision 2.8
Page 1 of 110
June 2016
NAU8812
IP PBX
Mobile Telephone Hands-free Kits
Residential & Consumer Intercoms
Line Driver
AUX
ADC Filter
AUX
Input
Mixers
Output
Mixers
DAC Filter
BTL
Speaker
Driver
Volume
Control
Volume
Control
Microphone
Interface
&
&
ADC
DAC
MIC-
HPF
Gain
Stage
Speaker
Volume
SPK+
SPK-
Limiter
MIC+
Notch Filter
-1
PLL
Micophone
Bias
MICBIAS
Digital Audio Interface
I2S
Serial Control Interface
2-wire SPI
GPIO
PCM
CSb/GPIO
Audio I/O
Digital I/O
emPowerAudio™
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NAU8812
PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREF
MIC -
AUX
VDDSPK
3
MIC +
MICBIAS
NC
VDDSPK
SPKOUT -
VSSSPK
VSSSPK
SPKOUT +
MOUT
4
5
6
VDDA
VSSA
VSSA
VDDC
VDDB
VSSD
ADCOUT
DACIN
FS
NAU8812
MONO AUDIO
CODEC
7
8
SSOP 28-Pin
9
MODE
10
11
12
13
14
SDIO
SCLK
CSb/GPIO
MCLK
BCLK
Figure 1: 28-Pin SSOP Package
VSSSPK
NC
VDDA
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VSSSPK
VSSA
VSSA
SPKOUT +
MOUT
NAU8812
MONO AUDIO
CODEC
NC
VDDL
VDDC
QFN 32-Pin
MODE
SO
VDDB
VSSD
SDIO
Figure 2: 32-Pin QFN Package
emPowerAudio™
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NAU8812
3. PIN DESCRIPTION
Pin Name
VREF
28-Pin
1
32-Pin
29
30
31
32
1
Functionality
Decoupling internal analog mid supply reference
Microphone Negative Input
Microphone Positive Input
Microphone Bias
A/D
A
Pin Type
O
I
MIC-
2
A
MIC+
3
A
I
MICBIAS
NC
4
A
O
5
No Connect
VDDA
VSSA
6
2
Analog Supply
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
I
O
O
O
I
7
3
Analog Ground
VSSA
8
4
Analog Ground
Logic supply voltage. This pin should not be
VDDL
-
5
VDDC
VDDB
VSSD
9
6
Digital Supply Core
10
11
-
7
Digital Supply Buffer
Digital Ground
I
8
O
O
O
I
VSSD
9
Digital Ground
ADCOUT
DACIN
FS
12
13
14
15
16
17
18
19
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Digital Audio Data Output
Digital Audio Data Input
Frame Sync
I/O
I/O
I
BCLK
Bit Clock
MCLK
CSb/GPIO
SCLK
Master Clock
SPI Chip Select or General Purposes 1 I/O
SPI or 2-Wire Serial Clock
SPI Data In or 2-Wire I/O
SPI Data Output
I/O
I
SDIO
O
O
I
SO
MODE
NC
20
-
Interface Select (2-Wire or SPI)
No Connect
MOUT
SPKOUT+
VSSSPK
VSSSPK
SPKOUT-
VDDSPK
VDDSPK
AUX
21
22
23
24
25
26
27
28
MONO Output
A
A
A
A
A
A
A
A
O
O
O
O
O
I
Speaker Positive Output
Speaker Ground
Speaker Ground
Speaker Negative Output
Speaker Supply
Speaker Supply
I
Auxiliary Input
I
Table 1: Pin Description for SSOP and QFN Packages
Notes
1. The 32-QFN package includes a bulk ground connection pad on the underside of the chip. This bulk ground
should be thermally tied to the PCB, and electrically tied to the analog ground.
2. Unused analog input pins should be left as no-connection.
3. Under all condition when digital pins are not used they should be tied to ground.
4. Pins designated as NC (Not Internally Connected) should be left as no-connection
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NAU8812
4. BLOCK DIAGRAM
VSSSPK
VSSSPK
VDDSPK
DACIN
BCLK
FS
VDDSPK
VSSA
VSSA
VSSD
VDDA
VDDB
ADCOUT
SO
SCLK
SDIO
MODE
VDDC
NC
CSb/GPIO
MCLK
Figure 3: NAU8812 General Block Diagram
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NAU8812
5. Table of Contents
1.
GENERAL DESCRIPTION..................................................................................................................................1
2.
FEATURES .........................................................................................................................................................1
PIN CONFIGURATION .......................................................................................................................................3
PIN DESCRIPTION.............................................................................................................................................4
BLOCK DIAGRAM...............................................................................................................................................5
TABLE OF CONTENTS ......................................................................................................................................6
LIST OF FIGURES............................................................................................................................................10
LIST OF TABLES..............................................................................................................................................12
ABSOLUTE MAXIMUM RATINGS ....................................................................................................................13
OPERATING CONDITIONS..............................................................................................................................13
ELECTRICAL CHARACTERISTICS..................................................................................................................14
FUNCTIONAL DESCRIPTION..........................................................................................................................17
12.1. INPUT PATH..............................................................................................................................................17
12.1.1. The Single Ended Auxiliary Input (AUX) .............................................................................................17
12.1.2. The differential microphone input (MIC- & MIC+ pins) ........................................................................19
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
12.1.2.1. Positive Microphone Input (MIC+)...............................................................................................20
12.1.2.2. Negative Microphone Input (MIC-)..............................................................................................20
12.1.2.3. PGA Gain Control.......................................................................................................................21
12.1.3. PGA Boost Stage................................................................................................................................21
12.2. MICROPHONE BIASING...........................................................................................................................23
12.3. ADC DIGITAL FILTER BLOCK ..................................................................................................................25
12.3.1. Programmable High Pass Filter (HPF)................................................................................................26
12.3.2. Programmable Notch Filter (NF) .........................................................................................................26
12.3.3. Digital ADC Gain Control.....................................................................................................................27
12.4. PROGRAMMABLE GAIN AMPLIFIER (PGA) ............................................................................................27
12.4.1. Automatic level control (ALC)..............................................................................................................27
12.4.1.1. Normal Mode ..............................................................................................................................30
12.4.1.2. ALC Hold Time (Normal mode Only) ..........................................................................................30
12.4.2. Peak Limiter Mode ..............................................................................................................................31
12.4.3. Attack Time .........................................................................................................................................32
12.4.4. Decay Times .......................................................................................................................................32
12.4.5. Noise gate (normal mode only) ...........................................................................................................32
12.4.6. Zero Crossing......................................................................................................................................33
12.5. DAC DIGITAL FILTER BLOCK ..................................................................................................................34
12.5.4. Hi-Fi DAC De-Emphasis and Gain Control..........................................................................................35
12.5.5. Digital DAC Output Peak Limiter.........................................................................................................36
12.5.6. Volume Boost......................................................................................................................................36
12.6. ANALOG OUTPUTS ..................................................................................................................................37
12.6.1. Speaker Mixer Outputs .......................................................................................................................37
12.6.2. MONO Mixer Output ...........................................................................................................................38
12.6.3. Unused Analog I/O..............................................................................................................................39
12.7. GENERAL PURPOSE I/O..........................................................................................................................40
12.7.1. Slow Timer Clock ................................................................................................................................41
12.7.2. Jack Detect .........................................................................................................................................41
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12.7.3. Thermal Shutdown..............................................................................................................................42
12.8. CLOCK GENERATION BLOCK .................................................................................................................43
12.9. CONTROL INTERFACE ............................................................................................................................47
12.9.1. SPI Serial Control................................................................................................................................47
12.9.1.1. 16-bit Write Operation (default)...................................................................................................48
12.9.1.2. 24-bit Write Operation.................................................................................................................48
12.9.1.3. 32-bit Read Operation.................................................................................................................49
12.9.2. 2-WIRE Serial Control Mode (I2C Style Interface)...............................................................................49
12.9.2.1. 2-WIRE Protocol Convention......................................................................................................50
12.9.2.2. 2-WIRE Write Operation .............................................................................................................50
12.9.2.3. 2-WIRE Read Operation.............................................................................................................51
12.10. DIGITAL AUDIO INTERFACES .................................................................................................................52
12.10.1. Right Justified audio data....................................................................................................................53
12.10.2. Left Justified audio data ......................................................................................................................54
12.10.3. I2S audio data......................................................................................................................................55
12.10.4. PCM audio data ..................................................................................................................................56
12.10.5. PCM Time Slot audio data ..................................................................................................................57
12.10.6. Companding........................................................................................................................................58
12.11. POWER SUPPLY.......................................................................................................................................59
12.11.1. Power-On Reset..................................................................................................................................59
12.11.2. Power Related Software Considerations.............................................................................................59
12.11.3. Software Reset....................................................................................................................................60
12.11.4. Power Up/Down Sequencing ..............................................................................................................60
12.11.5. Reference Impedance (REFIMP) and Analog Bias.............................................................................61
12.11.6. Power Saving......................................................................................................................................61
12.11.7. Estimated Supply Currents..................................................................................................................62
REGISTER DESCRIPTION...............................................................................................................................63
13.1. SOFTWARE RESET..................................................................................................................................65
13.2. POWER MANAGEMENT REGISTERS .....................................................................................................65
13.2.1. Power Management 1.........................................................................................................................65
13.2.2. Power Management 2.........................................................................................................................66
13.2.3. Power Management 3.........................................................................................................................66
13.3. AUDIO CONTROL REGISTERS................................................................................................................66
13.3.1. Audio Interface Control .......................................................................................................................66
13.3.2. Audio Interface Companding Control ..................................................................................................67
13.3.3. Clock Control Register ........................................................................................................................68
13.3.4. Audio Sample Rate Control Register ..................................................................................................69
13.3.5. GPIO Control Register ........................................................................................................................70
13.3.6. DAC Control Register..........................................................................................................................70
13.3.7. DAC Gain Control Register .................................................................................................................71
13.3.8. ADC Control Register..........................................................................................................................71
13.3.9. ADC Gain Control Register .................................................................................................................72
13.4. DIGITAL TO ANALOG CONVERTER (DAC) LIMITER REGISTERS ........................................................73
13.5. NOTCH FILTER REGISTERS....................................................................................................................74
13.6. AUTOMATIC LEVEL CONTROL REGISTER ............................................................................................75
13.6.1. ALC1 REGISTER................................................................................................................................75
13.6.2. ALC2 REGISTER................................................................................................................................76
13.
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13.6.3. ALC3 REGISTER................................................................................................................................77
13.7. NOISE GAIN CONTROL REGISTER.........................................................................................................78
13.8. PHASE LOCK LOOP (PLL) REGISTERS..................................................................................................79
13.8.1. PLL Control Registers.........................................................................................................................79
13.8.2. Phase Lock Loop Control (PLL) Registers ..........................................................................................79
13.9. INPUT, OUTPUT, AND MIXERS CONTROL REGISTER..........................................................................80
13.9.1. Attenuation Control Register ...............................................................................................................80
13.9.2. Input Signal Control Register ..............................................................................................................80
13.9.3. PGA Gain Control Register .................................................................................................................81
13.9.4. ADC Boost Control Registers..............................................................................................................82
13.9.5. Output Register...................................................................................................................................82
13.9.6. Speaker Mixer Control Register ..........................................................................................................83
13.9.7. Speaker Gain Control Register ...........................................................................................................83
13.9.8. MONO Mixer Control Register ............................................................................................................84
13.9.9. Trimming Register...............................................................................................................................84
13.10. PCM TIME SLOT CONTROL & ADCOUT IMPEDANCE OPTION CONTROL ..........................................85
13.10.1. PCM1 TIMESLOT CONTROL REGISTER..........................................................................................85
13.10.2. PCM2 TIMESLOT CONTROL REGISTER..........................................................................................85
13.11. REGISTER ID (READ ONLY) ....................................................................................................................86
13.11.1. Device revision register.......................................................................................................................86
13.11.2. 2-WIRE ID Register (READ ONLY).....................................................................................................86
13.11.3. Additional ID (READ ONLY)................................................................................................................86
13.12. Reserved....................................................................................................................................................87
13.13. OUTPUT Driver Control Register ...............................................................................................................87
13.14. AUTOMATIC LEVEL CONTROL ENHANCED REGISTER .......................................................................88
13.14.1. ALC1 Enhanced Register....................................................................................................................88
13.14.2. ALC Enhanced 2 Register...................................................................................................................88
13.15. MISC CONTROL REGISTER.....................................................................................................................89
13.16. Output Tie-Off REGISTER .........................................................................................................................90
13.17. ALC PEAK-TO-PEAK READOUT REGISTER ...........................................................................................90
13.18. ALC PEAK READOUT REGISTER............................................................................................................90
13.19. AUTOMUTE CONTROL AND STATUS READ REGISTER.......................................................................91
13.20. Output Tie-off Direct Manual Control REGISTER.......................................................................................91
CONTROL INTERFACE TIMING DIAGRAM ....................................................................................................92
14.1. SPI WRITE TIMING DIAGRAM..................................................................................................................92
14.2. SPI READ TIMING DIAGRAM ...................................................................................................................92
14.3. 2-WIRE TIMING DIAGRAM........................................................................................................................94
AUDIO INTERFACE TIMING DIAGRAM...........................................................................................................95
15.1. AUDIO INTERFACE IN SLAVE MODE......................................................................................................95
15.2. AUDIO INTERFACE IN MASTER MODE ..................................................................................................95
15.3. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Audo Data)................................................................96
15.4. PCM AUDIO INTERFACE IN MASTER MODE (PCM Audo Data) ............................................................96
15.5. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Time Slot Mode ).......................................................97
15.6. PCM AUDIO INTERFACE IN MASTER MODE (PCM Time Slot Mode ) ...................................................97
14.
15.
15.7.
System Clock (MCLK) Timing Diagram...............................................................................................98
15.8. µ-LAW ENCODE DECODE CHARACTERISTICS.....................................................................................99
15.9. A-LAW ENCODE DECODE CHARACTERISTICS...................................................................................100
15.10. µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE........................................................................101
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15.11. µ-LAW / A-LAW OUTPUT CODES (DIGITAL MW)..................................................................................101
16.
17.
18.
DIGITAL FILTER CHARACTERISTICS ..........................................................................................................102
TYPICAL APPLICATION.................................................................................................................................104
PACKAGE SPECIFICATION...........................................................................................................................106
18.1. 28 Pin SSOP32-Pin QFN .........................................................................................................................106
18.1. 32-Pin QFN ..............................................................................................................................................107
ORDERING INFORMATION...........................................................................................................................108
VERSION HISTORY .......................................................................................................................................109
19.
20.
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NAU8812
6. List of Figures
Figure 1: 28-Pin SSOP Package...................................................................................................................................3
Figure 2: 32-Pin QFN Package .....................................................................................................................................3
Figure 3: NAU8812 General Block Diagram..................................................................................................................5
Figure 4: Auxiliary Input Circuit Block Diagram with AUXM[3] = 0...............................................................................18
Figure 5: Auxiliary Input Circuit Block Diagram with AUXM[3] = 1...............................................................................18
Figure 6: Input PGA Circuit Block Diagram .................................................................................................................19
Figure 7: Boost Stage Block Diagram .........................................................................................................................21
Figure 8: Microphone Bias Schematic.........................................................................................................................23
Figure 9: ADC Digital Filter Path Block Diagram.........................................................................................................25
Figure 10: ALC Block Diagram....................................................................................................................................28
Figure 11: ALC Response Graph................................................................................................................................28
Figure 12: ALC Normal Mode Operation.....................................................................................................................30
Figure 13: ALC Hold Time...........................................................................................................................................31
Figure 14: ALC Limiter Mode Operations....................................................................................................................31
Figure 15: ALC Operation with Noise Gate disabled...................................................................................................32
Figure 16: ALC Operation with Noise Gate Enabled...................................................................................................33
Figure 17: DAC Digital Filter Path ...............................................................................................................................34
Figure 18: DAC Digital Limiter Control ........................................................................................................................36
Figure 19: Speaker and MONO Analogue Outputs.....................................................................................................37
Figure 20: Tie-off Options for the Speaker and MONO output Pins ............................................................................39
Figure 21: PLL and Clock Select Circuit......................................................................................................................43
Figure 22: Register write operation using a 16-bit SPI Interface .................................................................................48
Figure 23: Register Write operation using a 24-bit SPI Interface ................................................................................49
Figure 24: Register Read operation through a 32-bit SPI Interface.............................................................................49
Figure 25: Valid START Condition ..............................................................................................................................50
Figure 26: Valid Acknowledge.....................................................................................................................................50
Figure 27: Valid STOP Condition ................................................................................................................................50
Figure 28: Slave Address Byte, Control Address Byte, and Data Byte .......................................................................50
Figure 29: Byte Write Sequence .................................................................................................................................51
Figure 30: 2-Wire Read Sequence..............................................................................................................................51
Figure 31: Right Justified Audio Interface (Normal Mode)...........................................................................................53
Figure 32: Right Justified Audio Interface (Special mode) ..........................................................................................53
Figure 33: Left Justified Audio Interface (Normal Mode).............................................................................................54
Figure 34: Left Justified Audio Interface (Special mode).............................................................................................54
Figure 35: I2S Audio Interface (Normal Mode)............................................................................................................55
Figure 36: I2S Audio Interface (Special mode)............................................................................................................55
Figure 37: PCM Mode Audio Interface (Normal Mode) ...............................................................................................56
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Figure 38: PCM Mode Audio Interface (Special mode)...............................................................................................56
Figure 39: PCM Time Slot Mode (Time slot = 0) (Normal Mode) ................................................................................57
Figure 40: PCM Time Slot Mode (Time slot = 0) (Special mode) ................................................................................57
Figure 41: The Programmable ADCOUT Pin ..............................................................................................................85
Figure 42: SPI Write Timing Diagram..........................................................................................................................92
Figure 43: SPI Read Timing Diagram .........................................................................................................................92
Figure 44: 2-Wire Timing Diagram ..............................................................................................................................94
Figure 45: Audio Interface Slave Mode Timing Diagram.............................................................................................95
Figure 46: Audio Interface in Master Mode Timing Diagram .......................................................................................95
Figure 47: PCM Audio Interface Slave Mode Timing Diagram....................................................................................96
Figure 48: PCM Audio Interface Slave Mode Timing Diagram....................................................................................96
Figure 49: PCM Audio Interface Slave Mode (PCM Time Slot Mode )Timing Diagram..............................................97
Figure 50: PCM Audio Interface Master Mode (PCM Time Slot Mode )Timing Diagram.............................................97
Figure 51: MCLK Timing Diagram...............................................................................................................................98
Figure 52: DAC Filter Frequency Response..............................................................................................................103
Figure 53: ADC Filter Frequency Response..............................................................................................................103
Figure 54: DAC Filter Ripple .....................................................................................................................................103
Figure 55: ADC Filter Ripple .....................................................................................................................................103
Figure 56: Application Diagram 28-Pin SSOP...........................................................................................................104
Figure 57: Application Diagram for 32-Pin QFN........................................................................................................105
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7. List of Tables
Table 1: Pin Description for SSOP and QFN Packages................................................................................................4
Table 2: Register associated with Input PGA Contro ..................................................................................................19
Table 3: Microphone Non-Inverting Input Impedances.................................................................................................20
Table 4: Microphone Inverting Input Impedances .......................................................................................................20
Table 5: Registers associated with ALC and Input PGA Gain Control ........................................................................21
Table 6: Registers associated with PGA Boost Stage Control ....................................................................................22
Table 7: Register associated with Microphone Bias....................................................................................................23
Table 8: Microphone Bias Voltage Control..................................................................................................................24
Table 9: Register associated with ADC.......................................................................................................................25
Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1).......................................................................................26
Table 11: Registers associated with Notch Filter Function..........................................................................................26
Table 12: Equations to Calculate Notch Filter Coefficients..........................................................................................27
Table 13: Register associated with ADC Gain ............................................................................................................27
Table 14: Registers associated with ALC Control .......................................................................................................29
Table 15: ALC Maximum and Minimum Gain Values..................................................................................................29
Table 16: Registers associated with DAC Gain Control..............................................................................................34
Table 17: Speaker Output Controls.............................................................................................................................38
Table 18: MONO Output Controls...............................................................................................................................38
Table 19: General Purpose Control.............................................................................................................................41
Table 20: Jack Insert Detect mode..............................................................................................................................41
Table 21: Jack Insert Detect controls..........................................................................................................................42
Table 22: Thermal Shutdown ......................................................................................................................................42
Table 23: Registers associated with PLL ....................................................................................................................44
Table 24: Registers associated with PLL ....................................................................................................................45
Table 25: PLL Frequency Examples ...........................................................................................................................46
Table 26: Control Interface Selection..........................................................................................................................47
Table 27: Standard Interface modes...........................................................................................................................52
Table 28: Audio Interface Control Registers................................................................................................................52
Table 29: Companding Control ...................................................................................................................................58
Table 30: Power up sequence.....................................................................................................................................61
Table 31: Power down Sequence ...............................................................................................................................61
Table 32: Registers associated with Power Saving.....................................................................................................62
Table 33: VDDA 3.3V Supply Current .........................................................................................................................62
Table 34: SPI Timing Parameters ...............................................................................................................................93
Table 35: 2-WireTiming Parameters ...........................................................................................................................94
Table 36: Audio Interface Timing Parameters.............................................................................................................98
Table 37: MCLK Timing Parameter.............................................................................................................................98
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NAU8812
8. ABSOLUTE MAXIMUM RATINGS
CONDITION
VDDB, VDDC, VDDA supply voltages
VDDSPK supply voltage (MOUT=0, SPKBST=0)
VDDSPK supply voltage (MOUTBST=1, SPKBST=1)
Core Digital Input Voltage range
MIN
-0.3
MAX
+3.63
Units
V
V
-0.3
+3.63
-0.3
+5.50
V
VSSD – 0.3
VSSD – 0.3
VSSA – 0.3
-40
VDDC + 0.30
VDDB + 0.30
VDDA + 0.30
+85
V
Buffer Digital Input Voltage range
Analog Input Voltage range
V
V
Industrial operating temperature
0C
0C
Storage temperature range
-65
+150
CAUTION: Do not operate at or near the maximum ratings listed for extended period of time. Exposure to such
conditions may adversely influence product reliability and result in failures not covered by warranty. These
devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
9. OPERATING CONDITIONS
Typical
Value
Condition
Analogue supplies range
Digital supply range (Buffer)
Digital supply range (Core)
Speaker supply
Symbol
VDDA
Min Value
2.501
Max Value
3.60
Units
V
VDDB
1.712
3.60
V
VDDC
1.712
3.60
V
VDDSPK
2.50
5.50
V
VSSD, VSSA,
VSSSPK
Ground
0
V
Note:
1. VDDA must be ≥ VDDC.
2. VDDB must be ≥ VDDC.
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NAU8812
10. ELECTRICAL CHARACTERISTICS
VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25oC, 1kHz signal,
fs = 48kHz, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue to Digital Converter (ADC)
PGABST = 0dB
1.0
0
VRMS
dBV
dB
Full scale input signal 1
VINFS
PGAGAIN = 0dB
Signal to Noise Ratio 2
Total Harmonic Distortion 3
SNR
THD
Gain = 0dB, A-weighted
Input = -1dBFS, Gain = 0dB
87
91
-79
-65
dB
Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load)
1.0x
(VREF
MOUTBST=0
Full Scale output signal 1
)
VRMS
1.5 x
VREF
MOUTBST=1
A-weighted (ADC/DAC oversampling rate
of 128)
Signal to Noise Ratio 2
SNR
THD
90
93
dB
dB
Total Harmonic Distortion 3
RL = 10 kΩ; -1.0dBfs
-84
-70
Auxiliary Analogue Input (AUX)
1
0
VRMS
dBV
Full-scale Input Signal Level1
VINFS
Gain = 0dB
AUXM=0
Input Resistance
Input Capacitance
RAUX
CAUX
20
kΩ
10
pF
Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA)
PGABST = 0dB
1
0
VRMS
dBV
dB
Full-scale Input Signal Level 1
VINFS
PGAGAIN = 0dB
Programmable input PGA gain
Programmable Gain Step Size
-12
35.25
Guaranteed monotonic
PGABST = 0
0.75
0
dB
dB
dB
µV
Programmable Boost PGA
gain
PGABST = 1
20
Mute Attenuation
100
0 to 20kHz,
PGA equivalent output noise
110
Gain set to 35.25dB
PGA Gain = 35.25dB
kΩ
kΩ
kΩ
1.6
47
75
Auxiliary Input resistance
RAUX
PGA Gain = 0dB
PGA Gain = -12dB
Positive Microphone Input
resistance
kΩ
RMIC+
CMIC
PMICPGA = 1
94
10
Input Capacitance
pF
Speaker Output PGA
Programmable Gain
dB
dB
-57
6
Programmable Gain Step Size
Guaranteed monotonic
1
VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25oC, 1kHz signal,
fs = 48kHz, 24-bit audio data unless otherwise stated.
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NAU8812
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRMS
BTL Speaker Output (SPKOUT+, SPKOUT- with 8Ω bridge tied load)
SPKBST = 0
VDDSPK = VDDA
SPKBST = 1
VDDSPK = 1.5 * VDDA
VDDA / 3.3
Full scale output 7
(VDDA / 3.3) * 1.5
Output power is very closely correlated with THD;
Output Power
PO
see below
VDDSPK = 3.3V
RL = 8Ω
90
90
dB
dB
Signal to Noise Ratio
SNR
VDDSPK = 1.5*VDDA
RL = 8Ω
PO
=180mW
-63
-56
-60
-61
dB
dB
dB
dB
VDDSPK=3.3V
PO
=400mW
RL =
8Ω
PO
=360mW
Total Harmonic Distortion
THD
VDDSPK =
1.5*VDDA
PO
=800mW
PO =1W
-34
50
dB
dB
dB
Power Supply Rejection Ratio
(50Hz - 22kHz)
VDDSPK = 3V, SPKBST = 0
PSRR
VDDSPK = 1.5*VDDA, SPKBST = 1
50
Headphone’ output (SPKOUTP, SPKOUTN with resistive load to ground)
Full scale output 7
VDDA / 3.3
90
VRMS
dB
Signal to Noise Ratio
Total Harmonic Distortion
Microphone Bias
A-weighted
Po = 20mW
SNR
THD
RL=16
Ω
-84
-85
dB
dB
VDDSPK=3.3V
RL=32
Ω
Po = 20mW
0.9*
VDD
A
(MICBIASV = 0)
(MICBIASV = 1)
V
V
Bias Voltage
VMICBIAS
0.65*
VDD
A
Bias Current Source
Output Noise Voltage
IMICBIAS
3
mA
MICBIASM = 0
(1kHz to 20kHz)
MICBIASM = 1
(1kHz to 20kHz)
14
nV/√Hz
VN
4
nV/√Hz
Automatic Level Control (ALC)/Limiter – ADC only
Target Record Level
-28.5
-12
-6
dB
Programmable Gain
35.25
dB
dB
0.75
Programmable Gain Step Size
Gain Hold Time 4, 6
Guaranteed Monotonic
MCLK=12.288MHz
0 / 2.67 / …/ 43691
(time doubles with
each step)
tHOLD
ms
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NAU8812
VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25oC, 1kHz signal,
fs = 48kHz, 24-bit audio data unless otherwise stated.
PARAMETER
Automatic Level Control (ALC)/Limiter – ADC only
ALC Mode
ALCM=0
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3 / 6.6 / 13.1 / … /
3360 (time doubles every
step)
ms
ms
Gain Ramp-Up (Decay) Time 5,
MCLK=12.288MHz
Limiter Mode
ALCM=1
tDCY
6
0.73 / 1.45 / 2.91 / … /
744 (time doubles every
step)
MCLK=12.288MHz
ALC Mode
0.83 / 1.66 / 3.33 / … /
852 (time doubles every
step)
ALCM=0
ms
ms
MCLK=12.288MHz
Limiter Mode
ALCM=1
Gain Ramp-Down (Attack)
Time 5, 6
tATK
0.18 / 0.36 / 0.73 / … /
186 (time doubles every
step)
MCLK=12.288MHz
Digital Input / Output
0.7 ×
VDDB
0.3 ×
Input HIGH Level
VIH
VIL
V
V
V
V
Input LOW Level
Output HIGH Level
Output LOW Level
VDDB
0.9 ×
VOH
VOL
IOL = 1mA
VDDB
0.1 x
IOH = -1mA
VDDB
Notes
1. Full Scale is relative to VDDA (FS = VDDA/3.3.). Input level to AUX is limited to a maximum of -3dB so that
THD+N performance will not be reduced.
2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the
output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
3. THD+N (dB) - THD+N are a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain.
It does not apply to ramping down the gain when the signal is too loud, which happens without a delay.
5. Ramp-up and Ramp-Down times are defined as the time it takes to change the PGA gain by 6dB of its gain
range.
6. All hold, ramp-up and ramp-down times scale proportionally with MCLK
7. The maximum output voltage can be limited by the speaker power supply. If MOUTBST or SPKBST is, set
then VDDSPK should be 1.5xVDDA to prevent clipping taking place in the output stage (when PGA gains are set
to 0dB).
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NAU8812
11. FUNCTIONAL DESCRIPTION
The NAU8812 is a MONO Audio CODEC with very robust ADC and DAC. The device provides one single ended
auxiliary input (AUX pin) and one differential microphone input (MIC- & MIC+ pins). The auxiliary input (AUX) can
be configured to sum multiple signals into a single input. It has three different amplification paths with a total gain
of up to +55.25dB. The differential input also has amplification paths similar to auxiliary input.
The device also has an internal configurable biasing circuit for biasing the microphone, which in turn reduces
external components. The PGA output has programmable ADC gain. An advanced Sigma Delta DAC is used
along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 kHz to 48
kHz. The Digital Filter blocks include ADC high pass filters, and Notch filter. The device has two output mixers,
one for MONO output and the other for the speaker output. It also has one input mixer.
The NAU8812 has two different types of serial control interface 2-Wire and SPI for device control. 2-Wire and
SPI are hardware selectable through MODE pin on the device. The device also supports I2S, PCM time slotting,
Left Justified and Right Justified for audio interface.
The device can operate as a master or slave device. It can operate with sample rates ranging from 8 kHz to 48
kHz, depending on the values of MCLK and its prescaler. The NAU8812 includes a PLL block, where it takes the
external clock (MCLK pin) to generate other clocks for the audio data transfer such as Bit clock (BCLK), Frame
sync (FS), and I2S clocks. The PLL can also configure a separate programmable clock for the use in the system
through CSb/GPIO pin. The power control registers help save power by controlling the major individual functional
blocks of the NAU8812.
11.1. INPUT PATH
The NAU8812 has two different types of microphone inputs single ended and differential. Figure 3 shows the
different paths that the input signals can take.
All inputs are maintained at a DC bias at approximately half of the VDDA supply voltage. Connections to these
inputs should be AC-coupled by means of DC blocking capacitors suitable for the device application.
11.1.1. The Single Ended Auxiliary Input (AUX)
The single ended auxiliary input (AUX) has three different paths to MONO output (MOUT).
Directly connected to the MONO Mixer or Speaker Mixer to MOUT or SPKOUT+ and SPKOUT- respectively
Connect through the PGA Boost Mixer which has a range of -12dB to +6dB
Connect through both the input PGA Gain (range of -12dB to +35.25 dB) and PGA Boost Mixer (range of 0db
or +20dB)
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NAU8812
The last two paths above go through the ADC filters where the ALC loop controls the amplitude of the input signal.
The device also has an internal configurable biasing circuit for biasing the microphone, reducing external
components.
An internal inverting operational amplifier circuit allows the auxiliary input pin to connect multiple signals for mixing.
This can be achieved by setting AUXM[3] address (0x2C) to LOW. The combination of the 20k ohm resistors can
vary due to process variation in the gain stage. The block can also be configured to be used as a buffer by
setting AUXM[3] address (0x2C) to HIGH. The internal inverting circuit block can be enable/disable by setting
AUXEN[6] address (0x01).
AUXM[3]
(0x2C)
R
20k
20k
AUX
Pin
Output to
PGA Gain
MONO Mixer
Speaker Mixer
AUXM[3]
(0x2C)
VREF
AUXEN[6]
(0x01)
Figure 4: Auxiliary Input Circuit Block Diagram with AUXM[3] = 0
AUXM[3]
(0x2C)
R
R
R
20k
20k
AUX
Pin
Output to
PGA Gain
MONO Mixer
Speaker Mixer
AUXM[3]
(0x2C)
VREF
AUXEN[6]
(0x01)
Figure 5: Auxiliary Input Circuit Block Diagram with AUXM[3] = 1
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NAU8812
11.1.2. The differential microphone input (MIC- & MIC+ pins)
The NAU8812 features a low-noise, high common mode rejection ratio (CMRR), differential microphone inputs
(MIC- & MIC+ pins) which are connected to a PGA Gain stage. The differential input structure is essential in
noisy digital systems where amplification of low-amplitude analog signals is necessary such as notebooks and
PDAs. When properly employed, the differential input architecture offers an improved power-supply rejection ratio
(PSRR) and higher ground noise immunity.
PGAGAIN[5:0]
(0x2D)
AUXPGA[2]
AUXPGA[2]
(0x2C)
(0x2C)
From AUX
stage
R
R
R
NMICPGA[1]
(0x2C)
NMICPGA[1]
(0x2C)
MIC-
R
PGAGAIN[5:0]
(0x2D)
PMICPGA[0]
(0x2C)
MIC+
To PGA
Boost
-12 dB to +35.25 dB
R
VREF
PGAGAIN[5:0]
(0x2D)
Figure 6: Input PGA Circuit Block Diagram
Bit(s)
Addr
Parameter
Programmable Range
0 = Input PGA Positive terminal to VREF
1 = Input PGA Positive terminal to MICP
PMICPGA[0]
0x2C
Positive Microphone to PGA
Negative Microphone to
PGA
0 = MICN not connected to input PGA
1 = MICN to input PGA Negative terminal.
NMICPGA[1]
0x2C
Table 2: Register associated with Input PGA Contro
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NAU8812
11.1.2.1.
Positive Microphone Input (MIC+)
The positive microphone input (MIC+) can be used as part of the differential input. It connects to the positive
terminal of the PGA gain amplifier by setting PMICPGA[0] address (0x2C) to HIGH or can be connected to VREF
by setting PMICPGA[0] address (0x2C) to LOW.
When the associated control bit is set logic = 1, the MIC+ pin is connected to a resistor of approximately 1kΩ
which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC
level of the MIC+ pin close to VREF at all times.
Note: In single ended applications where the MIC+ input is used without using MIC-, the PGA gain values will be
valid only if the MIC- pin is terminated to a low impedance signal point. This termination should normally be an
AC coupled path to signal ground. This input impedance is constant regardless of the gain value. The following
table gives the nominal input impedance for this input. Impedance for specific gain values not listed in this table
can be estimated through interpolation between listed values.
MIC+ to non-inverting PGA input
MIC- to inverting PGA input
Nominal Input Impedance
Nominal Input Impedance
Gain (dB)
Impedance (kΩ)
Gain (dB)
Impedance (kΩ)
-12
-9
94
94
94
94
94
94
94
94
94
94
94
94
-12
-9
75
69
63
55
47
39
31
25
19
11
2.9
1.6
-6
-3
-6
-3
0
0
3
3
6
6
9
9
12
18
30
35.25
12
18
30
35.25
Table 3: Microphone Non-Inverting
Input Impedances
Table 4: Microphone Inverting Input
Impedances
11.1.2.2. Negative Microphone Input (MIC-)
The negative microphone input (MIC-) has two distinctive configuration; differential input or single ended input.
This input connects to the negative terminal of the PGA gain amplifier by setting NMICPGA[1] address (0x2C) to
HIGH. When the MIC- is used as a single ended input, MIC+ should be conned to VREF by setting PMICPGA[0]
address (0x2C) bit to LOW. The AUX input signal can also be mixed with the MIC- input signal by setting
AUXPGA[2] address (0x2C) to HIGH.
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NAU8812
When the associated control bit is set logic = 1, the MIC- pin is connected to a resistor of approximately 30kΩ
which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC
level of the MIC- pin close to VREF at all times. It is important for a system designer to know that the MIC-input
impedance varies as a function of the selected PGA gain. This is normal and expected for a difference amplifier
type topology. The above table gives the nominal resistive impedance values for this input over the possible gain
range. Impedance for specific gain values not listed in this table can be estimated through interpolation between
listed values.
11.1.2.3.
PGA Gain Control
The PGA amplification is common to all three input pins MIC-, MIC+, AUX, and enabled by PGAEN[2] address
(0x02). It has a range of -12dB to +35.25dB in 0.75dB steps, controlled by PGAGAIN[5:0] address (0x2D). Input
PGA gain will not be used when ALC is enabled using ALCEN[8] address (0x20).
Addr
0x2D
0x20
Bit 8
0
Bit 7
Bit 6
Bit5
Bit 4
Bit 3
PGAGAIN[5:0]
ALCMXGAIN[2:0] ALCMNGAIN[2:0]
Table 5: Registers associated with ALC and Input PGA Gain Control
Bit 2
Bit 1
Bit 0
Default
0x010
0x038
PGAZC PGAMT
ALCEN
0
0
11.1.3.
PGA Boost Stage
The boost stage has three inputs connected to the PGA Boost Mixer. All three inputs can be individually
connected or disconnected from the PGA Boost Mixer. The boost stage can be enabled by setting BSTEN[4]
address (0x02) to HIGH. The following figure shows the PGA Boost stage.
AUXBSTGAIN[2:0]
(0x2F)
Output from
AUX stage
PGABST[8]
(0x2F)
PGAMT[6]
(0x2D)
Output from
PGA Gain
To ADC
PMICBSTGAIN[6:4]
(0x2F)
MIC+
Pin
Figure 7: Boost Stage Block Diagram
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NAU8812
The signal from AUX stage can be amplified at the PGA Boost stage before connecting to the Boost Mixer by
setting a binary value from “001” - “111” to AUXBSTGAIN[2:0] address (0x2F). The path is disconnected by
setting “000” to the AUXBSTGAIN bits.
Signal from PGA stage to the PGA Boost Mixer is disconnected or muted by setting PGAMT[6] address (0x2D) to
HIGH. In this path the PGA boost can be a fixed value of +20dB or 0dB, controlled by the PGABST[8] address
(0x2F) bit.
The signal from MIC+ pin to the PGA Boost Mixer is disconnected by setting ‘000’ binary value to
PMICBSTGAIN[6:4] address (0x2F) and any other combination connects the path.
Bit(s)
BSTEN[4]
Addr
0x02
Parameter
Programmable Range
0 = Boost stage OFF
Enable PGA Boost Block
1 = Boost stage ON
0=Input PGA not muted
1=Input PGA muted
PGAMT[6]
0x2D
0x2F
0x2F
0x2F
Mute control for input PGA
Boost AUX signal
AUXBSTGAIN[2:0]
PMICBSTGAIN[6:4]
PGABST[8]
Range: -12dB to +6dB @ 3dB increment
Range: -12dB to +6dB @ 3dB increment
Boost MIC+ signal
Boost PGA stage
0 = PGA output has +0dB
1 = PGA output has +20dB
Table 6: Registers associated with PGA Boost Stage Control
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NAU8812
11.2. MICROPHONE BIASING
MICBIASM[0]
(0x28)
VREF
MICBIAS
R
R
MICBIASV[1:0]
(0x2C)
Figure 8: Microphone Bias Schematic
The MICBIAS pin is a low-noise microphone bias source for an external microphone, which can provide a
maximum of 3mA of bias current. This DC bias voltage is suitable for powering either traditional ECM (electret)
type microphones, or for MEMS types microphones with an independent power supply pin. Seven different bias
voltages are available for optimum system performance, depending on the specific application. The microphone
bias pin normally requires an external filtering capacitor as shown on the schematic in the Application section.
The output bias can be enabled by setting MICBIASEN[4] address (0x01) to HIGH. It has various voltage values
selected by a combination of bits MICBIASM[4] address (0x3A) and MICBIASV[8:7] address (0x2C).
The low-noise feature results in greatly reduced noise in the external MICBIAS voltage by placing a resistor of
approximately 200-ohms in series with the output pin. This creates a low pass filter in conjunction with the
external microphone-bias filter capacitor, but without any additional external components.
Bit(s)
Addr
0x01
Parameter
Microphone bias enable
Programmable Range
0 = Disable
1 = Enable
MICBIASEN[4]
MICBIASM[4]
(0x3A)
(0x2C)
Microphone bias mode selection
Microphone bias voltage selection
0 = Disable
1 = Enable
MICBIASV[8:7]
Table 7: Register associated with Microphone Bias
Below are the unloaded values when MICBIASM[4] is set to 1 and 0. When loaded, the series resistor will cause
the voltage to drop, depending on the load current.
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NAU8812
Microphone Bias Voltage Control
MICBIASV[8:7] MICBIASM[4] = 0 MICBIASM[4]= 1
0
0
1
1
0
1
0
1
0.9* VDDA
0.65* VDDA
0.75* VDDA
0.50* VDDA
0.85* VDDA
0.60* VDDA
0.70* VDDA
0.50* VDDA
Table 8: Microphone Bias Voltage Control
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NAU8812
11.3. ADC DIGITAL FILTER BLOCK
ADC Digital Filters
High
Pass
Filter
Digital
Audio
Interface
Digital
Decimator
Digital
Filter
Notch
Filter
/
ADC
Gain
Figure 9: ADC Digital Filter Path Block Diagram
The ADC digital filter block performs a 24-bit signal processing. The block consists of an oversampled analog
sigma-delta modulator, digital decimator, digital filter, high pass filter, and a notch filter. The oversampled analog
sigma-delta modulator provides a bit stream to the decimation stages and filter. The ADC coding scheme is in
twos-complement format and the full-scale input level is proportional to VDDA. With a 3.3V supply voltage, the
full-scale level is 1.0VRMS and any voltage greater than full scale may overload the ADC and cause distortion.
The ADC is enabled by setting ADCEN[0] address (0x02) bit. Polarity and oversampling rate of the ADC output
signal can be changed by ADCPL[0] address (0x0E) and ADCOS[3] address (0x0E) respectively.
Bit(s)
Addr
0x0E
Parameter
Programmable Range
0 = Normal
1 = Inverted
ADCPL[0]
ADC Polarity
ADC Over Sample
Rate
0=64x (Lowest power)
1=128x (best SNR at typical condition)
ADCOS[3]
HPFEN[8]
HPFAM[7]
HPF[6:4]
0x0E
0x0E
0x0E
0x0E
0x02
0x07
High Pass Filter
Enable
0 = Disable
1 = Enable
0 = Audio (1st order, fc ~ 3.7 Hz)
Audio or Application Mode
High Pass Filter frequencies
Enable ADC
1 = Application (2nd order, fc =HPF)
82 Hz to 612 Hz dependant on the sample
rate
0 = Disable
1 = Enable
ADCEN[0]
SMPLR[3:1]
Sample rate
8k Hz to 48 kHz
Table 9: Register associated with ADC
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NAU8812
11.3.1. Programmable High Pass Filter (HPF)
The high pass filter (HPF) has two different modes that it can operate in either Audio or Application mode
HPFAM[7] address (0x0E). In Audio Mode (HPFAM=0) the filter is first order, with a cut-off frequency of 3.7Hz.
In Application mode (HPFAM=1) the filter is second order, with a cut-off frequency selectable via the HPF[2:0]
register bits. Cut-off frequency of the HPF depends on sample frequency selected by SMPLR[3:1] address (0x07).
The HPF is enabled by setting HPFEN[8] address (0x0E) to HIGH. Table below shows the cut-off frequencies
with different sampling rate.
fs (kHz)
HPF[2:0]
SMPLR=101/100
11.025
SMPLR=011/010
SMPLR=001/000
8
12
16
22.05
113
141
180
225
281
360
450
563
24
32
44.1
113
141
180
225
281
360
450
563
48
000
001
010
011
100
101
110
111
82
113
122
153
156
245
306
392
490
612
82
122
153
156
245
306
392
490
612
82
122
153
156
245
306
392
490
612
102
131
163
204
261
327
408
141
180
225
281
360
450
563
102
131
163
204
261
327
408
102
131
163
204
261
327
408
Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1)
11.3.2. Programmable Notch Filter (NF)
The NAU8812 has a programmable notch filter where it passes all frequencies except those in a stop band
centered on a given center frequency. The filter gives lower distortion and flattens response. The notch filter is
enabled by setting NFCEN[7] address (0x1B) to HIGH. The variable center frequency is programmed by setting
two’s complement values to NFCA0[6:0] address (0x1C), NFCA0[13:7] address (0x1B) and NFCA1[6:0] address
(0x1E), NFCA1[13:7] address (0x1D) registers. The coefficients are updated in the circuit when the NFCU[8] bit
is set HIGH in a write to any of the registers NF1-NF4 address (0x1B, 0x1C, 0x1D, 0x1E).
Addr
0x1B
0x1C
0x1D
0x1E
Bit 8
Bit 7
Bit 6
Bit5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
0x000
0x000
0x000
0x000
NFCU
NFCU
NFCU
NFCU
NFCEN
NFCA0[13:7]
NFCA0[6:0]
NFCA1[13:7]
NFCA1[6:0]
0
0
0
Table 11: Registers associated with Notch Filter Function
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A0
A1
Notation
Register Value (DEC)
2
f
NFCA0 = -A0 x 213
NFCA1 = -A1 x 212
(then convert to 2’s
complement)
b
b
fc = center frequency (Hz)
fb = -3dB bandwidth (Hz)
fs = sample frequency
1 tan
1 tan
2
f
f
2
f
s
c
x cos
1 A
Coefficient
0
f
2
f
s
(Hz)
2
s
Table 12: Equations to Calculate Notch Filter Coefficients
11.3.3. Digital ADC Gain Control
The digital ADC can be muted by setting “0000 0000” to ADCGAIN[7:0] address (0x0F). Any other combination
digitally attenuates the ADC output signal in the range -127dB to 0dB in 0.5dB increments].
Addr
Name
Bit 8
0
Bit 7
Bit 6
Bit5
Bit 4
ADCGAIN
Table 13: Register associated with ADC Gain
Bit 3
Bit 2
Bit 1
Bit 0 Default
0x0F ADCG
0x0FF
11.4. PROGRAMMABLE GAIN AMPLIFIER (PGA)
NAU8812 has a programmable gain amplifier (PGA) which controls the gain such that the signal level of the PGA
remains substantially constant as the input signal level varies within a specified dynamic range. The PGA has
two functions
Automatic level control (ALC) or
Input peak limiter
The Automatic Level Control (ALC) seeks to control the PGA gain in response to the amplitude of the input signal
such that the PGA output maintains a constant envelope. A digital peak detector monitors the input signal
amplitude and compares it to a register defined threshold level ALCSL[3:0] address (0x21). Note: When the ALC
automatic level control is enabled, the function of the ALC is to automatically adjust PGAGAIN[5:0] address (0x2D)
volume setting.
11.4.1. Automatic level control (ALC)
The ALC seeks to control the PGA gain such that the PGA output maintains a constant envelope. This helps to
prevent clipping at the input of the sigma delta ADC while maximizing the full dynamic range of the ADC. The
ALC monitors the output of the ADC, measured after the digital decimator has converted it to 1.23 fixed-point
formats. The ADC output is fed into a peak detector, which updates the measured peak value whenever the
absolute value of the input signal is higher than the current measured peak. The measured peak gradually
decays to zero unless a new peak is detected, allowing for an accurate measurement of the signal envelope.
Based on a comparison between the measured peak value and the target value, the ALC block adjusts the gain
control, which is fed back to the PGA.
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Rate Convert/ Decimator
Input
Pin
Digital
Filter
Sinc
Filter
Digital
Decimator
PGA
ADC
ALC
Figure 10: ALC Block Diagram
The ALC is enabled by setting ALCEN[8] address (0x20) bit to HIGH. The ALC has two functional modes, which
is set by ALCM[8] address (0x22).
Normal mode (ALCM = LOW)
Peak Limiter mode (ALCM = HIGH)
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update
must be made by writing to the PGAGAIN[5:0] address (0x2D). A digital peak detector monitors the input signal
amplitude and compares it to a register defined threshold level ALCSL[3:0] address (0x21).
Input < noise
gate threshold
Gain (Attenuation) Clipped
at ALCMNGAIN -12dB
ALC operation range
Target ALCSL -6dB
+33 dB
ALCNEN = 1
PGA Gain
ALCNTH = -39dB
MIC Boost Gain = 0dB
ALCSL = -6dB
0 dB
ALCMNGAIN = -12dB
ALCMXGAIN = +35.25dB
-12 dB
-39dB
-39dB
-6dB +6dB
Input Level
Figure 11: ALC Response Graph
The registers listed in the following section allow configuration of ALC operation with respect to:
ALC target level
Gain increment and decrement rates
Minimum and maximum PGA gain values for ALC operating range
Hold time before gain increments in response to input signal
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Inhibition of gain increment during noise inputs
Limiter mode operation
Bit(s)
Addr
0x20
Parameter
Programmable Range
ALCMNGAIN[2:0]
ALCMXGAIN[2:0]
Minimum Gain of PGA
Range: -12dB to +30dB @ 6dB increment
Maximum Gain of PGA
Enable ALC function
ALC Target
Range: -6.75dB to +35.25dB @ 6dB increment
0 = Disable
1 = Enable
ALCEN[8]
ALCSL[3:0]
ALCHT[3:0]
Range: -28.5dB to -6dB @ 1.5dB increment
ALC Hold Time
Range: 0ms to 1s, time doubles with every step)
0x21
0 = Disable
1 = Enable
ALCZC[8]
ALC Zero Crossing
ALC Attack time
ALCM=0 - Range: 125us to 128ms
ALCM=1 - Range: 31us to 32ms (time doubles with
every step)
ALCATK[3:0]
ALCM=0 - Range: 500us to 512ms
ALCM=1 - Range: 125us to 128ms
(Both ALC time doubles with every step)
0x22
ALCDCY[3:0]
ALCM[8]
ALC Decay time
ALC Select
0 = ALC mode
1 = Limiter mode
Table 14: Registers associated with ALC Control
The operating range of the ALC is set by ALCMXGAIN[5:3] address (0x20) and ALCMNGAIN[2:0] address (0x20)
bits such that the PGA gain generated by the ALC is between the programmed minimum and maximum levels.
When the ALC is enabled, the PGA gain is disabled.
In Normal mode, the ALCMXGAIN bits set the maximum level for the PGA in the ALC mode but in the Limiter
mode ALCMXGAIN has no effect because the maximum level is set by the initial PGA gain setting upon enabling
of the ALC.
ALCMAXGAIN
Maximum Gain (dB)
ALCMINGAIN
Minimum Gain (dB)
111
110
35.25
29.25
000
001
-12
-6
ALC Max Gain Range 35.25dB to -6dB @
6dB increments
ALC Min Gain Range -12dB to 30dB @
6dB increments
001
000
-0.75
-6.75
110
111
24
30
Table 15: ALC Maximum and Minimum Gain Values
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11.4.1.1.
Normal Mode
Normal mode is selected when ALCM[8] address (0x22) is set LOW and the ALC is enabled by setting ALCEN[8]
address (0x20) HIGH. This block adjusts the PGA gain setting up and down in response to the input level. A
peak detector circuit measures the envelope of the input signal and compares it to the target level set by
ALCSL[3:0] address (0x21). The ALC increases the gain when the measured envelope is greater than the target
and decreases the gain when the measured envelope is less than - 1.5dB. The following waveform illustrates the
behavior of the ALC.
PGA Input
PGA Output
PGA Gain
Figure 12: ALC Normal Mode Operation
11.4.1.2.
ALC Hold Time (Normal mode Only)
The hold parameter ALCHT[3:0] configures the time between detection of the input signal envelope being outside
of the target range and the actual gain increase.
Input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter
for optimal performance. Increasing the ALC hold time prevents the ALC from reacting too quickly to brief periods
of silence such as those that may appear in music recordings; having a shorter hold time, on the other hand, may
be useful in voice applications where a faster reaction time helps to adjust the volume setting for speakers with
different volumes. The waveform below shows the operation of the ALCHT parameter.
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PGA Input
PGA Output
PGA Gain
Hold Delay
Change
Figure 13: ALC Hold Time
11.4.2. Peak Limiter Mode
Peak Limiter mode is selected when ALCM[8] address (0x22) is set to HIGH and the ALC is enabled by setting
ALCEN[8] address (0x20). In limiter mode, the PGA gain is constrained to be less than or equal to the gain
setting at the time the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than
in normal mode as indicated by the different lookup tables for these parameters for limiter mode. The following
waveform illustrates the behavior of the ALC in Limiter mode in response to changes in various ALC parameters.
PGA Input
PGA
Output
PGA Gain
Limiter
Enabled
Figure 14: ALC Limiter Mode Operations
When the input signal exceeds 87.5% of full scale, the ALC block ramps down the PGA gain at the maximum
attack rate (ALCATK=0000) regardless of the mode and attack rate settings until the ADC output level has been
reduced below the threshold. This limits ADC clipping if there is a sudden increase in the input signal level.
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11.4.3. Attack Time
When the absolute value of the ADC output exceeds the level set by the ALC threshold, ALCSL[3:0] address
(0x21), attack mode is initiated at a rate controlled by the attack rate register ALCATK[3:0] address (0x22). The
peak detector in the ALC block loads the ADC output value when the absolute value of the ADC output exceeds
the current measured peak; otherwise, the peak decays towards zero, until a new peak has been identified. This
sequence is continuously running. If the peak is ever below the target threshold, then there is no gain decrease
at the next attack timer time; if it is ever above the target-1.5dB, then there is no gain increase at the next decay
timer time.
11.4.4. Decay Times
The decay time ALCDCY[6:4] address (0x22) is the time constant used when the gain is increasing. In limiter
mode, the time constants are faster than in ALC mode.
11.4.5. Noise gate (normal mode only)
A noise gate is used when there is no input signal or the noise level is below the noise gate threshold. The noise
gate is enabled by setting ALCNEN[3] address (0x23) to HIGH. It does not remove noise from the signal. The
noise gate threshold ALCNTH[2:0] address (0x23) is set to a desired level so when there is no signal or a very
quiet signal (pause), which is composed mostly of noise, the ALC holds the gain constant instead of amplifying
the signal towards the target threshold. The noise gate only operates in conjunction with the ALC and ONLY in
Normal mode. The noise gate flag is asserted when
(Signal at ADC – PGA gain – MIC Boost gain) < ALCNTH (ALC Noise Gate Threshold) (dB)
Levels at the extremes of the range may cause inappropriate operation, so care should be taken when setting up
the function.
PGA Input
PGA Output
PGA Gain
Figure 15: ALC Operation with Noise Gate disabled
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PGA Input
Noise Gate Threshold
PGA Output
PGA Gain
Figure 16: ALC Operation with Noise Gate Enabled
11.4.6. Zero Crossing
The PGA gain comes from either the ALC block when it is enabled or from the PGA gain register setting when the
ALC is disabled. Zero crossing detection may be enabled to cause PGA gain changes to occur only at an input
zero crossing. Enabling zero crossing detection limits clicks and pops that may occur if the gain changes while
the input signal has a high volume.
There are two zero crossing detection enables:
Register ALCZC[8] address (0x21) – is only relevant when the ALC is enabled.
Register PGAZC[7] address (0x2D) – is only relevant when the ALC is disabled.
If the zero crossing function is enabled (using either register) and SCLKEN[0] address (0x07) is asserted, the zero
cross timeout function may take effect. If the zero crossing flag does not change polarity within 0.25 seconds of a
PGA gain update (either via ALC update or PGA gain register update), then the gain will update. This backup
system prevents the gain from locking up if the input signal has a small swing and a DC offset that prevents the
zero crossing flag from toggling.
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11.5. DAC DIGITAL FILTER BLOCK
DAC Digital Filters
Digital
Audio
Interface
Digital
Peak
Limiter
Sigma
Delta
Modulator
Digital
Gain
Digital
Filters
Interpo-
lation
DAC
Figure 17: DAC Digital Filter Path
The DAC digital block uses 24-bit signal processing to generate analog audio with a 16-bit digital sample stream
input. This block consists of a sigma-delta modulator, high pass filter, digital gain/filters, de-emphasis, and analog
mixers. The DAC coding scheme is in twos complement format and the full-scale output level is proportional to
VDDA. With a 3.3V supply voltage, the full-scale output level is 1.0VRMS. The DAC is enabled by setting
DACEN[0] address (0x03) bit HIGH.
Bit(s)
Addr
0x03
Parameter
Programmable Range
0 = Disable
DACEN[0]
DAC enable
1 = Enable
0 = Disable
Pass-through of ADC output data
into DAC input
ADDAP[0]
DACPL[0]
0x05
1 = Enable
0 = No Inversion
1 = DAC Output Inverted
0 = Disable
DAC Polarity
AUTOMT[2]
DEEMP[5:4]
DACMT[6]
Auto Mute
Sample Rate
Soft Mute
1 = Enable
0x0A
32 kHz, 44.1 kHz, and 48 kHz
0 = Disable
1 = Enable
Range: -127dB to 0dB @ 0.5dB
increment, 00 hex is Muted
DACGAIN[7:0]
0x0B
0x18
DAC Volume Control
DACLIMATK[3:0]
DACLIMDCY[7:4]
DAC Limiter Attack
DAC Limiter Decay
Range: 68us to 139ms
Range: 544us to 1.1s
0 = Disable
DACLIMEN[8]
DAC Limiter Enable
1 = Enable
Range: 0dB to +12dB @ 1dB
increment
DACLIMBST[3:0]
DACLIMTHL[6:4]
DAC Limiter Volume Boost
DAC Limiter Threshold
0x19
Range: -6dB to -1bB @ 1dB increment
Table 16: Registers associated with DAC Gain Control
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11.5.1. DAC Soft Mute
The NAU8812 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero.
When removed, the gain will ramp back up to the digital gain setting. This function is disabled by default. This
feature provides a tool that is useful for using the DACs without introducing pop and click sounds. To play back
an audio signal, it must first be disabled by setting the DACMT[6] address (0x0A) bit to LOW.
11.5.2. DAC Auto Mute
The output of the DAC can be muted by the analog auto mute function. The auto mute function is enabled by
setting AUTOMT[2] address (0x0A) to HIGH and applied to the DAC output when it sees 1024 consecutive zeros
at its input.
If at any time there is a non-zero sample value, the DAC will be un-muted, and the 1024 count will be reinitialized
to zero.
11.5.3. DAC Sampling / Oversampling rate, Polarity, DAC Volume control and Digital Pass-
through
The sampling rate of the DAC is determined entirely by the frequency of its input clock and the oversampling rate
setting. The oversampling rate of the DAC can be changed to 64x or 128x. In the 128x oversampling mode it
gives an improved audio performance at slightly higher power consumption. Because the additional supply
current is only 1mA, in most applications the 128x oversampling is preferred for maximum audio performance.
The polarity of the DAC output signal can be changed as a feature sometimes useful in management of the audio
phase. This feature can help minimize any audio processing that may be otherwise required as the data are
passed to other stages in the system.
The effective output audio volume of the DAC can be changed using the digital volume control feature. This
processes the output of the DAC to scale the output by the amount indicated in the volume register setting.
Included is a “digital mute” value which will completely mute the signal output of the DAC. The digital volume
setting can range from 0dB through -127dB in 0.5dB steps.
Digital audio pass-through allows the output of the ADC to be directly sent to the DAC as the input signal to the
DAC for DAC output. In this mode of operation, the external digital audio signal for the DAC will be ignored. The
pass-through function is useful for many test and application purposes, and the DAC output may be utilized in any
way that is normally supported for the DAC analog output signals.
11.5.4. Hi-Fi DAC De-Emphasis and Gain Control
The NAU8812 has Hi-Fi DAC gain control for signal conditioning. The level of attenuation for an eight-bit code X
is given by:
0.5 × (X-255) dB
for 1 ≤ X ≤ 255;
MUTE for X = 0
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It includes on-chip digital de-emphasis and is available for sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The
digital de-emphasis can be enabled by setting DEEMP[5:4] address (0x0A) bits depending on the input sample
rate. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis
equalization as a means of noise reduction. The DAC output can be inverted (phase inversion) by setting
DACPL[1:0] address (0x0A) to HIGH, non-inverted output is set by default.
11.5.5. Digital DAC Output Peak Limiter
Output Peak-Limiters reduce the dynamic range by ensuring the signal will not exceed a certain threshold, while
maximizing the RMS of the resulted audio signal, and minimizing audible distortions. NAU8812 has a digital
output limiter function. In the figure below, the upper graph shows the envelope of the input/output signals and
the lower graph shows the gain characteristic. The limiter has a programmable threshold, DACLIMTHL[6:4]
address (0x19), which ranges from -1dB to -6dB in 1dB increments. The digital peak limiter seeks to keep the
envelope of the output signal within the target threshold +/- 0.5dB. The attack and decay rates programmed in
registers DACLIMATK[3:0] address (0x18) and DACLIMDCY[7:4] address (0x18) specify how fast the digital peak
limiter decrease and increase the gain, respectively, in response to the envelope of the output signal falling
outside of this range. In normal operation LIMBST=000 signals below this threshold are unaffected by the limiter.
DAC Input
Data
Threshold
-1dB
DAC Output
Signal
0dB
Digital Gain
-0.5dB
-1dB
Figure 18: DAC Digital Limiter Control
11.5.6. Volume Boost
The limiter has programmable upper gain, which boosts signals below the threshold to compress the dynamic
range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost
capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the DACLIMBST[3:0] register bits.
The output limiter volume boost can also be used as a stand-alone digital gain boost when the limiter is disabled.
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11.6. ANALOG OUTPUTS
The NAU8812 features two different types of outputs, a single-ended MONO output (MOUT) and a differential
speaker outputs (SPKOUT+ and SPKOUT-). The speaker amplifiers designed to drive a load differentially; a
configuration referred to as Bridge-Tied Load (BTL).
MOUTBST[3]
(0x31)
VDDSPK
Output from
Auxiliary Amplifier
MOUTMXEN[3]
(0x03)
DACOUT[0]
(0x38)
DAC Output
MOUT
MONO
MIXER
MOUTBST GAIN DC output
0
1
1.0x 1.0 x VREF
1.5x 1.5 x VREF
-10dB or +0dB
SIDETONE
Output from PGA Boost
VSSSPK
VDDSPK
Zero Cross
Detection
-1
SPKOUT-
SPEAKER
MIXER
SPKBST GAIN
DC output
1.0 x VREF
1.5 x VREF
0
1
1.0x
1.5x
SPKOUT+
-10dB or 0dB
SPKMXEN[2]
(0x03)
Zero Cross
Detection
Buffer
SPKBST[2]
(0x31)
SPKVOL[5:0]
(0x36)
VSSSPK
Figure 19: Speaker and MONO Analogue Outputs
Important: For analog outputs depopping purpose, when powering up speakers, headphone,
AUXOUTs, certain delays are generated after enabling sequence. However, the delays are created
by MCLK and sample rate register. For correct operation, sending I2S signal no earlier than 250ms
after speaker or headphone enabled and MCLK appearing
11.6.1.
Speaker Mixer Outputs
The speaker amplifiers are designed to drive a load differentially; a configuration referred to as Bridge-Tied Load
(BTL). The differential speaker outputs can drive a single 8Ω speaker or two headphone loads of 16Ω or 32Ω or
a line output. Driving the load differentially doubles the output voltage. The output of the speaker can be
manipulated by changing attenuation and the volume (loudness of the output signal).
The output stage is powered by the speaker supply, VDDSPK, which are capable of driving up to 1.5VRMS signals
(equivalent to 3VRMS into a BTL speaker). The speaker outputs can be controlled and can be muted individually.
The output pins are at reference DC level when the output is muted.
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Bit(s)
Addr
0x03
Parameter
Programmable Range
0 – Disabled
1 – Enabled
SPKMXEN[2]
Speaker Mixer enable
Speaker positive terminal
enable
0 – Disabled
1 – Enabled
PSPKEN[5]
NSPKEN[6]
SPKATT[1]
SPKBST[2]
SPKGAIN[5:0]
SPKMT[6]
0x03
0x03
0x28
0x31
0x36
0x36
Speaker negative terminal
enable
0 – Disabled
1 – Enabled
0 - 0dB
1 - -10dB
Speaker output attenuation
Speaker output Boost
Speaker output Volume
Speaker output Mute
0 – (1.0x VREF) Boost
1- (1.5 x VREF) Boost
Range: -57dB to +6dB @ 6dB increment
0 – Speaker Enabled
1 – Speaker Muted
Table 17: Speaker Output Controls
11.6.2. MONO Mixer Output
The single ended output can drive headphone loads of 16Ω or 32Ω or a line output. The MOUT can be
manipulated by changing attenuation and the volume (loudness of the output signal).
The output stage is powered by the speaker supply, VDDSPK, which are capable of driving up to 1.5VRMS signals.
The MONO output can be enabled for signal output or muted. The output pins are at reference DC level when the
output is muted.
Bit(s)
Addr
0x03
Parameter
Programmable Range
0 – Disabled
1 – Enabled
MOUTMXEN[3]
MONO mixer enable
0 – Disabled
1 – Enabled
MOUTEN[7]
MOUTATT[2]
MOUTBST[3]
MOUTMXMT[6]
MOUTMT[4]
0x03
0x28
0x31
0x38
0x45
MONO output enable
MONO output attenuation
MONO output boost
0 - 0dB
1 - -10dB
0 – (1.0x VREF) Boost
1- (1.5 x VREF) Boost
0 – MONO Mixer Normal Mode
1 – MONO Mixer Muted
MONO Output Mixer Mute
MONO Output Mute
0 – MONO Output Normal Mode
1 – MONO Output Muted
Table 18: MONO Output Controls
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11.6.3. Unused Analog I/O
AUX
30k
AUXEN[6]
(0x01)
SMOUT[3]
(0x4F)
MOUTBST[3] = 0
(0x31)
30k
MIC-
1K
NMICPGA[1]
(0x2C)
MOUT
30K
40k
MIC+
MOUTBST[3] = 1
(0x31)
PMICPGA[0]
(0x2C)
SPSPK[4]
(0x4F)
1.0 x VREF
1K
VREF
SPKOUT+
30K
SBUFL[6]
(0x4F)
IOBUFEN[2]
(0x01)
SNSPK[5]
(0x4F)
SBUFH[7]
(0x4F)
DCBUFEN[8]
(0x01)
1K
SPKOUT-
1.5 x VREF
30K
AOUTIMP[0]
(0x31)
R
R
Figure 20: Tie-off Options for the Speaker and MONO output Pins
In audio and voice systems, any time there is a sudden change in voltage to an audio signal, an audible pop or
click
sound may be the result. Systems that change inputs and output configurations dynamically, or which are
required to manage low power operation, need special attention to possible pop and click situations. The
NAU8812 includes many features which may be used to greatly reduce or eliminate pop and click sounds. The
most common cause of a pop or click signal is a sudden change to an input or output voltage. This may happen
in either a DC coupled system, or in an AC coupled system.
The strategy to control pops and clicks is similar for either a DC coupled system, or an AC coupled system. The
case of the AC coupled system is the most common and the more difficult situation, and therefore, the AC
coupled case will be the focus for this information section. When an input or output pin is being used, the DC
level of that pin will be very close to half of the VDDA voltage that is present on the VREF pin. The only exception
is that when outputs are operated in the 5-Volt mode known as the 1.5x boost condition, then the DC level for
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those outputs will be equal to 1.5xVREF. In all cases, any input or output capacitors will become charged to the
operating voltage of the used input or output pin. The goal to reduce pops and clicks is to insure that the charge
voltage on these capacitors does not change suddenly at any time.
When an input or output is in a not-used operating condition, it is desirable to keep the DC voltage on that pin at
the same voltage level as the DC level of the used operating condition. This is accomplished using special
internal DC voltage sources that are at the required DC values. When an input or output is in the not-used
condition, it is connected to the correct internal DC voltage as not to have a pop or click. This type of connection
is known as a “tie-off” condition.
Two internal DC voltage sources are provided for making tie-off connections. One DC level is equal to the VREF
voltage value, and the other DC level is equal to 1.5x the VREF value. All inputs are always tied off to the VREF
voltage value. Outputs will automatically be tied to either the VREF voltage value or to the 1.5xVREF value,
depending on the value of the “boost” control bit for that output. That is to say, when an output is set to the 1.5x
gain condition, then that same output will automatically use the 1.5xVREF value for tie-off in the not-used
condition. The input pull-ups are connected to IOBUFEN[2] address (0x01) buffer with a voltage source (VREF).
The output pull-ups can be connected two different buffers depending on the voltage source. IOBUFEN[2]
address (0x01) buffer is enabled if the voltage source is (VREF) and DCBUFEN[8] address (0x01) buffer is
enabled if the voltage source is (1.5 x VREF). IOBUFEN[2] address (0x01) buffer is shared between input and
output pins.
To conserve power, these internal voltage buffers may be enabled/disabled using control register settings. To
better manage pops and clicks, there is a choice of impedance of the tie-off connection for unused outputs. The
nominal values for this choice are 1kΩ and 30kΩ. The low impedance value will better maintain the desired DC
level in the case when there is some leakage on the output capacitor or some DC resistance to ground at the
NAU8812 output pin. A tradeoff in using the low-impedance value is primarily that output capacitors could change
more suddenly during power-on and power-off changes.
Automatic internal logic determines whether an input or output pin is in the used or un-used condition. This logic
function is always active. An output is determined to be in the un-used condition when it is in the disabled
unpowered condition, as determined by the power management registers. An input is determined to be in the un-
used condition when all internal switches connected to that input are in the “open” condition.
11.7. GENERAL PURPOSE I/O
The CSb/GPIO pin can be configured in two ways, chip select for SPI interface and general purpose GPIO.
Therefore, the general-purpose configuration is only available in the 2-Wire interface mode, which is configured
by setting GPIOSEL[2:0] address (0x08) to 001 – 101. “000” configures the pin to be a chip select for SPI mode.
The CSb/GPIO pin is not available in the SPI interface mode. When the pin is configured as an input, it can be
used as chip select signal for SPI interface or for jack detect. When the pin is configured as output, it can be used
for signaling analog mute, temperature alert, PLL frequency output, and PLL frequency lock. The CSb/GPIO pin
can also output the master clock through a PLL or directly. The path also included a divider for different clocks
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NAU8812
needed in the system. Note that SCLKEN must be enabled when using the Jack Detect function.
Addr
0x08
0x07
D8
0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
Default
0x000
GPIOPLL[1:0]
GPIOPL
GPIOSEL[2:0]
0
0
0
0
0
SMPLR[2:0]
SCLKEN 0x000
Table 19: General Purpose Control
11.7.1. Slow Timer Clock
An internal Slow Timer Clock is supplied to automatically control features that happen over a relatively long period
of time, or time-spans. This enables the NAU8812 to implement long time-span features without any
host/processor management or intervention.
The Slow Timer Clock supports two features automatic time out for the zero-crossing holdoff of PGA volume
changes, and timing for debouncing of the mechanical jack detection feature. If either feature is required, the
Slow Timer Clock must be enabled. The Slow Timer Clock is initialized in the disabled state.
The Slow Timer Clock rate is derived from MCLK using an integer divider that is compensated for the sample rate
as indicated by the register address (0x07). If the sample rate register value precisely matches the actual
sample rate, then the internal Slow Timer Clock rate will be a constant value of 128ms. If the actual sample rate
is, for example, 44.1kHz and the sample rate selected in register 0x07 is 48kHz, the rate of the Slow Timer Clock
will be approximately 10% slower in direct proportion of the actual vs. indicated sample rate. This scale of
difference should not be important in relation to the dedicated end uses of the Slow Timer Clock.
11.7.2. Jack Detect
Jack detect is a specific GPIO function. Jack detect is only available in 2-Wire mode only. Jack detect is selected
by setting GPIOSEL[2:0] address (0x08) to “001”. The GPIOPL[3] bit address (0x08) inverts the CSb/GPIO pin
when set to 1. The table below shows all the combinations for jack insert detects.
The CSb/GPIO pin has an internal de-bounce circuit so that when the jack detect feature is enabled it does not
toggle multiple times due to input glitches. Slow clock mode must be enabled when using jack insert detect by
setting SCLKEN[0] address (0x07).
NSPKEN/
PSPKEN
Speaker MONO output
GPIOPL CSb/GPIO
MOUTEN
Enabled
Enabled
0
0
1
1
0
1
0
1
1
X
X
1
X
1
1
X
Yes
No
No
Yes
No
Yes
Yes
No
Table 20: Jack Insert Detect mode
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NAU8812
Bit(s)
Addr
0x08
Parameter
Programmable Range
0 - CSb Input
1 - Jack Detect
2 - Temperature OK
3 - AMUTE Active
4 - PLL Frequency Output
5 - PLL Lock (0- Locked, 1 – Not
Locked)
GPIOSEL[2:0]
GPIO select
6 - HIGH
7 - LOW
0 – Non- Inverted
1 – Inverted
GPIOPL[3]
0x08
0x08
GPIO polarity
0 - Divide by 1
1 - Divide by 2
2 - Divide by 3
3 - Divide by 4
0 – Muted
1 – Enabled
0 – Muted
GPIOPLL[4:5]
GPIO PLL divider
PSPKEN[5]
NSPKEN[6]
0x03
0x03
Speaker positive terminal enable
Speaker negative terminal
enable
1 – Enabled
0 – Muted
1 – Enabled
Period 221 * MCLK
MOUTEN[7]
SCLKEN[0]
0x03
0x07
MONO Output enable
Slow clock enable
Table 21: Jack Insert Detect controls
11.7.3. Thermal Shutdown
The device contains an on-chip temperature sensor that senses the temperature inside the package. By enabling
the temperature sensor interrupt in GPIOSEL[2:0] address (0x08), an interrupt will be generated if the
temperature reaches a threshold of approximately 125°C. This facilitates control of the temperature should the
device get close to the junction temperature. Note that there is no filtering associated with this temperature alarm
since the package has an intrinsic thermal time constant. The thermal temperature is enabled by setting TSEN[1]
address (0x31).
Bit(s)
Addr
0x31
Parameter
Programmable Range
0: Thermal Shutdown Disable
1: Thermal Shutdown Enable
TSEN[1]
Temperature Sense Enable
Table 22: Thermal Shutdown
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NAU8812
11.8. CLOCK GENERATION BLOCK
ADCOS[3]
(0x0E)
MCLKSEL[7:5]
(0x06)
fPLL
ADC
PLLMCLK[4]
(0x24)
f/N
f/N
IMCLK
f1
MCLK
f2
f/N
DAC
PLL1
R=f2/f1
f/4
f/2
DACOS[3]
(0x0A)
CLKM[8]
(0x06)
PLL BLOCK
IMCLK/
N
IMCLK/
256
BCLKSEL[4:2]
(0x06)
CLKIOEN[0]
(0x06)
f/N
FS
BCLK
Digital Audio
Interface
…
GPIO1
/CSb
GPIO1PLL[5:4]
(0x08)
GPIO1SEL[2:0]
(0x08)
Figure 21: PLL and Clock Select Circuit
The NAU8812 has two basic clock modes that support the ADC and DAC data converters. It can accept external
clocks in the slave mode, or in the master mode, it can generate the required clocks from an external reference
frequency using an internal PLL (Phase Locked Loop). The internal PLL is a fractional type scaling PLL, and
therefore, a very wide range of external reference frequencies can be used to create accurate audio sample rates.
Separate from this ADC and DAC clock subsystem, audio data are clocked to and from the NAU8812 by means
of the control logic described in the Digital Audio Interfaces section. The Frame Sync (FS) and Bit Clock (BCLK)
pins in the Digital Audio Interface manage the audio bit rate and audio sample rate for this data flow.
It is important to understand that the Digital Audio Interface does not determine the sampling rate for the ADC and
DAC data converters, and instead, this rate is derived exclusively from the Internal Master Clock (IMCLK). It is
therefore a requirement that the Digital Audio Interface and data converters be operated synchronously, and that
the FS, BCLK, and IMCLK signals are all derived from a common reference frequency. If these three clocks
signals are not synchronous, audio quality will be reduced.
The IMCLK is always exactly 256 times the sampling rate of the data converters. IMCLK is output from the
Master Clock Prescaler. The prescaler reduces by an integer division factor the input frequency input clock. The
source of this input frequency clock is either the external MCLK pin, or the output from the internal PLL Block.
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NAU8812
Addr
0x01
0x06
0x07
0x24
0x25
0x26
0x27
D8
D7
0
D6
D5
D4
D3
D2
D1
0
D0
REFIMP
Default
DCBUFEN
AUXEN
PLLEN
MICBIASEN ABIASEN IOBUFEN
BCLKSEL[2:0]
CLKM
MCLKSEL[2:0]
CLKIOEN 0x140
SCLKEN 0x000
0x008
0
0
0
0
0
0
0
0
0
0
0
0
SMPLR[2:0]
PLLN[3:0]
PLLMCLK
PLLK[23:18]
0x00C
PLLK[17:9]
PLLK[8:0]
0x093
0x0E9
Table 23: Registers associated with PLL
In Master Mode, the IMCLK signal is used to generate FS and BCLK signals that are driven onto the FS and
BCLK pins and input to the Digital Audio Interface. FS is always IMCLK/256 and the duty cycle of FS is
automatically adjusted to be correct for the mode selected in the Digital Audio Interface. The frequency of BCLK
may optionally be divided to optimize the bit clock rate for the application scenario.
In Slave Mode, there is no connection between IMCLK and the FS and BCLK pins. In this mode, FS and BLCK
are strictly input pins, and it is the responsibility of the system designer to insure that FS, BCLK, and IMCLK are
synchronous and scaled appropriately for the application.
11.8.1. Phase Locked Loop (PLL) General description
The PLL may be optionally used to multiply an external input clock reference frequency by a high resolution
fractional number. To enable the use of the widest possible range of external reference clocks, the PLL block
includes an optional divide-by-two prescaler for the input clock, a fixed divide-by-four scaler on the PLL output,
and an additional programmable integer divider that is the Master Clock Prescaler.
The high resolution fraction for the PLL is the ratio of the desired PLL oscillator frequency (f2), and the reference
frequency at the PLL input (f1). This can be represented as R = f2/f1, with R in the form of a decimal number:
xy.abcdefgh. To program the NAU8812, this value is separated into an integer portion (“xy”), and a fractional
portion, “abcdefgh”. The fractional portion of the multiplier is a value that when represented as a 24-bit binary
number (stored in three 9-bit registers on the NAU8812), very closely matches the exact desired multiplier factor.
To keep the PLL within its optimal operating range, the integer portion of the decimal number (“xy”), must be any
of the following decimal values: 6, 7, 8, 9, 10, 11, or 12. The input and output dividers outside of the PLL are
often helpful to scale frequencies as needed to keep the “xy” value within the required range. Also, the optimum
PLL oscillator frequency is in the range between 90MHz and 100MHz, and thus, it is best to keep f2 within this
range.
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NAU8812
In summary, for any given design, choose:
Equations
Description
Notes
IMCLK = (256) * (desired codec
sample rate)
IMCLK = desired Master Clock
The integer values for D and P
are chosen to keep the PLL in its
optimal operating range. It may
be best to assign initial values of
1 to both D and P, and then by
inspection, determine if they
should be a different value.
where P is the Master Clock divider
integer value;
optimal f2: 90MHz< f2 <100MHz
f2 = (4 * P * IMCLK)
where D is the PLL Prescale factor of 1,
or 2, and MCLK is the frequency at the
MCLK pin
f1 = (MCLK / D)
R = f2 / f1 = xy.abcdefgh decimal
value
which is the fractional frequency
multiplication factor for the PLL
truncated integer portion of the R value
and limited to decimal value 6, 7, 8, 9,
10, 11, or 12
N = xy
rounded to the nearest whole integer
value then converted to a binary 24-bit
value
K = (224) * (0.abcdefgh)
Table 24: Registers associated with PLL
11.8.2. CSB/GPIO as PLL out (fPLL
)
CSB/GPIO is a multi-function pin that may be used for a variety of purposes. If not required for some other
purpose, this pin may be configured to output the clock frequency from the PLL subsystem. This is the same
frequency that is available from the PLL subsystem as the input to the Master Clock Prescaler. This frequency
may be optionally divided by an additional integer factor of 2, 3, or 4, before being output on GPIO.
11.8.3. Phase Locked Loop (PLL) Design Example
In an example application, a desired sample rate for the DAC is known to be 48.000kHz. Therefore, it is also
known that the IMCLK rate will be 256fs, or 12.288MHz. Because there is a fixed divide-by-four scaler on the PLL
output, then the desired PLL oscillator output frequency will be 49.152MHz.
In this example system design, there is already an available 12.000MHz clock from the USB subystem. To
reduce system cost, this clock will also be used for audio. Therefore, to use the 12MHz clock for audio, the
desired fractional multiplier ratio would be R = 49.152/12.000 = 4.096. This value, however, does not meet the
requirement that the “xy” whole number portion of the multiplier be in the inclusive range between 6 and 12. To
meet the requirement, the Master Clock Prescaler can be set for an additional divide-by-two factor. This now
makes the PLL required oscillator frequency 98.304 MHz, and the improved multiplier value is now R =
98.304/12.000 = 8.192.
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NAU8812
To complete this portion of the design example, the integer portion of the multiplier is truncated to the value, 8 and
the fractional portion is multiplied by 224, as to create the needed 24-bit binary fractional value. The calculation for
this is: (224)(0.192) = 3221225.472.
It is best to round this value to the nearest whole value of 3221225, or hexadecimal 0x3126E9.
Below are additional examples of results for this calculation applied to commonly available clock frequencies and
desired IMCLK 256fs sample rates.
Desired
Output
(MHz)
Input
Frequency
(f1)
MCLK
Divider
bits
Actual Register Setting
MCLK
(MHz)
f2
N
(Hex)
R
K (Hex)
(MHz)
PLLK[23:18] PLLK[17:9] PLLK[8:0]
12.0
12.0
14.4
14.4
19.2
19.2
19.8
19.8
24.0
24.0
26.0
26.0
11.28960
12.28800
11.28960
12.28800
11.28960
12.28800
11.28960
12.28800
11.28960
12.28800
11.28960
12.28800
MCLK/1
MCLK/1
MCLK/1
MCLK/1
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK/2
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
90.3168
98.3040
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
fPLL/2
7.526400
8.192000
6.272000
6.826667
9.408000
10.240000
9.122909
9.929697
7.526400
8.192000
6.947446
7.561846
7
8
86C226
3126E9
45A1CA
D3A06D
6872B0
3D70A3
1F76F8
EE009E
86C226
3126E9
F28BD4
8FD526
21
0C
11
34
1A
0F
07
3B
21
0C
3C
23
161
93
26
E9
6
D0
1CA
6D
B0
6
1D0
39
9
10
9
B8
A3
1BB
100
161
93
F8
9
9E
7
26
8
E9
6
145
1EA
1D4
126
7
Table 25: PLL Frequency Examples
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NAU8812
11.9. CONTROL INTERFACE
The NAU8812 features two serial bus interfaces SPI and 2-Wire that provide access to the control registers. The
MODE pin in conjunction with SPIEN[8] (address 0x49) as shown in the following Table selects the control
interfaces. 2-Wire interface is compatible with industry I2C serial bus protocol using a bidirectional data signal
(SDIO) and a clock signal (SCLK). SPI interface is also compatible with other industry interfaces allowing
operation on a simple 3-wire or 4-wire bus. Table below describes the selection of the protocol modes.
SPIEN[8] Bit
MODE Pin
Description
(0x49)
0
1
0
2-Wire Interface (Write/Read)
SPI Interface 16-bit (Write ONLY)
0
1
SPI Interface 32-bit (Read)
SPI Interface 24-bit (Write)
(SSOP 28-Pin Write ONLY,
QFN 32-Pin Write/Read)
x
Table 26: Control Interface Selection
11.9.1.
SPI Serial Control
The Serial Peripheral Interface (SPI) is one of the widely accepted communication interfaces implemented in
Nuvoton’s Audio CODEC portfolio. SPI is a software protocol allowing operation on a simple 3-wire or 4-wire bus
where the data is transferred MSB first. NAU8812 has two different SPI architectures
16-bit write ONLY (default)
24-bit write with 32-bit read
The SPI interface consists of a clock (SCLK), chip select (CSb), serial data input (SDIO), and serial data output
(SO) to configure all the internal register contents. The SO Pin is ONLY available on the 32-Pin QFN package.
SCLK is static, allowing the user to stop the clock and then start it again to resume operations where it left off.
The 24-bit write operation consists of 8-bits of device address, 7-bits of control register address, and 9-bits of data.
The 32-bit read operation consists of 8-bits of device address, 8-bits of control register address, and 16-bits of
data of which 9 LSB bits are actual data bits and the rest are 0’s.
The device address
Write operation is 00010000b = 10h
Read operation is 00100000b = 20h
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NAU8812
11.9.1.1. 16-bit Write Operation (default)
The default control interface architecture is SPI 16-bit. This interface architecture consists of 7-bits of control
register address, and 9-bits of control register data. The MODE Pin set to “1” (HIGH) selects the SPI 16-bit. In
this mode, the user can only do write operation. The write operation requires a valid control register address,
then a valid 9-bit Data Byte and the finally to complete the transaction the CSb has to transition from LOW to
HIGH to latch the last 9-bits (data).
CBb/GPIO
SCLK
SDIO
A6 A5 A4 A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Control Register
9-bit Data Byte
Address
Figure 22: Register write operation using a 16-bit SPI Interface
11.9.1.2. 24-bit Write Operation
The 24-bit write operation is a three-byte operation. To start the operation the host controller transitions the CSb
from HIGH to LOW. The host micro-controller sends valid device address, then a valid control register address
following Data Byte. Finally the interface is terminated by toggling CSb pin from LOW to HIGH. The write
operation will accept multiple 9-bit DATA blocks, which will be written in to sequential address beginning with the
address, specified in the control register address. Steps below show the procedure to enter and exit SPI 24-bit
write and 32-bit read
Procedure to enter the 24-bit SPI interface
Set the Mode pin to “0” (LOW)
Use the 2-wire write architecture to write to register address 0x049 SPIEN[8] = “1” (HIGH)
OR
Set the Mode pin to “1” (HIGH)
Use the 16-bit write architecture to write to register address 0x049 SPIEN[8] = “1” (HIGH)
Procedure to exit the 24-bit SPI interface
Use the 24-bit write architecture to write to register address 0x49 SPIEN[8] = “0” (LOW)
Depending on the state of the Mode pin, control interface will be selected
o
o
Mode Pin = “0” for I2C
Mode Pin = “1” for 16-bit SPI
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NAU8812
CBb/GPIO
SCLK
SDIO
0
0
0
1
0
0
0
0
A6 A5 A4 A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Control Register
9-bit Data Byte
Address
Device Address = 10h
Figure 23: Register Write operation using a 24-bit SPI Interface
11.9.1.3.
32-bit Read Operation
The 32-bit read operation is a four-byte operation with 2-bytes of data. The transmission starts with the falling
edge of the CSb line and ends with the rising edge of the CSb. The host micro-controller sends device address,
control register address byte following 2 bytes of data. The device can receive more than one byte of data by
continuously clocking. Note after reaching the maximum address the internal pointer “rolls over” to address 0x00
(hex). The device will output a dummy byte [0x00] when locations without register assignments are within the
sequence.
CBb/GPIO
SCLK
SDIO
SO
0
0
1
0
0
0
0
0
A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
D8 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte 1
Data Byte 2
Control Register
Address
Device Address = 20h
Figure 24: Register Read operation through a 32-bit SPI Interface
11.9.2.
2-WIRE Serial Control Mode (I2C Style Interface)
The NAU8812 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the receiver. Therefore, the 2-Wire operates as slave
interface. All communication over the 2-Wire interface is conducted by sending the MSB of each byte of data first.
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NAU8812
11.9.2.1.
2-WIRE Protocol Convention
All 2-Wire interface operations must begin with a START condition, which is a HIGH to LOW transition of SDIO
while SCLK is HIGH. All 2-Wire and all interface operations are terminated by a STOP condition, which is a LOW
to HIGH transition of SDIO while SCLK is HIGH. A STOP condition at the end of a read or write operation places
the device in standby mode. An acknowledge (ACK), is a software convention used to indicate a successful data
transfer. The transmitting device, either master or slave, releases the SDIO bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDIO line LOW to acknowledge the reception of the eight bits
of data.
Following a START condition, the master must output a device address byte. The 7-MSB bits “0011010” are the
device address. The LSB of the device address byte is the R/W bit and defines a read (R/W = 0) or write (R/W =
1) operation. When this, R/W, bit is a “1”, then a read operation is selected and when “0” the device selects a
write operation. The device outputs an acknowledge LOW for a correct device address and HIGH for an incorrect
device address on the SDIO pin.
9th
Clock
SCLK
SCLK
SDIO
SCLK
SDIO
SDIO
Receive
ACK
SDIO
Transmit
START
STOP
Figure 27: Valid STOP Condition
Figure 25: Valid START Condition
Figure 26: Valid Acknowledge
Device
R/W
0
0
1
1
0
1
0
Address Byte
Control
Address Byte
Write - D8
Read - 0
A6
D7
A5
D6
A4
D5
A3
D4
A2
D3
A1
D2
A0
D1
Data Byte
D0
Figure 28: Slave Address Byte, Control Address Byte, and Data Byte
11.9.2.2.
2-WIRE Write Operation
A Write operation consists of a two-byte instruction followed by one or more Data Bytes. A Write operation
requires a START condition, followed by a valid device address byte, a valid control address byte, data byte(s),
and a STOP condition. After each three bytes sequence, the NAU8812 responds with an ACK and the 2-Wire
interface enters a standby state.
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NAU8812
SCLK
SDIO
0
0
1
1
0
1
0
0
A6
A0 D8
A5 A4 A3 A2 A1
D7 D6 D5
D4 D3 D2 D1 D0
S
T
O
P
A
C
S
T
A
A
C
K
A
C
K
K
R
T
Device Address
=34h
R/W
Control Register Address
9-bit Data Byte
Figure 29: Byte Write Sequence
11.9.2.3.
2-WIRE Read Operation
A Read operation consists of a three-byte instruction followed by one or more Data Bytes. The master initiates
the operation issuing the following sequence: a START condition, device address byte with the R/W bit set to “0”,
a control address byte, a second START condition, and a second device address byte with the R/W bit set to “1”.
After each of the three bytes, the NAU8812 responds with an ACK. Then the NAU8812 transmits Data Bytes as
long as the master responds with an ACK during the SCLK cycle following the ninth bit of each byte. The master
terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte.
After reaching the memory location 7Fh the pointer “rolls over” to 00h, and the device continues to output data for
each ACK received.
SCLK
0
0
1
1
0
1
0
0
A6 A5 A4 A3 A2 A1 A0
Control Register Address
0
0
1
1
0
1
0
1
0
S
S
A
C
K
A
C
K
A
C
K
2ND Device Address = 35h
T
A
R
T
T
A
R
T
Device Address = 34h
0
0
0
0
0
0
D8
D6 D5 D4 D3 D2 D1 D0
D7
0
A
C
K
N
A
C
K
S
T
O
P
16-bit Data
Figure 30: 2-Wire Read Sequence
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NAU8812
11.10. DIGITAL AUDIO INTERFACES
NAU8812 only uses the Left channel to transfer data in normal mode. It supports an independent digital interface
for voice and audio. The digital interface is used to input digital data to the DAC, or output digital data from the
ADC. The digital interface can be configured to Master mode or Slave mode.
Master mode is configured by setting CLKIOEN[0] address (0x06) bit to HIGH. The main clock (MCLK) of the
digital interface is provided from an external clock either from a crystal oscillator or from a microcontroller. With
an appropriate MCLK, the device generates bit clock (BCLK) and frame sync (FS) internally in the master mode.
By generating the bit clock and frame sync internally, the NAU8812 has full control of the data transfer.
Slave mode is configured by setting CLKIOEN[0] address (0x06) bit to LOW. In this mode, an external controller
has to supply the bit clock and the frame sync. The NAU8812 uses ADCOUT, DACIN, FS, and BCLK pins to
control the digital interface. Care needs to be exercised when designing a system to operate the NAU8812 in this
mode as the relationship between the sample rate, bit clock, and frame sync needs to be controlled by other
controller. In both modes of operation, the internal MCLK and MCLK prescalers determine the sample rate for the
DAC and ADC.
The output state of the ADCOUT pin by default is pulled-low. Depending on the application, the output can be
configured to be Hi-Z, pull-low, pull-high, Low or High. To configure the output, three different bits have to be set.
First the output switched to the mask by setting PUDOEN[5] address (0x3C), then the mask has to be enabled be
setting PUDPE[4] address (0x3C) and finally output state select pulled up or down by PUDPS[3] address (0x3C).
Six different audio formats are supported by NAU8812 with MSB first and they are as follows.
AIFMT[4]
Addr: (0x04)
AIFMT[3]
Addr: (0x04)
PCMTSEN[8]
Addr: (0x3C) Addr: (0x3C)
PCMB[1]
PCM Mode
PCM B
0
0
0
1
1
1
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
Right Justified
Left Justified
I2S
PCM A
PCM Time Slot
Table 27: Standard Interface modes
Addr
0x04
0x06
0x3B
D8
D7
D6
WLEN[1:0]
MCLKSEL[2:0]
D5
D4
AIFMT[1:0]
BCLKSEL[2:0]
TSLOT[8:0]
D3
D2
D1
D0
0
Default
0x050
BCLKP
CLKM
FSP
DACPHS ADCPHS
0
CLKIOEN 0x140
0x000
0x3C PCMTSEN TRI PCM8BIT PUDOEN PUDPE
PUDPS LOUTR PCMB TSLOT[9:8] 0x000
Table 28: Audio Interface Control Registers
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NAU8812
11.10.1. Right Justified audio data
In right justified interface (normal mode), the left channel serial audio data is synchronized with the frame sync.
Left channel data is transferred during the HIGH frame sync. The MSB data is sampled first. The data is latched
on the last rising edge of BCLK before frame sync transition (FS). The LSB is aligned with the falling edge of the
frame sync signal (FS). Right justified format is selected by setting AIFMT[1:0] address (0x04) to “00” binary in
conjunction with PCMTSEN[8] address (0x3C) set to LOW.
FS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
DACIN/
ADCOUT
1
2
N-1
N
MSB
LSB
Figure 31: Right Justified Audio Interface (Normal Mode)
NAU8812 features a special mode where the device outputs Left channel data to both Left and Right channels.
This is accomplished by setting LOUTR[2] address (0x3C) to “1”
FS
BCLK
LEFT CHANNEL
RIGHT CHANNEL
ADCOUT
1
2
N-1
N
1
2
N-1
N
MSB
LSB
MSB
LSB
Figure 32: Right Justified Audio Interface (Special mode)
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11.10.2. Left Justified audio data
In Left justified interface (normal mode), the left channel serial audio data is synchronized with the frame sync.
Left channel data is transferred during the HIGH frame sync. The MSB data is sampled first and is available on
the first rising edge of BCLK following a frame sync transition (FS). Left justified format is selected by setting
AIFMT[1:0] address (0x04) to “01” binary in conjunction with PCMTSEN[8] address (0x3C) set to LOW.
FS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
DACIN/
ADCOUT
1
2
N-1
N
MSB
LSB
Figure 33: Left Justified Audio Interface (Normal Mode)
NAU8812 features a special mode where the device outputs Left channel data to both Left and Right channels.
This is accomplished by setting LOUTR[2] address (0x3C) to “1”
FS
BCLK
LEFT CHANNEL
RIGHT CHANNEL
ADCOUT
1
2
N-1
N
1
2
N-1
N
MSB
LSB
MSB
LSB
Figure 34: Left Justified Audio Interface (Special mode)
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11.10.3. I2S audio data
In I2S interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left
channel data is transferred during the LOW frame sync. The MSB data is sampled first. The data is latched on
the second rising edge of BCLK following a frame sync transition (FS). I2S format is selected by setting
AIFMT[1:0] address (0x04) to “10” binary in conjunction with PCMTSEN[8] address (0x3C) set to LOW.
FS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
DACIN/
ADCOUT
1
2
N-1
N
MSB
LSB
1 BCLK
Figure 35: I2S Audio Interface (Normal Mode)
NAU8812 features a special mode where the device outputs Left channel data to both Left and Right channels.
This is accomplished by setting LOUTR[2] address (0x3C) to “1”
FS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
ADCOUT
1
2
N-1
N
1
2
N-1
N
MSB
LSB
MSB
LSB
1 BCLK
1 BCLK
Figure 36: I2S Audio Interface (Special mode)
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11.10.4. PCM audio data
In PCM interface (normal mode), the left channel serial audio data is synchronized with the frame sync. Left
channel data is transferred during the LOW frame sync. The MSB data is sampled first. The data is latched on
the second rising edge of BCLK following a frame sync transition (FS). PCM format is selected by setting
AIFMT[4:3] address (0x04) to “11” binary in conjunction with PCMTSEN[8] address (0x3C) set to LOW.
The digital data can be forced to appear on the right phase of the FS by setting ADCPHS[0] and DACPHS[1]
address (0x04) bits to HIGH respectively. The starting point of the right phase data depends on the word length
WLEN[6:5] address (0x04) after the frame sync transition (FS).
1 BCLK
FS
LEFT CHANNEL
BCLK
DACIN/
ADCOUT
1
2
N-1
N
MSB
LSB
Word Length, WLEN[6:5]
Figure 37: PCM Mode Audio Interface (Normal Mode)
NAU8812 features a special mode where the device outputs Left channel data to both Left and Right channels.
This is accomplished by setting LOUTR[2] address (0x3C) to “1”
1 BCLK
FS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
ADCOUT
1
2
N-1
LSB MSB
Word Length, WLEN[6:5]
N
1
2
N-1
N
MSB
LSB
Word Length, WLEN[6:5]
Figure 38: PCM Mode Audio Interface (Special mode)
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11.10.5. PCM Time Slot audio data
In PCM Time-Slot interface (normal mode), the left channel serial audio data is synchronized with the frame sync.
Left channel data is transferred during the LOW frame sync. The MSB data is sampled first. The starting point of
the timeslot is controlled by a 10-bit byte TSLOT[9:0] address (0x3B and 0x3C). The data is latched on the first
rising edge of BCLK following a frame sync transition (FS) providing PCM is in timeslot zero (TSLOT[9:0] = 000).
PCM Time-Slot format is selected by setting AIFMT[4:3] address (0x04) to “11” binary in conjunction with
PCMTSEN[8] address (0x3C) set to HIGH. The digital data can be forced to appear on the right phase of the FS
by setting ADCPHS[0] and DACPHS[1] address (0x04) bits to HIGH respectively. The starting point of the right
phase data depends on the word length WLEN[6:5] address (0x04) and timeslot assignment TSLOT[9:0] address
(0x3B and 0x3C) after the frame sync transition (FS). DACIN will return to the bus condition either on the
negative edge of BCLK during the LSB, or on the positive edge of BCLK following the LSB depending on the
setting of TRI[7] address (0x3C). Tri-stating on the negative edge allows the transmission of data by multiple
sources in adjacent timeslots without the risk of driver contention.
1 BCLK
FS
LEFT CHANNEL
BCLK
DACIN/
ADCOUT
1
2
N-1
N
MSB
LSB
Word Length, WLEN[6:5]
Figure 39: PCM Time Slot Mode (Time slot = 0) (Normal Mode)
NAU8812 features a special mode where the device outputs Left channel data to both Left and Right channels.
This is accomplished by setting LOUTR[2] address (0x3C) to “1”
1 BCLK
FS
LEFT CHANNEL
RIGHT CHANNEL
BCLK
ADCOUT
1
2
N-1
N
1
2
N-1
N
MSB
LSB MSB
LSB
Word Length, WLEN[6:5]
Word Length, WLEN[6:5]
Figure 40: PCM Time Slot Mode (Time slot = 0) (Special mode)
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11.10.6. Companding
Companding is used in digital communication systems to optimize signal-to-noise ratios with reduced data bit
rates, and make use of non-linear algorithms. NAU8812 supports two different types of companding A-law and µ-
law on both transmit and receive sides. A-law algorithm is used in European communication systems and µ-law
algorithm is used by North America, Japan, and Australia. This feature is enabled by setting DACCM[4:3]
address (0x05) or ADCCM[2:1] address (0x05) register bits. Companding converts 13 bits (µ-law) or 12 bits (A-
law) to 8 bits using non-linear quantization. The companded signal is an 8-bit word containing sign (1-bit),
exponent (3-bits) and mantissa (4-bits). As recommended by the G.711 standard (all 8-bits are inverted for µ-law,
all even data bits are inverted for A-law).
Setting CMB8[5] address 0x05 to 1 will cause the PCM interface to use 8-bit word length for data transfer,
overriding the word length configuration setting in WLEN[6:5] address 0x04.
Addr
D8
0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
Default
0x05
CMB8
DACCM[1:0]
ADCCM[1:0]
ADDAP
0x000
Table 29: Companding Control
The following equations for data compression (as set out by ITU-T G.711 standard):
µ-law (where µ=255 for the U.S. and Japan):
F(x) = ln( 1 + µ|x|) / ln( 1 + µ)
-1 ≤ x ≤ 1
A-law (where A=87.6 for Europe):
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NAU8812
11.11. POWER SUPPLY
This device has been designed to operate reliably using a wide range of power supply conditions and power-
on/power-off sequences. There are no special requirements for the sequence or rate at which the various power
supply pins change. Any supply can rise or fall at any time without harm to the device. However, pops and clicks
may result from some sequences. Optimum handling of hardware and software power-on and power-off
sequencing is described in more detail in the Power Up/Down Sequencing section of this document.
11.11.1. Power-On Reset
The NAU8812 does not have an external reset pin. The device reset function is automatically generated
internally when power supplies are too low for reliable operation. The internal reset is generated any time that
either VDDA or VDDC is lower than is required for reliable maintenance of internal logic conditions. The threshold
voltage for VDDA is approximately ~1.52Vdc and the threshold voltage for VDDC is approximately
~0.67Vdc. Note that these are much lower voltages than are required for normal operation of the chip. These
values are mentioned here as general guidance as to overall system design.
If either VDDA or VDDC is below its respective threshold voltage, an internal reset condition may be
asserted. During this time, all registers and controls are set to the hardware determined initial
conditions. Software access during this time will be ignored, and any expected actions from software activity will
be invalid.
When both VDDA and VDDC reach a value above their respective thresholds, an internal reset pulse is generated
which extends the reset condition for an additional time. The duration of this extended reset time is approximately
50 microseconds, but not longer than 100 microseconds. The reset condition remains asserted during this
time. If either VDDA or VDDC at any time becomes lower than its respective threshold voltage, a new reset
condition will result. The reset condition will continue until both VDDA and VDDC again higher than their
respective thresholds. After VDDA and VDDC are again both greater than their respective threshold voltage, a
new reset pulse will be generated, which again will extend the reset condition for not longer than an additional 100
microseconds.
11.11.2. Power Related Software Considerations
There is no direct way for software to determine that the device is actively held in a reset condition. If there is a
possibility that software could be accessing the device sooner than 100 microseconds after the VDDA and VDDC
supplies are valid, the reset condition can be determined indirectly. This is accomplished by writing a value to any
register other than register 0x00, with that value being different than the power-on reset initial values. The
optimum choice of register for this purpose may be dependent on the system design, and it is recommended the
system engineer choose the register and register test bit for this purpose. After writing the value, software will
then read back the same register. When the register test bit reads back as the new value, instead of the power-
on reset initial value, software can reliably determine that the reset condition has ended.
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Although it is not required, it is strongly recommended that a Software Reset command should be issued after
power-on and after the power-on-reset condition is ended. This will help insure reliable operation under every
power sequencing condition that could occur.
11.11.3. Software Reset
The control registers can be reset to default conditions by writing any value to RST address (0x00), using any of
the control interface modes. Writing valid data to any other register disables the reset, but all registers will need
to be initiated again appropriate to the operation. See the applications section on powering NAU8812 up for
information on avoiding pops and clicks after a software reset.
11.11.4. Power Up/Down Sequencing
Most audio products have issues during power up and power down in the form of pop and click noise. To avoid
cuch issues the NAU8812 provides four different power supplies VDDA, VDDB, VDDC and VDDSPK with
separated grounds VSSA, VSSD and VSSSPK. The audio CODEC circuitry, the input amplifiers, output
amplifiers and drivers, the audio ADC and DAC converters, the PLL, and so on, can be powered up and down
individually by software control via 2-Wire or SPI interface. The zero cross function should be used when
changing the volume in the PGAs to avoid any audible pops or clicks. There are two different modes of operation
5.0V and 3.3V mode. The recommended power-up and power-down sequences for both the modes are outlined
as following.
Power Up
Name
VDDSPK - 3.3V operation
Analog – VDDA
VDDSPK - 5.0V operation
Analog – VDDA
Buffer - VDDB
Buffer - VDDB
Power supplies
Digital – VDDC
Digital – VDDC
Output driver - VDDSPK
SPKBST[2] = 0
Output driver – VDDSPK
SPKBST[2] = 1
Mode
MOUTBST[3] = 0
REFIMP[1:0]
MOUTBST[3] = 1
as required (value of the REFIMP bits based on the startup
time which is a combination of the reference impedance and
the decoupling capacitor on VREF)
Power
Management
ABIASEN[3] = 1
(enables the internal device bias for all analog blocks)
IOBUFEN[2] = 1
(enables the internal device bias buffer)
CLKIOEN[0] if required
BCLKSEL[4:2] if required
MCLKSEL[7:5] if required
PLLEN[5] if required
DACEN[0] = 1
CLKIOEN[0] if required
BCLKSEL[4:2] if required
MCLKSEL[7:5] if required
PLLEN[5] if required
DACEN[0] = 1
Clock divider
PLL
DAC, ADC
Mixers
ADCEN[0] = 1
ADCEN[0] = 1
SPKMXEN[2]
SPKMXEN[2]
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Power Up
VDDSPK - 3.3V operation
Name
VDDSPK - 5.0V operation
MOUTMXEN[3]
MOUTEN[7]
MOUTMXEN[3]
MOUTEN[7]
NSPKEN[6]
Output stages
Un-mute DAC
NSPKEN[6]
PSPKEN[5]
PSPKEN[5]
DACMT[6] = 0
DACMT[6] = 0
Table 30: Power up sequence
Name
Power Down Both Cases
Un-mute DAC
DACMT[6] = 1
Power Management
PWRM1 = 0x000
MOUTEN[7]
Output stages
Power supplies
NSPKEN[6]
PSPKEN[5]
Analog – VDDA
Buffer - VDDB
Digital – VDDC
Output driver – VDDSPK
Table 31: Power down Sequence
11.11.5. Reference Impedance (REFIMP) and Analog Bias
Before the device is functional or any of the individual analog blocks are enabled REFIMP[1:0] address (0x01)
and ABIASEN[3] address (0x01) must be set. The REFIMP[1:0] bits control the resistor values (“R” in Figure3)
that generates the mid supply reference, VREF. REFIMP[1:0] bits control the power up ramp rate in conjunction
with the external decoupling capacitor. A small value of “R” allows fast ramp up of the mid supply reference and a
large value of “R” provides higher PSRR of the mid supply reference.
The master analog biasing of the device is enabled by setting ABIASEN[3] address (0x01). This bit has to be set
before for the device to function.
11.11.6. Power Saving
Saving power is one of the critical features in a semiconductor device specially ones used in the Bluetooth
headsets and handheld device. NAU8812 has two oversampling rates 64x and 128x. The default mode of
operation for the DAC and ADC is in 64x oversampling mode which is set by programming DACOS[3] address
(0x0A) and ADCOS[3] address (0x0E) respectively to LOW. Power is saved by choosing 64x oversampling rate
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compared to 128x oversampling rate but slightly degrades the noise performance. To each lowest power
possible after the device is functioning set ABIASEN[3] address (0x01) bit to LOW.
Addr
0x01 DCBUFEN
0x0A
D8
D7
0
0
D6
AUXEN PLLEN MICBIASEN ABIASEN IOBUFEN
DACMT DEEMP[1:0] DACOS AUTOMT
MOUTF[2:0]
0x3A LPSPKA LPIPBST LPADC LPSPKD
LPDAC
D5
D4
D3
D2
D1
REFIMP
0
0
D0
Default
0x000
0
DACPL 0x000
ADCPL 0x100
0x0E MOUTFEN MOUTFAM
ADCOS
TRIMREG
0
0
IBADJ
0
0x000
Table 32: Registers associated with Power Saving
11.11.7. Estimated Supply Currents
NAU8812 can be programmed to enable or disable various analog blocks individually. The table below shows the
amount of current consumed by certain analog blocks. Sample rate settings will vary current consumption of the
VDDC supply. VDDC consumes approximately 4mA with VDDC = 1.8V and fs = 48kHz. Lower sampling rates
will draw lower current.
BIT
Address
VDDA CURRENT
10K => 300 uA
161k/595k < 100 uA
REFIMP[1:0]
IOBUFEN[2]
ABIASEN[3]
MICBIASEN[4]
PLLEN[5]
40uA
600uA
0x01
500 uA
2.5mA Clocks Applied
80uA
DCBUFEN[8]
ADCEN[0]
x64 - ADCOS= 0 => 2.0mA
x128 - ADCOS= 1 => 3.0mA
PGAEN[2]
0x02
400uA
200 uA
BSTEN[4]
X64 (DACOS=0)=>1.6mA
x128(DACOS=1)=>1.7mA
DACEN[0]
SPKMXEN[2]
MOUTMXEN[3]
NSPKEN[6]
PSPKEN[5]
MOUTEN[7]
400uA
200uA
0x03
1mA from VDDSPK + 100uA (VDDA = 5V mode)
1mA from VDDSPK + 100uA (VDDA = 5V mode)
100uA
Table 33: VDDA 3.3V Supply Current
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NAU8812
12. REGISTER DESCRIPTION
Register
Address
Register Bits
D4
Register Names
Default
DEC HEX
D8
D7
D6
D5
D3
D2
D1
D0
0
0
Software Reset
RESET (SOFTWARE)
000
POWER MANAGEMENT
1
2
3
01 Power Management 1 DCBUFEN
0
0
AUXEN
0
PLLEN MICBIASEN ABIASEN
IOBUFEN
PGAEN
REFIMP
000
02 Power Management 2
03 Power Management 3
0
0
0
BSTEN
0
0
0
0
ADCEN
DACEN
000
000
MOUTEN NSPKEN
PSPKEN
MOUTMXEN SPKMXEN
AUDIO CONTROL
AIFMT[1:0]
4
5
6
7
8
04 Audio Interface
05 Companding
06 Clock Control 1
07 Clock Control 2
08 GPIO CTRL
BCLKP
FSP
0
WLEN[1:0]
DACPHS
ADCPHS
0
050
000
140
000
000
000
0FF
100
0FF
0
0
0
0
DACCM[1:0]
ADCCM[1:0]
ADDAP
CLKIOEN
SCLKEN
CLKM
MCLKSEL[2:0]
BCLKSEL[2:0]
0
0
0
0
0
0
0
0
SMPLR[2:0]
AUTOMT
0
0
GPIOPLL[1:0]
DEEMP[1:0]
GPIOPL
DACOS
GPIOSEL[2:0]
0
10 0A DAC CTRL
11 0B DAC Volume
14 0E ADC CTRL
15 0F ADC Volume
0
DACMT
DACPL
ADCPL
0
HPFEN
0
DACGAIN
ADCOS
ADCGAIN
DIGITAL TO ANALOG (DAC) LIMITER
DACLIMDCY[3:0]
DACLIMTHL[2:0]
NOTCH FILTER
NFCA0[13:7]
HPFAM
HPF[2:0]
0
24 18 DAC Limiter 1
25 19 DAC Limiter 2
DACLIMEN
0
DACLIMATK[3:0]
DACLIMBST[3:0]
032
000
0
27 1B Notch Filter High
28 1C Notch Filter Low
29 1D Notch Filter High
30 1E Notch Filter Low
NFCU
NFCU
NFCU
NFCU
NFCEN
000
000
000
000
0
0
0
NFCA0[6:0]
NFCA1[13:7]
NFCA1[6:0]
ALC CONTROL
32 20 ALC CTRL 1
33 21 ALC CTRL 2
34 22 ALC CTRL 3
35 23 Noise Gate
ALCEN
ALCZC
ALCM
0
0
0
0
ALCMXGAIN[2:0]
ALCMNGAIN[2:0]
038
00B
032
000
ALCHT[3:0]
ALCDCY[3:0]
ALCSL[3:0]
ALCATK[3:0]
0
0
0
ALCNEN
ALCNTH[2:0]
PLL CONTROL
PLLMCLK
36 24 PLL N CTRL
37 25 PLL K 1
38 26 PLL K 2
39 27 PLL K 3
0
0
0
0
0
0
0
PLLN[3:0]
008
00C
093
0E9
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
INPUT, OUTPUT & MIXER CONTROL
40 28 Attenuation CTRL
44 2C Input CTRL
45 2D PGA Gain
0
0
0
0
0
0
0
0
0
MOUTATT
AUXPGA
SPKATT
0
000
003
010
MICBIASV
AUXM
NMICPGA PMICPGA
0
PGAZC
PGAMT
PGAGAIN[5:0]
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Register
Address
Register Bits
D4
Register Names
Default
DEC HEX
D8
D7
D6
D5
D3
D2
D1
AUXBSTGAIN
TSEN
D0
47 2F ADC Boost
PGABST
0
PMICBSTGAIN
0
MOUTBST
0
100
49 31 Output CTRL
50 32 Mixer CTRL
0
0
0
0
0
0
0
0
0
0
SPKBST
0
AOUTIMP
DACSPK
002
001
039
0
SPKZC
0
AUXSPK
BYPSPK
54 36 SPKOUT Volume
56 38 MONO Mixer Control
SPKMT
MOUTMT
SPKGAIN[5:0]
0
0
0
AUXMOUT BYPMOUT DACMOUT 001
LOW POWER CONTROL
LPDAC MICBIASM
58 3A Power Management 4 LPIPBST
LPADC
TRI
LPSPKD
TRIMREG
IBADJ
000
PCM TIME SLOT & ADCOUT IMPEDANCE OPTION CONTROL
59 3B Time Slot
TSLOT[8:0]
000
60 3C ADCOUT Drive
PCMTSEN
PCM8BIT PUDOEN
PUDPE
PUDPS
LOUTR
PCMB
TSLOT[9:8] 020
REGISTER ID
62 3E Silicon Revision
63 3F 2-Wire ID
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0EE
01A
0CA
124
001
000
000
1
0
0
64 40 Additional ID
65 41 Reserved
0
0
0
1
0
0
69 45 High Voltage CTRL
70 46 ALC Enhancements 1
MOUTMT
HVOPU
HVOP
ALCPKSEL ALCNGSEL
ALCGAINL (READ ONLY)
71 47 ALC Enhancements 2 PKLIMEN
0
73 49 Additional IF CTRL
75 4B Power/Tie-off CTRL
76 4C ALC P2P Detector
77 4D ALC Peak Detector
78 4E Control and Status
SPIEN
0
FSERRVAL[1:0]
FSERFLSH FSERRENA
NFDLY
0
DACINMT PLLLOCKP DACOS256 000
LPSPKA
0
0
0
MANVREFH MANVREFM MANVREFL 000
P2PDET (READ ONLY)
PDET (READ ONLY)
000
000
0
0
AMTCTRL
SBUFL
HVDET
SNSPK
NSGATE
SPSPK
AMUTE
SMOUT
DMUTE
0
0
0
FTDEC
0
000
000
79 4F Output tie-off CTRL MANOUTEN SBUFH
emPowerAudio™
Datasheet Revision 2.8
Page 64 of 110
June 2016
NAU8812
12.1. SOFTWARE RESET
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x000
0x00
RESET (SOFTWARE)
This is device Reset register. Performing a write instruction to this register with any data will reset all the bits in
the register map to default.
12.2. POWER MANAGEMENT REGISTERS
12.2.1. Power Management 1
Addr
D8
D7
0
D6
D5
D4
D3
D2
D1
D0
Default
0x01 DCBUFEN
AUXEN PLLEN MICBIASEN ABIASEN IOBUFEN
REFIMP[1:0]
0x000
Microphone
Bias
Enable
Analogue
amplifier
bias control
Buffer for DC
level shifting
Enable
Unused
input/output tie
off buffer enable
AUX input
buffer enable
Name
PLL enable
Bit
DCBUFEN[8]
AUXEN[6]
PLLEN[5]
MICBIASEN[4]
ABIASEN[3]
IOBUFEN[2]
0
Disable
Disable
Disable
Disable
Enable
Disable
Disable
Enable
(required for
1.5x gain)
1
Enable
Enable
Enable
Enable
The DCBUFEN[8] address (0x01) is a dedicated buffer for DC level shifting output stages when in 1.5x gain
boost configuration. There are three different reference impedance selections to choose from as follows:
VREF REFERENCE
IMPEDANCE SELECTION
(“R” refers to “R” as shown in Figure3)
REFIMP[1]
REFIMP[0]
Mode
0
0
1
1
0
1
0
1
Disable
R = 80 k
R = 300 k
R = 3 k
emPowerAudio™
Datasheet Revision 2.8
Page 65 of 110
June 2016
NAU8812
12.2.2. Power Management 2
Addr
D8
0
D7
0
D6
0
D5
0
D4
D3
0
D2
D1
0
D0
Default
0x02
BSTEN
PGAEN
ADCEN 0x000
Input Boost
Enable
MIC(+/-)
PGA Enable
Name
ADC Enable
Bit
BSTEN[4]
PGAEN[2]
ADCEN[0]
0
1
Stage Disable
Stage Enable
Disable
Enable
Disable
Enable
12.2.3. Power Management 3
Addr
D8
0
D7
D6
D5
D4
0
D3
D2
D1
D0
Default
0x03
MOUTEN NSPKEN PSPKEN
MOUTMXEN SPKMXEN
0
DACEN 0x000
MOUT
Enable
SPKOUT-
Enable
SPKOUT+
Enable
MONO Mixer
Enable
Speaker
Mixer Enable
DAC
Enable
Name
Bit
MOUTEN[7] NSPKEN[6]
PSPKEN[5]
MOUTMXEN[3] SPKMXEN[2] DACEN[0]
0
1
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
12.3. AUDIO CONTROL REGISTERS
12.3.1. Audio Interface Control
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Default
0x04
BCLKP
FSP
WLEN[1:0]
AIFMT[1:0]
DACPHS ADCPHS
0x050
The following table explains the PCM control register bits.
DAC Data ‘right’ or ‘left’
ADC Data ‘right’ or ‘left’
BCLK
Polarity
Frame Clock
Polarity
Name
phases of FRAME clock
phases of FRAME clock
Bit
BCLKP[8]
FSP[7]
Normal
Inverted
DACPHS[2]
ADCPHS[1]
DAC data appear in ‘left’ phase of
ADC data appear in ‘left’ phase of
0
1
Normal
FRAME
FRAME
DAC data appears in ‘right’ phase of
ADC data appears in ‘right’ phase of
Inverted
FRAME
FRAME
There are three different CODEC modes to choose from as follows:
emPowerAudio™
Datasheet Revision 2.8
Page 66 of 110
June 2016
NAU8812
Word Length Selection
WLEN[6] WLEN[5] Bits
Audio Data Format Select
AIFMT[4] AIFMT[3] Format
Right
Justified
0
0
16
0
0
0
1
1
1
0
1
20
24
32
0
1
1
1
0
1
Left Justified
I2S
PCM A
12.3.2. Audio Interface Companding Control
Addr
D8
0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
Default
0x000
0x05
CMB8
DACCM[1:0]
ADCCM[1:0]
ADDAP
The NAU8812 provides a Digital Loopback ADDAP[0] address (0x05) bit. Setting ADDAP[0] bit to HIGH enables
the loopback so that the ADC data can be fed directly into the DAC input.
Companding Mode 8-bit
DAC Companding Selection
DACCM[4] DACCM[3] Mode
ADC Companding Select
ADCCM[2] ADCCM[1] Mode
word enable
CMB8[5] Mode
normal
operation
0
1
0
0
Disabled
0
0
Disabled
8-bit operation
0
1
1
1
0
1
Reserved
µ-Law
0
1
1
1
0
1
Reserved
µ-Law
A-Law
A-Law
DAC audio data input option to route
directly to ADC data stream
ADDAP[0]
Mode
0
Normal Operation
ADC output data stream
routed to DAC input data
path
1
emPowerAudio™
Datasheet Revision 2.8
Page 67 of 110
June 2016
NAU8812
12.3.3. Clock Control Register
Addr
D8
D7
D6
D5
D4
D3
D2
D1
0
D0
Default
0x06
CLKM
MCLKSEL[2:0]
BCLKSEL[2:0]
CLKIOEN 0x140
Master Clock Selection
MCLKSEL MCLKSEL MCLKSEL
Bit Clock Select
BCLKSEL BCLKSEL BCLKSEL
Mode
1
Mode
[7]
[6]
[5]
[4]
[3]
[2]
1
(BCLK=MCLK)
2
0
0
0
0
0
0
1.5
0
0
1
0
0
1
(BCLK=MCLK/2)
2
3
4
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
8
4
16
32
6
8
Reserved
Reserved
12
Source of Internal Clock master
clock source selection control
Enables chip master mode to
drive FS and BCLK outputs
Name
Bit
CLKM[8]
CLKIOEN[0]
MCLK (PLL Bypassed)
MCLK pin used as master clock
Slave Mode
(FS and BCLK are inputs)
0
1
Master Mode
(FS and BCLK are driven as
outputs by internally generated
clocks)
MCLK (PLL Output)
Internal PLL oscillator output
used as master clock
emPowerAudio™
Datasheet Revision 2.8
Page 68 of 110
June 2016
NAU8812
12.3.4. Audio Sample Rate Control Register
Addr
D8
0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
Default
0x07
SMPLR[2:0]
SCLKEN 0x000
The Audio sample rate configures the coefficients for the internal digital filters
Sample Rate Selection
SMPLR[3] SMPLR[2] SMPLR[1] Mode (Hz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
48 k
32 k
24 k
16 k
12 k
8 k
Reserved
Reserved
NAU8812 provides a slow clock to be used for both the jack insert detect debounce circuit and the zero cross
timeout.
Slow Clock Enable
Bit
SCLKEN[0]
0
1
MCLK
PLL Output (Period 221 * MCLK)
emPowerAudio™
Datasheet Revision 2.8
Page 69 of 110
June 2016
NAU8812
12.3.5. GPIO Control Register
Addr
D8
0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
Default
0x08
GPIOPLL[4:5]
GPIOPL
GPIOSEL[2:0]
0x000
General Purpose I/O Selection
GPIOSEL GPIOSEL GPIOSEL
Mode (Hz)
[2]
[1]
[0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CSb Input
Jack Insert Detect
Temperature OK
AMUTE Active
PLL CLK Output
PLL Lock
1
0
PLL Output Clock Divider
GPIO Polarity
GPIOPLL[5]
GPIOPLL[4]
Mode
Bit
GPIOPL[3]
1
2
3
4
0
0
1
1
0
1
0
1
0
1
Normal
Inverted
12.3.6. DAC Control Register
Addr
D8
0
D7
0
D6
D5
D4
D3
D2
D1
D0
Default
0x0A
DACMT
DEEMP[1:0]
DACOS AUTOMT
0
DACPL 0x000
Name Soft Mute Enable Over Sample Rate Auto Mute enable Polarity Invert
Bit
DACMT[6]
DACOS[3]
AUTOMT[2]
DACPL[0]
64x
0
Disable
Disable
Normal
(Lowest power)
128x
(best SNR)
DAC Output
Inverted
1
Enable
Enable
emPowerAudio™
Datasheet Revision 2.8
Page 70 of 110
June 2016
NAU8812
De-emphasis
DEEMP[4]
DEEMP[5]
Mode
0
0
1
1
0
1
0
1
No de-emphasis
32kHz sample rate
44.1kHz sample rate
48kHz sample rate
12.3.7. DAC Gain Control Register
Addr
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x0B
DACGAIN
0x0FF
DAC Gain
DACGAIN[7:0]
Mode (dB)
B7
B6
B5
B4
B3 B2 B1
B0
Digital
Mute
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
-127.0
-126.5
-126.0
DAC Gain Range -127dB to 0dB @ 0.5 increments
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
-1.5
-1.0
-0.5
0.0
12.3.8. ADC Control Register
Addr
D8
D7
D6
D5
D4
D3
ADCOS
D2
0
D1
0
D0
Default
0x0E HPFEN HPFAM
HPF[2:0]
ADCPL 0x100
High Pass Filter
Audio or Application
Mode
Over Sample
Rate
Name
ADC Polarity
Enable
Bit
HPFEN[8]
HPFAM[7]
ADCOS[3]
ADCPL[0]
0
1
Disable
Enable
Audio (1st order, fc ~ 3.7 Hz)
Application (2nd order, fc = HPF)
64x (Lowest power)
128x (best SNR)
Normal
Inverted
emPowerAudio™
Datasheet Revision 2.8
Page 71 of 110
June 2016
NAU8812
High Pass Filter
fs ( kHz)
SMPLR=101
SMPLR=100
SMPLR=011
SMPLR=010
SMPLR=001
SMPLR=000
HPF[6]
B2
HPF[5]
HPF[4]
B0
B1
8
11.025
12
16
22.05
24
32
44.1
48
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
82
113
141
180
225
281
360
450
563
122
153
156
245
306
392
490
612
82
113
141
180
225
281
360
450
563
122
153
156
245
306
392
490
612
82
113
141
180
225
281
360
450
563
122
153
156
245
306
392
490
612
102
131
163
204
261
327
408
102
131
163
204
261
327
408
102
131
163
204
261
327
408
12.3.9. ADC Gain Control Register
Addr
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x0F
ADCGAIN
0x0FF
ADC Gain
ADCGAIN[7:0]
Mode (dB)
B7
B6
B5
B4
B3 B2 B1
B0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Unused
-127.0
-126.5
-126.0
ADC Gain Range -127dB to 0dB @ 0.5 increments
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
-1.5
-1.0
-0.5
0.0
emPowerAudio™
Datasheet Revision 2.8
Page 72 of 110
June 2016
NAU8812
12.4.
DIGITAL TO ANALOG CONVERTER (DAC) LIMITER REGISTERS
Addr
0x18 DACLIMEN
0x19
D8
D7
0
D6
DACLIMDCY[3:0]
DACLIMTHL[2:0]
D5
D4
D3
D2
D1
D0
Default
DACLIMATK[3:0]
DACLIMBST[3:0]
0x032
0x000
0
DAC Limiter Decay time (per 6dB gain change) for 44.1
kHz sampling. Note that these will scale with sample
rate
DAC Limiter Attack time (per 6dB gain change) for 44.1
kHz sampling. Note that these will scale with sample rate
DACLIMDCY[3:0]
DACLIMATK[3:0]
B3
B2
B1
B0
Decay Time
B3
B2
B1
B0
Attack Time
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
544.0 us
1.1 ms
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
68 us
136 us
272 us
544 us
1.1 ms
2.2 ms
4.4 ms
8.7 ms
17.4 ms
35 ms
2.2 ms
4.4 ms
8.7 ms
17.4 ms
35.0 ms
69.6 ms
139.0 ms
278.5 ms
557.0 ms
69.6 ms
To
1.1 s
To
139 ms
1
1
1
1
1
1
1
1
emPowerAudio™
Datasheet Revision 2.8
Page 73 of 110
June 2016
NAU8812
DAC Limiter volume Boost (can be used as
DAC Limiter Programmable signal threshold level
(determines level at which the limiter starts to
operate)
a
stand alone volume Boost when
DACLIMEN=0)
DACLIMTHL[3:0]
B1
DACLIMBST[3:0]
Threshold
(dB)
Boost
(dB)
B2
B0
B3
B2
B1
B0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
-1
-2
-3
-4
-5
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
+1
+2
+3
+4
+5
+6
+7
+8
+9
+10
+11
1
1
0
0
To
1
-6
1
1
DAC Digital Limiter
Bit
DACLIMEN[8]
0
1
Disabled
Enabled
1
1
1
1
0
0
0
1
+12
To
Reserved
1
1
1
1
12.5. NOTCH FILTER REGISTERS
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x000
0x000
0x000
0x000
0x1B NFCU NFCEN
NFCA0[13:7]
NFCA0[6:0]
NFCA1[13:7]
NFCA1[6:0]
0x1C NFCU
0x1D NFCU
0x1E NFCU
0
0
0
The Notch Filter is enabled by setting NFCEN[7] address (0x1B) bit to HIGH. The coefficients, A0 and A1, should
be converted to 2’s complement numbers to determine the register values. A0 and A1 are represented by the
register bits NFCA0[13:0] and NFCA1[13:0]. Since there are four register of coefficients, a Notch Filter Update bit
is provided so that the coefficients can be updated simultaneously. NFCU[8] is provided in all registers of the
Notch Filter coefficients but only one bit needs to be toggled for LOW - HIGH - LOW for an update. If any of the
NFCU[8] bits are left HIGH then the Notch Filter coefficients will continuously update. An example of how to
calculate is provided in the Notch Filter section.
emPowerAudio™
Datasheet Revision 2.8
Page 74 of 110
June 2016
NAU8812
Name
A0
A1
Notation
Register Value (DEC)
2fb
2fs
NFCA0 = -A0 x 213
NFCA1 = -A1 x 212
(then convert to 2’s
complement)
1 tan
fc = center frequency (Hz)
fb = -3dB bandwidth (Hz)
fs = sample frequency
2fc
fs
1 A0 xcos
Coefficient
2fb
2fs
1 tan
(Hz)
12.6. AUTOMATIC LEVEL CONTROL REGISTER
12.6.1. ALC1 REGISTER
Addr
D8
D7
0
D6
0
D5
D4
ALCMXGAIN[2:0]
D3
D2
D1
D0
Default
0x038
0x20
ALCEN
ALCMNGAIN[2:0]
Maximum Gain
Minimum Gain
ALCMNGAIN[2:0]
ALCMXGAIN[2:0]
Mode
Mode
B2
B1
B0
B2
B1
B0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
-6.75dB
-0.75dB
+5.25dB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-12dB
-6dB
0dB
1
0
1
0
1
+11.25dB
+17.25dB
+23.25dB
+29.25dB
+35.25dB
+6dB
+12dB
+18dB
+24dB
+30dB
Name
ALC Enable
ALCEN[8]
Bit
Disabled (PGA gain set by PGAGAIN
register bits)
0
1
Enabled (ALC controls PGA gain)
emPowerAudio™
Datasheet Revision 2.8
Page 75 of 110
June 2016
NAU8812
12.6.2. ALC2 REGISTER
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00B
0x21
ALCZC
ALCHT[3:0]
ALCSL[3:0]
ALC HOLD TIME before gain is increased.
ALC TARGET – sets signal level at ADC input
ALCHT[3:0]
B6 B5
ALCSL[3:0]
B2 B1
ALC Hold
Time (sec)
ALC Target
Level (dB)
B7
B4
B3
B0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
-28.5 fs
-27 fs
0
0
0
1
2 ms
4 ms
0
0
0
1
25.5 fs
ALC Target Level Range
-28.5dB to -6dB @ 1.5dB increments
Time Doubles with every increment
1
1
1
0
0
0
0
0
1
0
1
0
256 ms
512 ms
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
-12 fs
-10.5 fs
-9 fs
To
1 s
-7.5 fs
-6 fs
1
1
1
1
ALC Zero Crossing
Detect
Name
Bit
ALCZC[8]
0
1
Disabled
Enabled
It is recommended that zero crossing should not be used in conjunction with the ALC or Limiter functions
emPowerAudio™
Datasheet Revision 2.8
Page 76 of 110
June 2016
NAU8812
12.6.3. ALC3 REGISTER
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x032
0x22
ALCM
ALCDCY[3:0]
ALCATK[3:0]
ALC DECAY TIME
ALCM = 0 (Normal Mode)
ALCDCY[3:0]
ALCM = 1 (Limiter Mode)
90% of
Range
90% of
Range
B3
B2
B1
B0
Per Step
Per 6dB
Per Step
Per 6dB
0
0
0
0
0
0
0
0
1
0
1
0
500 us
1 ms
4 ms
8 ms
28.78 ms
57.56 ms
115 ms
125 us
250 us
500 us
1 ms
2 ms
4 ms
7.2 ms
14.4 ms
28.8 ms
2 ms
16 ms
Time doubles with every increment
1
1
1
0
0
0
0
0
1
0
1
0
128 ms
256 ms
1 s
2 s
7.37 s
14.7 s
32 ms
64 ms
256 ms
512 ms
1.8 s
3.7 s
To
512 ms
4 s
29.5 s
128 ms
1 s
7.37 s
1
1
1
1
ALC ATTACK TIME
ALCM = 0 (Normal Mode)
ALCATK[3:0]
ALCM = 1 (Limiter Mode)
90% of
Range
90% of
Range
B3
B2
B1
B0
Per Step
Per 6dB
Per Step
Per 6dB
0
0
0
0
0
0
0
0
1
0
1
0
125 us
250 us
500 us
1 ms
2 ms
4 ms
7.2 ms
14.4 ms
28.85 ms
31 us
62 us
248 us
496 us
992 us
1.8 ms
3.6 ms
7.15 ms
124 us
Time doubles with every increment
1
1
1
0
0
0
0
0
1
0
1
0
26.5 ms
53 ms
256 ms
512 ms
1.53 s
3.06 s
7.9 ms
63.2 ms
127 ms
455.8 ms
916 ms
15.87 ms
To
128 ms
1 s
7.89 s
31.7ms
254 ms
1.83 s
1
1
1
1
emPowerAudio™
Datasheet Revision 2.8
Page 77 of 110
June 2016
NAU8812
12.7. NOISE GAIN CONTROL REGISTER
Addr
D8
0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
Default
0x000
0x23
ALCNEN
ALCNTH[2:0]
Noise Gate Enable
Noise Gate Threshold
Bit
ALCNEN[3]
Disabled
ALCNTH[2:0]
Mode
0
1
B2
B1
B0
Enabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-39 dB
-45 dB
-51 dB
-57 dB
-63 dB
-69 dB
-75 dB
-81 dB
emPowerAudio™
Datasheet Revision 2.8
Page 78 of 110
June 2016
NAU8812
12.8. PHASE LOCK LOOP (PLL) REGISTERS
12.8.1. PLL Control Registers
Addr
D8
0
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
Default
0x008
0x24
PLLMCLK
PLLN[3:0]
PLL Integer
PLLN[3:0]
PLL Clock
PLLMCLK[4]
MCLK not divided
Bit
Frequency
Ratio
B3
B2
B1
B0
0
1
Divide MCLK by 2 before input
PLL
0
0
0
1
Not Valid
To
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
5
6
7
8
9
10
11
12
13
Not Valid
12.8.2. Phase Lock Loop Control (PLL) Registers
Addr
0x25
0x26
0x27
D8
0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
Default
0x00C
0x093
0x0E9
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
Fractional (K) part of PLLK1 – PLLK3 input/output frequency ratio
emPowerAudio™
Datasheet Revision 2.8
Page 79 of 110
June 2016
NAU8812
12.9.
INPUT, OUTPUT, AND MIXERS CONTROL REGISTER
Attenuation Control Register
12.9.1.
Addr
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
D1
D0
0
Default
0x28
MOUTATT SPKATT
0x000
Attenuation Control
Attenuation control for bypass path (output of
Name input boost stage) to speaker mixer and MONO
mixer input
Bit
MOUTATT[2]
SPKATT[1]
0
1
0 dB
0 dB
-10 dB
-10 dB
12.9.2. Input Signal Control Register
Addr
D8
D7
D6
0
D5
0
D4
0
D3
D2
D1
D0
Default
0x2C
MICBIASV
AUXM AUXPGA NMICPGA PMICPGA 0x003
Input PGA amplifier
MICN to input PGA
AUX amplifier output to
input PGA signal source
Auxiliary Input mode
AUXM[3]
positive terminal to
negative terminal
MIC+ or VREF
Bit
AUXPGA[2]
NMICPGA[1]
PMICPGA[0]
AUX not connected to
input PGA
MICN not connected to
input PGA
Input PGA Positive
terminal to VREF
0
Inverting Buffer
Input PGA Positive
terminal to MICP
through variable resistor
Mixer (Internal Resistor
bypassed)
AUX to input PGA
Negative terminal
MICN to input PGA
Negative terminal.
1
Microphone Bias Voltage Control
MICBIASV[8:7]
Address (0x2C)
MICBIASM[4] = 0
Address (0x28)
MICBIASM[4] = 1
Address (0x28)
0
0
1
1
0
1
0
1
0.9* VDDA
0.65* VDDA
0.75* VDDA
0.50* VDDA
0.85* VDDA
0.60* VDDA
0.70* VDDA
0.50* VDDA
emPowerAudio™
Datasheet Revision 2.8
Page 80 of 110
June 2016
NAU8812
12.9.3. PGA Gain Control Register
Addr
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x010
0x2D
PGAZC PGAMT
PGAGAIN[5:0]
Programmable Gain Amplifier Gain
PGAGAIN[5:0]
B5
B4
B3
B2
B1
B0
Gain
0
0
0
0
0
0
0
0
0
0
0
1
-12.00 dB
-11.25 dB
-10.50 dB
:::
0
0
0
0
1
0
:::
0
:::
0
:::
1
:::
1
:::
1
:::
1
-0.75 dB
0 dB
0
1
0
0
0
0
0
1
0
0
0
1
+0.75 dB
PGA Gain Range -12dB to +35.25dB @ 0.75
increment
:::
1
:::
1
:::
1
:::
1
:::
0
:::
1
:::
33.75
34.50
35.25
1
1
1
1
1
0
1
1
1
1
1
1
PGA Zero Cross Enable
Mute Control for PGA
Bit
PGAZC[7]
PGAMT[6]
Update gain when gain
register changes
0
Normal Mode
PGA Muted
Update gain on 1st zero
cross after gain register
write
1
emPowerAudio™
Datasheet Revision 2.8
Page 81 of 110
June 2016
NAU8812
12.9.4. ADC Boost Control Registers
Addr
D8
D7
0
D6
D5
D4
D3
0
D2
D1
D0
Default
0x2F
PGABST
PMICBSTGAIN
AUXBSTGAIN
0x100
MIC+ pin to the input Boost Stage
(NB, when using this path set
PMICPGA=0):
Auxiliary to Input Boost Stage
PMICBSTGAIN[2:0]
AUXBSTGAIN[2:0]
Gain (dB)
Gain (dB)
B2
B1
B0
B2
B1
B0
Path
Disconnected
Path
Disconnected
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
-12
-9
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
-12
-9
-6
-3
0
-6
-3
0
+3
+6
+3
+6
Name
Input Boost
Bit
PGABST[8]
0
1
PGA output has +0dB gain through input Boost stage
PGA output has +20dB gain through input Boost stage
12.9.5. Output Register
Addr
D8
0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
Default
0x31
MOUTBST SPKBST TSEN AOUTIMP 0x002
MONO Output Boost
Stage
Speaker Output Boost
Stage
Thermal Shutdown Analog Output Resistance
Bit
MOUTBST[3]
SPKBST[2]
TSEN[1]
AOUTIMP[0]
0
1
(1.0 x VREF) Gain Boost
(1.0 x VREF) Gain Boost
Disabled
~1kΩ
(1.5 x VREF) Gain Boost
(1.5 x VREF) Gain Boost
Enabled
~30 kΩ
emPowerAudio™
Datasheet Revision 2.8
Page 82 of 110
June 2016
NAU8812
12.9.6. Speaker Mixer Control Register
Addr
D8
0
D7
0
D6
0
D5
D4
0
D3
0
D2
0
D1
D0
Default
0x32
AUXSPK
BYPSPK DACSPK 0x001
Bypass path (output of
Boost stage) to Speaker
Mixer
Auxiliary to Speaker Mixer
DAC to Speaker Mixer
Bit
AUXSPK[5]
BYPSPK[1]
DACSPK[0]
0
1
Disconnected
Connected
Disconnected
Connected
Disconnected
Connected
12.9.7. Speaker Gain Control Register
Addr
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x36
SPKZC
SPKMT
SPKGAIN[5:0]
0x039
Speaker Gain
SPKGAIN[5:0]
B5
B4
B3
B2
B1
B0
Gain (dB)
0
0
0
0
0
0
0
0
0
0
0
1
-57.0
-56.0
-55.0
:::
0
0
0
0
1
0
:::
1
:::
1
:::
1
:::
0
:::
0
:::
0
-1.0
0.0
1
1
1
0
0
1
1
1
1
0
1
0
+1.0
Speaker Gain Range -57 dB to +6 dB @ +1
increment
:::
1
:::
1
:::
1
:::
1
:::
0
:::
1
:::
+4.0
+5.0
+6.0
1
1
1
1
1
0
1
1
1
1
1
1
Speaker Gain Control Zero Cross
Speaker Output
Bit
SPKZC[7]
SPKMT[6]
Change Gain on Zero Cross
ONLY
0
1
Speaker Enabled
Speaker Muted
Change Gain Immediately
emPowerAudio™
Datasheet Revision 2.8
Page 83 of 110
June 2016
NAU8812
12.9.8. MONO Mixer Control Register
Addr
D8
0
D7
0
D6
D5
0
D4
0
D3
0
D2
D1
D0
Default
0x38
MOUTMXMT
AUXMOUT BYPMOUT DACMOUT 0x001
Bypass path (output of
Boost Stage) to MONO
Mixer
Auxiliary to
MONO Mixer
DAC to
MONO Mixer
MOUT Mute
Bit MOUTMXMT[6] AUXMOUT[2]
BYPMOUT[1]
DACMOUT[0]
0
1
Not Muted
Muted
Disconnected
Connected
Disconnected
Disconnected
Connected
Connected
During mute, the MONO output will output VREF that can be used as a DC reference for a headphone out.
12.9.9. Trimming Register
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x3A LPIPBST LPADC LPSPKD LPDAC MICBIASM
TRIMREG[3:2]
IBADJ[1:0]
0x000
Trim Output Regulator (V)
Adjust Master Bias of the Analog Portion
B1
B0
TRIMREG[3:2]
IBADJ[1:0]
0
0
1
1
0
1
0
1
1.800
1.610
1.400
1.218
Default Current Consumption
25% Current Increase from Default
14% Current Decrease from Default
25% Current Decrease from Default
Trim regulator bits can be used only when VDDD <2.7V.
Low Power
Speaker Driver
Low Power IP
Boost
Microphone bias
Mode selection
Low Power ADC
LPADC[7]
Low Power DAC
LPDAC[5]
Bit
LPIPBST[8]
LPSPKD[6]
MICBIASM[4]
0
Normal Function
Normal Function
Normal Function
Cut power in half
Normal Function
Disable
1
Cut power in half
Cut power in half
Cut power in half
Enable
Note cutting the power in half will directly affect the audio performances.
emPowerAudio™
Datasheet Revision 2.8
Page 84 of 110
June 2016
NAU8812
12.10. PCM TIME SLOT CONTROL & ADCOUT IMPEDANCE OPTION CONTROL
12.10.1. PCM1 TIMESLOT CONTROL REGISTER
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x000
0x3B
TSLOT[8:0]
Transmit and receive timeslot are expressed in number of BCLK cycles in a 10-bit word. The most significant bit
TSLOT[9] is located in register PCMTS2[0] address (0x3C). Timeslot, TSLOT[9:0], determines the start point for
the timeslot on the PCM interface for data in the transmit direction.
12.10.2. PCM2 TIMESLOT CONTROL REGISTER
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x3C PCMTSEN
TRI
PCM8BIT PUDOEN PUDPE PUDPS LOUTR PCMB TSLOT[9] 0x000
Left and Right
Tri-state PCMT
PCM Transit
Name
PCM Word Length
Channel have
same data
PCM Mode2
PCMB
Enable
LSB
Bit
0
PCMTSEN[8]
TRI[7]
PCM8BIT[6]
LOUTR
Drive the full Clock
of LSB
Use WLEN[6:5] to
select Word Length
PCM A
Disable
Disable
Audio interface will
be 8 Bit Word
Length
Tri-State the 2nd
half of LSB
1
PCM Time Slot
Enable
Enable
If TRI = 1 and PUDOEN = 0, the device will drive the LSB bit 1st half of BCLK out of the ADCOUT pin (stop driving
after LSB BCLK Rising edge) but if TRI = 0 or PUDOEN = 1 this feature is disabled, full BCLK of LSB will be
driven the LSB value.
PUDPE
PUDPS
iADCOUT
ADCOUT
PUDOE
Figure 41: The Programmable ADCOUT Pin
emPowerAudio™
Datasheet Revision 2.8
Page 85 of 110
June 2016
NAU8812
Internal ADC
out data
Power Up and Down
Output Enable
Power Up and
Down Pull Enable
Power Up and Down
Pull Select
OUTPUT
iADCOUT
PUDOEN[5]
PUDPE[4]
PUDPS[3]
PAD
0
1
x
x
x
1
1
0
0
0
x
x
0
1
1
x
x
x
0
1
0
1
Hi-Z
Pull-Low
Pull-High
12.11. REGISTER ID (READ ONLY)
12.11.1. Device revision register
Addr
D8
0
D7
1
D6
1
D5
1
D4
0
D3
D2
1
D1
D0
0
Default
0x0EE
0x3E
1
1
READ ONLY
Device revision ID
12.11.2. 2-WIRE ID Register (READ ONLY)
Addr
D8
0
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
Default
0x3F
1
1
0
1
0
0x01A
READ ONLY
First 7 bits (D0 – D6) of the 2-Wire device ID excluding the LSB read/write bit.
12.11.3. Additional ID (READ ONLY)
Addr
D8
0
D7
1
D6
1
D5
0
D4
0
D3
1
D2
0
D1
1
D0
0
Default
0x40
0x0CA
READ ONLY
emPowerAudio™
Datasheet Revision 2.8
Page 86 of 110
June 2016
NAU8812
12.12. Reserved
Addr
0x41
D8
1
D7
0
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
0
Default
0x124
12.13.
OUTPUT Driver Control Register
Addr
D8
D7
D6
D5
D4
D3
0
D2
D1
0
D0
Default
0x45
0
MOUTMT
HVOPU
HVOP
0x001
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
set internal output biasing to be
optimal for 3.6Vdc or lower
operation
set internal output biasing to be
optimal for higher than 3.6Vdc
operation
Override to automatic
3V/5V bias selection
0
HVOP
Note: For this to be effective
HVOPU[2] address 0x45 must
set
Note: For this to be effective
HVOPU[2] address 0x45 must set
This bit must set in conjunction with
HVOP[0] address 0x45 for the
automatic override to be effective
Update bit for HV
override feature
2
4
HVOPU
High Voltage override Disable
Disable
Headphone output mute MOUTMT
Enable
During mute, the MONO output will output VREF that can be used as a DC reference for a headphone out.
emPowerAudio™
Datasheet Revision 2.8
Page 87 of 110
June 2016
NAU8812
12.14. AUTOMATIC LEVEL CONTROL ENHANCED REGISTER
12.14.1. ALC1 Enhanced Register
Addr
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x001
0x46
ALCPKSEL ALCNGSEL
ALCGAINL[5:0] (READ ONLY)
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
ALC Disabled: Display PGA Gain
ALC Enabled: Display Real Time ALC Gain
5:0
6
Display PGA and ALC Gain
ALCGAINL
ALCNGSEL
ALCPKSEL
Choose peak or peak-to-peak value
for Noise Gate threshold logic
use peak-to-peak
use rectified peak
detector output value
detector output value
Choose peak or peak-to-peak value
for ALC threshold logic
use rectified peak
use peak-to-peak
7
detector output value
detector output value
12.14.2. ALC Enhanced 2 Register
Addr
D8
D7
D6
D5
D4
0
D3
D2
D1
D0
Default
0x47 PKLIMEN
0x000
Bit Value
Bit
Location
Bit Description
Bit Name
PKLIMEN
0
1
Enable control for ALC fast
peak limiter function
8
Enable
Disable
emPowerAudio™
Datasheet Revision 2.8
Page 88 of 110
June 2016
NAU8812
12.15. MISC CONTROL REGISTER
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x49 SPIEN FSERRVAL[1:0] FSERFLSH FSERRENA NFDLY DACINMT PLLLOCKP DACOS256 0x000
Bit Value
Set DAC to 256x
DACOS256 determined by Register 0x0A[3] oversampling rate regardless
(default) of Register 0x0A[3]
Bit
Location
Bit Description
Bit Name
0
1
Use oversampling rate as
Set DAC to use 256x
oversampling rate
0
1
2
Enable control to use PLL
output when PLL is not in
phase locked condition
PLL VCO output disabled when PLL VCO output used as-is
PLLLOCKP PLL is in unlocked condition
when PLL is in unlocked
condition
(default)
Enable control to mute
DAC limiter output when
softmute is enabled
DAC limiter output may not
move to exactly zero during
Softmute (default)
DAC limiter output muted to
exactly zero during Softmute
DACINMT
Enable control to delay use
of notch filter output when
filter is enabled
Enable control for short
frame cycle detection logic
Delay using notch filter output
512 sample times after notch
enabled (default)
Short frame cycle detection
logic enabled
Use notch filter output
immediately after notch filter
is enabled
Short frame cycle detection
logic disabled
Set DSP state to initial
conditions on short frame
sync event
3
4
5
NFDLY
FSERRENA
FSERFLSH
Enable DSP state flush on
short frame sync event
Ignore short frame sync events
(default)
Set SPI control bus mode
regardless of state of Mode SPIEN
pin
Force SPI 4-wire mode
regardless of state of Mode
pin
8
Default Operation
Short frame sync detection period value
trigger if frame time less than
FSERRVAL[1:0]
B1
B0
0
0
1
1
0
1
0
1
255 MCLK edges
253 MCLK edges
254 MCLK edges
255 MCLK edges
MODE
Pin
SPIEN[8]
Bit
Address
Description
0
0
0
2-Wire Interface (Write/Read)
1
SPI Interface 16-bit (Write ONLY)
0x49
SPI Interface 32-bit (Read)
SPI Interface 24-bit (Write)
(SSOP 28-Pin Write ONLY,
QFN 32-Pin Write/Read)
x
1
emPowerAudio™
Datasheet Revision 2.8
Page 89 of 110
June 2016
NAU8812
12.16. Output Tie-Off REGISTER
Addr
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x4B
LPSPKA
MANVREFH MANVREFM MANVREFL 0x000
Bit Value
Bit
Location
Bit Description
Bit Name
MANVREFL
MANVREFM
MANVREFH
LPSPKA
0
1
Direct manual control for switch for
VREF 6k-ohm resistor to ground
switch to ground controlled switch to ground in the
by Register 0x01 setting closed position
0
1
2
7
Direct manual control for switch for
VREF 160k-ohm resistor to ground
switch to ground controlled switch to ground in the
by Register 0x01 setting closed position
Direct manual control of switch for
VREF 600k-ohm resistor to ground
switch to ground controlled switch to ground in the
by Register 0x01 setting
closed position
Two-stage amplifier for
speaker driver
Three-stage amplifier
for speaker driver
Amplifier Stage
12.17. ALC PEAK-TO-PEAK READOUT REGISTER
Addr
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x4C
P2PDET
0x000
Bit
Location
Bit Description
Bit Name
P2PDET
READ ONLY Register
Outputs the instantaneous value contained in the peak-to-peak amplitude register
used by the ALC for signal level dependent logic. Value is highest of left or right
input when both inputs are under ALC control.
0 - 8
12.18. ALC PEAK READOUT REGISTER
Addr
D8
D7
D6
D5
D4
PDET
D3
D2
D1
D0
Default
0x4D
0x000
Bit
Location
Bit Description
Bit Name
PDET
READ ONLY Register
Outputs the instantaneous value contained in the peak detector amplitude register
used by the ALC for signal level dependent logic. Value is highest of left or right
input when both inputs are under ALC control.
0 - 8
emPowerAudio™
Datasheet Revision 2.8
Page 90 of 110
June 2016
NAU8812
12.19. AUTOMUTE CONTROL AND STATUS READ REGISTER
Addr
D8
0
D7
0
D6
D5
D4
D3
D2
D1
0
D0
Default
0x4E
AMTCTRL HVDET NSGATE
AMUTE
DMUTE
FTDEC 0x000
Bit Value
Bit
Location
Bit Description
Bit Name
FASTDEC
DMUTE
0
1
0
2
Peak limiter indicator
Below 87.5% of full scale
Above 87.5% of full scale
Digital gain is zero either by
.- Direct setting
READ ONLY BIT
Digital Mute function of the DAC
Digital gain greater than zero
.- Softmute function
READ ONLY BIT
Analog Mute function applied to DAC
3
4
AMUTE
Automute Disabled
Automute Enabled
Signal is greater than the noise Signal is less than the noise
gate threshold and ALC gain
can change
READ ONLY BIT
Logic controlling the Noise Gate
NSGATE
gate threshold and ALC gain
is held constant
READ ONLY BIT
High voltage detection circuit
monitoring VDDSPK voltage
VDDSPK logic switch voltage
threshold measured as 4.0Vdc
or Less
VDDSPK logic switch voltage
threshold measured as
4.0Vdc or Greater
5
6
HVDET
Automute operates on data at
the input to the DAC digital
attenuator (default)
Select observation point used by DAC
output Automute feature
Automute operates on data at
the DACIN input pin
AMTCTRL
12.20. Output Tie-off Direct Manual Control REGISTER
Addr
D8
D7
D6
D5
D4
D3
D2
0
D1
0
D0
0
Default
0x4F MANOUTEN SBUFH SBUFL SNSPK SPSPK
SMOUT
0x000
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
If MANUOUTEN = 1, use this bit to
control Auxout1 output tie-off
resistor switch
Tie-off resistor switch for
MOUT output is forced
closed
Tie-off resistor switch for MOUT
output is forced open
3
SMOUT
If MANUOUTEN = 1, use this bit to
control left speaker output Tie-off
resistor switch
Tie-off resistor switch for
SPKOUTP speaker output is
forced open
Tie-off resistor switch for
SPKOUTP speaker output
is forced closed
4
5
SPSPK
SNSPK
If MANUOUTEN = 1, use this bit to
control left speaker output Tie-off
resistor switch
Tie-off resistor switch for
SPKOUTN speaker output is
forced open
Tie-off resistor switch for
SPKOUTN speaker output
is forced closed
If MANUOUTEN = 1, use this bit to
control bypass switch around 1.0x
non-boosted output Tie-off buffer
amplifier
Bypass switch in closed
position when output buffer
amplifier is disabled
Normal automatic operation of
bypass switch
6
SBUFL
If MANUOUTEN = 1, use this bit to
control bypass switch around 1.5x
boosted output Tie-off buffer
amplifier
Bypass switch in closed
position when output buffer
amplifier is disabled
Normal automatic operation of
bypass switch
7
8
SBUFH
Ignore Register 0x4F bits to
control input Tie-off
resistor/buffer switching
Use Register 0x4F bits to
override automatic Tie-off
resistor/buffer switching
Enable direct control over output
Tie-off resistor switching
MANOUTEN
emPowerAudio™
Datasheet Revision 2.8
Page 91 of 110
June 2016
NAU8812
13. CONTROL INTERFACE TIMING DIAGRAM
13.1. SPI WRITE TIMING DIAGRAM
TCSBH
TCSBL
CSB
TSCCSH
TSCK
TRISE
TFALL
SCLK
TSCKH
TSCKL
SDIO
TSDIOS
TSDIOH
Figure 42: SPI Write Timing Diagram
13.2. SPI READ TIMING DIAGRAM
TCSBH
CSB
TSCCSH
TCSSCS
TSCK
TRISE
TFALL
SCLK
TSCKH
TSDIOS
TG3D
TSCKL
SDIO
TSDIOH
TZG3D
TG3ZD
GPIO1
Figure 43: SPI Read Timing Diagram
emPowerAudio™
Datasheet Revision 2.8
Page 92 of 110
June 2016
NAU8812
SYMBOL
TSCK
DESCRIPTION
MIN
80
35
35
---
TYP
---
MAX
---
UNIT
SCLK Cycle Time
ns
ns
ns
ns
ns
TSCKH
TSCKL
TRISE
SCLK High Pulse Width
SCLK Low Pulse Width
---
---
---
---
Rise Time for all SPI Signals
Fall Time for all SPI Signals
---
10
TFALL
---
---
10
CSb Falling Edge to 1st SCLK Falling Edge Setup Time (4
wire SPI only)
TCSSCS
30
---
---
ns
TSCCSH
TCSBL
Last SCLK Rising Edge to CSb Rising Edge Hold Time
CSb Low Time
30
30
30
20
20
---
---
---
---
---
---
---
---
---
---
ns
ns
ns
ns
ns
TCSBH
TSDIOS
TSDIOH
CSb High Time between CSb Lows
SDIO to SCLK Rising Edge Setup Time
SCLK Rising Edge to SDIO Hold Time
Delay Time from CSb Falling Edge to SO Active
(4 wire SPI Only)
TZG3D
--
--
15
ns
Delay Time from CSb Rising Edge to SO Tri-state (4 wire
SPI Only)
TG3ZD
TG3D
--
--
15
15
ns
ns
Delay Time from SCLK Falling Edge to SO (4 wire SPI Only)
Table 34: SPI Timing Parameters
---
---
emPowerAudio™
Datasheet Revision 2.8
Page 93 of 110
June 2016
NAU8812
13.3. 2-WIRE TIMING DIAGRAM
TSTAH
TSDIOS
TSDIOH
TSTAH
SDIO
SCLK
TSCKH
TFALL
TSCKL
TRISE
TSTAS
TSTOS
Figure 44: 2-Wire Timing Diagram
DESCRIPTION
SYMBOL
TSTAH
MIN
600
TYP
---
MAX
UNIT
START / Repeat START condition, SCLK falling edge to
SDIO falling edge hold timing
---
---
---
ns
ns
ns
Repeat START condition, SDIO rising edge to SCLK
falling edge setup timing
TSTAS
TSTOS
600
600
---
---
STOP condition, SDIO rising edge to SCLK rising edge
setup timing
TSCKH
TSCKL
TRISE
SCLK High Pulse Width
600
1.3
---
---
---
---
---
---
---
---
---
ns
us
ns
ns
ns
ns
SCLK Low Pulse Width
Rise Time for all 2-Wire Signals
Fall Time for all 2-Wire Signals
SDIO to SCLK Rising Edge DATA Setup Time
SCLK falling Edge to SDIO DATA Hold Time
Table 35: 2-WireTiming Parameters
300
300
---
TFALL
---
TSDIOS
TSDIOH
400
0
600
emPowerAudio™
Datasheet Revision 2.8
Page 94 of 110
June 2016
NAU8812
14. AUDIO INTERFACE TIMING DIAGRAM
14.1. AUDIO INTERFACE IN SLAVE MODE
TBCK
TRISE
TFALL
BCLK
(Slave)
TFSH
TBCKH
TFSH
TBCKL
TFSS
TFSS
FS
(Slave)
TDIS
TDIH
DACIN
TDOD
ADCOUT
Figure 45: Audio Interface Slave Mode Timing Diagram
14.2. AUDIO INTERFACE IN MASTER MODE
BCLK
(Master)
TFSD
TFSD
FS
(Master)
TDIS
TDIH
DACIN
TDOD
ADCOUT
Figure 46: Audio Interface in Master Mode Timing Diagram
emPowerAudio™
Datasheet Revision 2.8
Page 95 of 110
June 2016
NAU8812
14.3. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Audo Data)
TBCK
TRISE
TFALL
BCLK
(Slave)
TBCKH
TFSH
TFSH
TBCKL
TFSS
TFSS
FS
(Slave)
TDIS
TDIH
DACIN
MSB
TDOD
ADCOUT
MSB
Figure 47: PCM Audio Interface Slave Mode Timing Diagram
14.4. PCM AUDIO INTERFACE IN MASTER MODE (PCM Audo Data)
BCLK
(Master)
TFSD
TFSD
TFSD
FS
(Master)
TDIS
TDIH
DACIN
MSB
TDOD
MSB
ADCOUT
Figure 48: PCM Audio Interface Slave Mode Timing Diagram
emPowerAudio™
Datasheet Revision 2.8
Page 96 of 110
June 2016
NAU8812
14.5. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Time Slot Mode )
TBCK
TRISE
TFALL
BCLK
(Slave)
TBCKH
TFSH
TFSH
TBCKL
TFSS
TFSS
FS
(Slave)
TDIS
TDIH
DACIN
MSB
TDOD1
TDOD
ADCOUT
MSB
Figure 49: PCM Audio Interface Slave Mode (PCM Time Slot Mode )Timing Diagram
14.6. PCM AUDIO INTERFACE IN MASTER MODE (PCM Time Slot Mode )
BCLK
(Master)
TFSD
TFSD
FS
(Master)
TDIS
TDIH
DACIN
MSB
TDOD
ADCOUT
MSB
Figure 50: PCM Audio Interface Master Mode (PCM Time Slot Mode )Timing Diagram
emPowerAudio™
Datasheet Revision 2.8
Page 97 of 110
June 2016
NAU8812
SYMBOL
TBCK
DESCRIPTION
MIN
50
TYP
---
MAX
---
UNIT
BSCK Cycle Time (Slave Mode)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TBCKH
TBCKL
TFSS
TFSH
TFSD
TRISE
TFALL
TDIS
BSCK High Pulse Width (Slave Mode)
20
20
20
20
---
---
---
15
15
---
---
---
---
---
---
---
---
---
---
---
---
BSCK Low Pulse Width (Slave Mode)
---
fs to SCK Rising Edge Setup Time (Slave Mode)
SCK Rising Edge to fs Hold Time (Slave Mode)
fs to SCK falling to fs transition (Master Mode)
Rise Time for All Audio Interface Signals
Fall Time for All Audio Interface Signals
ADCIN to SCK Rising Edge Setup Time
SCK Rising Edge to ADCIN Hold Time
---
---
10
0.135TBCK
0.135TBCK
---
TDIH
---
TDOD
Delay Time from SCLK falling Edge to DACOUT
10
Table 36: Audio Interface Timing Parameters
14.7. System Clock (MCLK) Timing Diagram
TMCLKH
MCLK
TMCLKL
Figure 51: MCLK Timing Diagram
PARAMETER
MCLK Duty Cycle
SYMBOL
TMCLKDC
TEST CONDITIONS
MIN
TYP
MAX UNIT
40:60
60:40
MCLK High Pulse Width
TMCLKH
TMCLKL
20
20
---
---
---
---
ns
ns
MCLK Low Pulse Width
Table 37: MCLK Timing Parameter
emPowerAudio™
Datasheet Revision 2.8
Page 98 of 110
June 2016
NAU8812
14.8. µ-LAW ENCODE DECODE CHARACTERISTICS
Normalized
Digital Code
Normalized
Decode
Levels
Encode
Decision
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
8159
1
:
0
:
0
:
0
:
0
:
0
:
0
:
0
:
8031
7903
:
:
4319
1
:
0
:
0
:
0
:
1
:
1
:
1
:
1
:
4191
4063
:
:
2143
1
:
0
:
0
:
1
:
1
:
1
:
1
:
1
:
2079
2015
:
:
1055
1
:
0
:
1
:
0
:
1
:
1
:
1
:
1
:
1023
991
:
:
511
1
:
0
:
1
:
1
:
1
:
1
:
1
:
1
:
495
479
:
239
:
231
:
1
:
1
:
0
:
0
:
1
:
1
:
1
:
1
:
223
:
103
1
:
1
:
0
:
1
:
1
:
1
:
1
:
1
:
99
:
95
:
35
1
:
1
:
1
:
0
:
1
:
1
:
1
:
1
:
33
:
31
:
3
1
:
1
:
1
:
1
:
1
:
1
:
1
:
0
:
2
:
1
0
1
1
1
1
1
1
1
1
0
Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values
emPowerAudio™
Datasheet Revision 2.8
Page 99 of 110
June 2016
NAU8812
14.9. A-LAW ENCODE DECODE CHARACTERISTICS
Normalized
Digital Code
Normalized
Decode
Levels
Encode
Decision
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
4096
1
:
0
:
1
:
0
:
1
:
0
:
1
:
0
:
4032
3968
:
:
2176
1
:
0
:
1
:
0
:
0
:
1
:
0
:
1
:
2112
2048
:
:
1088
1
:
0
:
1
:
1
:
0
:
1
:
0
:
1
:
1056
1024
:
:
544
1
:
0
:
0
:
0
:
0
:
1
:
0
:
1
:
528
512
:
:
272
1
:
0
:
0
:
1
:
0
:
1
:
0
:
1
:
264
256
:
:
132
:
136
1
:
1
:
1
:
0
:
0
:
1
:
0
:
1
:
128
:
68
1
:
1
:
1
:
0
:
0
:
1
:
0
:
1
:
66
:
64
:
2
1
1
0
1
0
1
0
1
1
0
Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits
emPowerAudio™
Datasheet Revision 2.8
Page 100 of 110
June 2016
NAU8812
14.10. µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE
µ-Law
A-Law
Level
Sign bit
(D7)
Chord bits
(D6,D5,D4)
Step bits
(D3,D2,D1,D0)
Sign bit
(D7)
Chord bits
(D6,D5,D4)
Step bits
(D3,D2,D1,D0)
+ Full Scale
+ Zero
1
1
0
0
000
111
111
000
0000
1111
1111
0000
1
1
0
0
010
101
101
010
1010
0101
- Zero
0101
- Full Scale
1010
14.11.
µ-LAW / A-LAW OUTPUT CODES (DIGITAL MW)
µ-Law
A-Law
Sample
Sign bit
(D7)
Chord bits
(D6,D5,D4)
Step bits
(D3,D2,D1,D0)
Sign bit
(D7)
Chord bits
(D6,D5,D4)
Step bits
(D3,D2,D1,D0)
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
001
000
000
001
001
000
000
001
1110
1011
1011
1110
1110
1011
1011
1110
0
0
0
0
1
1
1
1
011
010
010
011
011
010
010
011
0100
0001
0001
0100
0100
0001
0001
0100
emPowerAudio™
Datasheet Revision 2.8
Page 101 of 110
June 2016
NAU8812
15. DIGITAL FILTER CHARACTERISTICS
TEST
CONDITIONS
PARAMETER
MIN
0
TYP
MAX
UNIT
ADC Filter
+/- 0.025dB
-6dB
0.454*fs
Passband
0.5*fs
Passband Ripple
Stopband
+/-0.025
dB
dB
0.546*fs
-60
Stopband
Attenuation
f > 0.546*fs
Group Delay
21/fs
ADC High Pass Filter
-3dB
3.7
High Pass Filter
Corner Frequency
-0.5dB
-0.1dB
10.4
21.6
Hz
DAC Filter
+/- 0.035dB
-6dB
0
0.454*fs
+/-0.035
Passband
0.5*fs
Passband Ripple
Stopband
dB
dB
0.546*fs
-55
Stopband
Attenuation
f > 0.546*fs
Group Delay
29/fs
Table 57 Digital Filter Characteristics
TERMINOLOGY
1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
3. Note that this delay applies only to the filters and does not include
emPowerAudio™
Datasheet Revision 2.8
Page 102 of 110
June 2016
NAU8812
Figure 53: ADC Filter Frequency Response
Figure 52: DAC Filter Frequency Response
Figure 54: DAC Filter Ripple
Figure 55: ADC Filter Ripple
emPowerAudio™
Datasheet Revision 2.8
Page 103 of 110
June 2016
NAU8812
16. TYPICAL APPLICATION
C9
4.7uF
C10
1uF
VREF
AUX
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C8
1uF
VDDSPK
VDDSPK
MIC -
MIC +
C7
1uF
VDDSPK
SPKOUT -
VSSSPK
VSSSPK
SPKOUT +
3
C4
4.7uF
R1
R2
1.2k ohm
1.2k ohm
MICBIAS
NC
VSS
4
C6
4.7uF
5
VDDA
VDDA
VSSA
VSSA
VDDC
VDDB
6
VSS
NAU8812
MONO AUDIO
CODEC
7
C5
1uF
MOUT
MODE
SDIO
8
VDDC
SSOP 28-Pin
9
VDDB
10
11
12
13
14
C2
C1
C3
4.7uF
4.7uF
4.7uF
VSSD
SCLK
VSS
CSb/GPIO
MCLK
ADCOUT
DACIN
FS
BCLK
Figure 56: Application Diagram 28-Pin SSOP
emPowerAudio™
Datasheet Revision 2.8
Page 104 of 110
June 2016
NAU8812
C8
1uF
VSS
C4
4.7uF
VDDSPK
C7
1uF
C9
4.7uF
C10
1uF
R2
1.2k ohm
R1
1.2k ohm
MICBIAS
C6
4.7uF
VSSSPK
VSSSPK
SPKOUT +
MOUT
NC
1
24
23
22
21
20
19
18
17
VDDA
VDDA
2
3
4
5
6
7
8
VSSA
VSSA
VDDL
VDDC
NAU8812
MONO AUDIO
CODEC
C11
10nF
C5
1uF
NC
VDDC
QFN 32-Pin
MODE
VDDB
VDDB
VSSD
SO
C1
C2
4.7uF
C3
4.7uF
SDIO
4.7uF
VSS
Figure 57: Application Diagram for 32-Pin QFN
Note 1: All non-polar capacitors are assumed to be low ESR type parts, such as with MLC construction or similar.
If capacitors are not low ESR, additional 0.1uF and/or 0.01uF capacitors may be necessary in parallel
with the bulk 4.7uF capacitors on the supply rails.
Note 2: Load resistors to ground on outputs may be helpful in some applications to insure a DC path for the
output capacitors to charge/discharge to the desired levels. If the output load is always present and the
output load provides a suitable DC path to ground, then the additional load resistors may not be
necessary. If needed, such load resistors are typically a high value, but a value dependent upon the
application requirements.
Note 3: To minimize pops and clicks, large polarized output capacitors should be a low leakage type.
Note 4: Depending on the microphone device and PGA gain settings, common mode rejection can be improved
by choosing the resistors on each node of the microphone such that the impedance presented to any
noise on either microphone wire is equal.
emPowerAudio™
Datasheet Revision 2.8
Page 105 of 110
June 2016
NAU8812
17. PACKAGE SPECIFICATION
17.1. 28 Pin SSOP
D
28
15
DTEAIL A
H
E
E
1
14
A
A2
b
SEATING PLANE
SEATING PLANE
L
Y
L1
e
b
A1
DETAIL A
DIMENSION IN MM DIMENSION IN INCH
MIN. NOM MAX. MIN. NOM MAX.
SYMBOL
0.079
2.00
A
A1
A2
b
0.05
1.65 1.75 1.85
0.002
0.065
0.069
0.073
0.015
0.010
0.22
0.09
0.38 0.009
0.25 0.004
c
10.20
5.30 5.60
7.80 8.20
0.65
10.05
5.00
0.395 0.401 0.407
0.197 0.209 0.220
10.35
D
E
HE
7.40
0.291 0.307 0.323
0.0256
e
L
L1
0.95
0.037
0.55 0.75
1.25
0.021 0.030
0.050
0.004
8
Y
0.10
8
0
0
emPowerAudio™
Datasheet Revision 2.8
Page 106 of 110
June 2016
NAU8812
32-Pin QFN
32
25
1
24
8
17
16
9
32
25
24
1
17
8
16
9
emPowerAudio™
Datasheet Revision 2.8
Page 107 of 110
June 2016
NAU8812
18. ORDERING INFORMATION
Nuvoton Part Number Description
NAU8812_ _
Package Material:
Pb-free Package
G
=
Package Type:
R
Y
=
=
28-Pin SSOP Package
32-Pin QFN Package
emPowerAudio™
Datasheet Revision 2.8
Page 108 of 110
June 2016
NAU8812
19. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
1.0
September 2009
Preliminary release
Updated Figure numbers
13 - 15
36
The word SPKBST was updated with VDDSPK
Figure 19 updated
1.1
1.2
November 2009
December 2009
38
Figure 20 updated
69
Description of CLKM and CLKIOEN is updated
Updated type on the VERSION
Note Added
108
3
13 - 15
66
Electrical Specification table format updated
Register 0x05 description updated
Register 0x06 description updated
67
1.3
1.4
1.5
January 2010
January 2010
February 2010
46 - 48
107
Control interface description updated
Package description updated
Figure 7 updated
22
14
63, 87
63, 87
4
Speaker THD for 2-stage updated
Bit-8 of register 0x46 deleted from the document.
Default value of register 0x47 updated
Block diagram updated
1.6
1.7
March 2010
April 2010
44
Table 24 updated
62
Table 34 updated
63, 86
Register 0x41 Reserved updated
47
63
79
97
Removed trailing clock cycle from SPI timing diagram
Corrected Register 0x38 Register name
Improved description of Mic Bias set up
Added System Clock Timing Diagram
2.0
2.1
January 2011
October 2013
15
93
Corrected Digital I/O voltages from DCVDD to DBVDD
Corrected 2 wire timing diagram
An additional remark of VDDSPK boost mode
Modify Figure29 Byte Write Sequence
13 – 15
2.2
2.7
2.8
Jan 2014
March 2016
June 2016
50
Modify Figure30 2-Wire Read Sequence
37
Add Important Notice
46
87
Revise f1 equation from * to /
Silicon Revision ID changed
Package infromation
108
emPowerAudio™
Datasheet Revision 2.8
Page 109 of 110
June 2016
NAU8812
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
emPowerAudio™
Datasheet Revision 2.8
Page 110 of 110
June 2016
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