74ABT646APW,118 [NXP]
74ABT646A - Octal bus transceiver/register; 3-state TSSOP2 24-Pin;
| 型号： | 74ABT646APW,118 |
| 厂家： | 
NXP |
| 描述： | 74ABT646A - Octal bus transceiver/register; 3-state TSSOP2 24-Pin 信息通信管理 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总19页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ABT646A
Octal bus transceiver/register; 3-state
Rev. 03 — 15 March 2010
Product data sheet
1. General description
The 74ABT646A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of
data directly from the input bus or the internal registers. Data on the A bus or B bus will be
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.
Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver
function. In the transceiver mode, data present at the high-impedance port may be stored
in either the A or B register or both.
The Select (SAB, SBA) pins determine whether data is stored or transferred through the
device in real-time. The DIR pin determines which bus receives data when OE is active
(LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register
and/or data from bus B may be stored in the A register. When an output function is
disabled, the input function is still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time. The examples in Figure 5
“Real time bus transfer and storage” on page 6 demonstrate the four fundamental bus
management functions that can be performed with the 74ABT646A.
2. Features and benefits
I Combines 74ABT245 and 74ABT373A type functions in one device
I Independent registers for A and B buses
I Multiplexed real-time and stored data
I Live insertion and extraction permitted
I Output capability: +64 mA to −32 mA
I Power-up 3-state
I Power-up reset
I Latch-up protection exceeds 500 mA per JESD78B class II level A
I ESD protection:
N HBM JESD22-A114F exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74ABT646AD
−40 °C to +85 °C SO24
plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
74ABT646ADB
−40 °C to +85 °C SSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74ABT646APW −40 °C to +85 °C TSSOP24 plastic thin shrink small outline package; 24 leads;
SOT355-1
body width 4.4 mm
4. Functional diagram
21
G3
3EN1[BA]
3
3EN2[AB]
22
G6
2
23
1
4
5
6
7
8
9
10 11
G7
C4
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
C5
1
2
SAB
DIR
20
4
≥1
6
4D
1
3
1
6
23
22
21
CPBA
SBA
OE
5D
7
≥1
2
1
7
5
6
19
18
17
16
15
14
13
B0 B1 B2 B3 B4 B5 B6 B7
7
20 19 18 17 16 15 14 13
8
001aae891
9
10
11
001aae892
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
2 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
21
OE
3
DIR
23
CPBA
22
SBA
1
CPAB
2
SAB
1 of 8 channels
1D
C1
Q
4
20
B0
A0
1D
C1
Q
5
A1
6
19
B1
18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
A2
7
A3
8
DETAIL A × 7
A4
9
A5
10
A6
11
A7
001aae894
Fig 3. Logic diagram
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
3 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
5. Pinning information
5.1 Pinning
74ABT646A
1
2
24
23
22
21
20
19
18
17
16
15
14
13
CPAB
SAB
DIR
A0
V
CC
CPBA
3
SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
4
5
A1
6
A2
7
A3
8
A4
9
A5
10
11
12
A6
A7
GND
001aae890
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
1
Description
CPAB
A to B clock input
SAB
2
A to B select input
DIR
3
direction control input
data input/output (A side)
ground (0 V)
A0, A1, A2, A3, A4, A5, A6, A7
4, 5, 6, 7, 8, 9, 10, 11
12
GND
B0, B1, B2, B3, B4, B5, B6, B7
20, 19, 18, 17, 16, 15, 14, 13
data input/output (B side)
output enable input (active LOW)
B to A select input
OE
21
22
23
24
SBA
CPBA
VCC
B to A clock input
positive supply voltage
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
4 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
6. Functional description
Table 3.
Inputs
OE
Function table[1]
Data I/O
An
Operating mode
Bn
DIR
CPAB
CPBA
SAB
SBA
X
X
↑
X
X
X
input
unspecified store A, B unspecified
output[2]
X
X
X
↑
X
X
unspecified input
output[2]
store B, A unspecified
H
H
L
L
L
L
X
X
L
↑
↑
X
X
X
X
L
X
X
L
input
input
output
output
input
input
input
input
input
input
output
output
store A and B data
H or L
H or L
isolation, hold storage
real time B data to A bus
stored B data to A bus
real time A data to B bus
stored A data to B bus
X
X
L
X
H or L
H
X
X
H
H
X
X
X
H or L
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH clock transition;
[2] The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled,
i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
5 of 19
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A OR B
A
B
A
B
A
B
A
B
OE
L
DIR CPAB CPBA SAB SBA
OE
L
DIR CPAB CPBA SAB SBA
OE
L
L
DIR CPAB CPBA SAB SBA
OE
L
L
DIR CPAB CPBA SAB SBA
L
X
X
X
L
H
X
X
L
X
H
L
X
X
X
X
X
X
X
L
H
X
H/L
H/L
X
X
H
H
X
X
H
X
001aae893
Fig 5. Real time bus transfer and storage
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−1.2
−0.5
−18
−50
-
Max
+7.0
+7.0
+5.5
-
Unit
V
supply voltage
[1]
[1]
input voltage
V
VO
output voltage
output in OFF-state or HIGH-state
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
mA
mA
mA
°C
°C
IOK
IO
VO < 0 V
-
output in LOW-state
128
150
+150
[2]
Tj
junction temperature
storage temperature
-
Tstg
−65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
4.5
0
Typ
Max
5.5
VCC
-
Unit
V
supply voltage
-
-
-
-
-
-
-
-
VI
input voltage
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
2.0
-
V
VIL
0.8
-
V
IOH
−32
-
mA
mA
ns/V
°C
IOL
64
∆t/∆V
Tamb
0
10
in free air
−40
+85
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
7 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
9. Static characteristics
Table 6.
Static characteristics
Symbol Parameter
Conditions
25 °C
−40 °C to 85 °C Unit
Min Typ Max
Min
Max
VIK
input clamping voltage
VCC = 4.5 V; IIK = −18 mA
VI = VIL or VIH
−1.2 −0.9
-
−1.2
-
V
VOH
HIGH-level output
voltage
VCC = 4.5 V; IOH = −3 mA
VCC = 5.0 V; IOH = −3 mA
VCC = 4.5 V; IOH = −32 mA
2.5
3.0
2.0
-
3.0
3.5
2.4
-
-
-
2.5
3.0
2.0
-
-
V
V
V
V
-
-
VOL
LOW-level output voltage VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
0.3 0.55
0.55
[1]
VOL(pu) power-up LOW-level
output voltage
VCC = 5.5 V; IO = 1 mA;
VI = GND or VCC
-
-
0.13 0.55
-
-
0.55
V
II
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
control pins
±0.0 ±1.0
±1.0 µA
1
data pins
-
-
-
±5 ±100
±5.0 ±100
±5.0 ±50
-
-
-
±100 µA
±100 µA
±50 µA
IOFF
power-off leakage current VCC = 0 V; VI or VO ≤ 4.5 V
[2]
IO(pu/pd) power-up/power-down
output current
VCC = 2.1 V; VO = 0.5 V;
VI = GND or VCC; OE HIGH
IOZ
OFF-state output current VCC = 5.5 V; VI = VIL or VIH
VO = 2.7 V
VO = 0.5 V
-
-
-
5.0
−5.0 −50
5.0 50
50
-
-
-
50
−50 µA
50 µA
µA
ILO
output leakage current
VCC = 5.5 V; HIGH-state;
VO = 5.5 V; VCC = 5.5 V;
VI = GND or VCC
[3][5]
IO
output current
supply current
VCC = 5.5 V; VO = 2.5 V
VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state
−180 −65 −40
−180
−40 mA
250 µA
ICC
-
-
-
-
110 250
20 30
110 250
-
-
-
-
outputs LOW-state
30
mA
outputs disabled
250 µA
[4]
∆ICC
additional supply current per input pin; VCC = 5.5 V; one input
at 3.4 V; other inputs at VCC or GND
0.6
1.5
1.5
mA
CI
input capacitance
control pins; VI = 0 V or VCC
-
-
4
7
-
-
-
-
-
-
pF
pF
CI/O
input/output capacitance I/O pins; outputs disabled; VO = 0 V
or VCC
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a
transition time of up to 100 µs is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
[5] This data sheet limit may vary among suppliers.
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
8 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 11.
Symbol Parameter Conditions
25 °C; VCC = 5.0 V −40 °C to +85 °C; Unit
V
CC = 5.0 V ± 0.5 V
Min Typ Max
Min
125
2.2
Max
-
fmax
tPLH
maximum frequency see Figure 6
125 350
-
MHz
ns
LOW to HIGH
CPAB to Bn or CPBA to An;
see Figure 6
2.2
3.9
5.1
5.6
propagation delay
An to Bn or Bn to An; see Figure 7
1.5
1.5
1.7
3.2
3.8
4.4 5.2[1]
4.3
5.1
1.5
1.5
1.7
4.8
6.5
5.6
ns
ns
ns
SAB to Bn or SBA to An; see Figure 7
tPHL
HIGH to LOW
CPAB to Bn or CPBA to An;
see Figure 6
propagation delay
An to Bn or Bn to An; see Figure 7
SAB to Bn or SBA to An; see Figure 7
OE to An or Bn; see Figure 8
DIR to An or Bn; see Figure 8
OE to An or Bn; see Figure 9
DIR to An or Bn; see Figure 9
OE to An or Bn; see Figure 8
DIR to An or Bn; see Figure 8
OE to An or Bn; see Figure 9
DIR to An or Bn; see Figure 9
An to CPAB, Bn to CPBA; see Figure 10
An to CPAB, Bn to CPBA; see Figure 10
An to CPAB, Bn to CPBA; see Figure 10
An to CPAB, Bn to CPBA; see Figure 10
CPAB, CPBA; see Figure 6
1.5
1.5
1.5
1.5
3.0
2.5
1.5
1.5
1.5
1.5
3.0
3.0
3.7
4.4 5.3[1]
4.6
1.5
1.5
1.5
1.2
3.0
2.5
1.5
1.5
1.5
1.5
3.0
3.0
0.0
0.0
4.0
4.0
5.4
5.9
6.3
6.7
8.8
9.5
5.3[1]
5.7
4.5
6.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPZH
tPZL
tPHZ
tPLZ
OFF-state to HIGH
propagation delay
3.5
3.9
4.5
4.7
5.3
5.7
7.4
9.0
OFF-state to LOW
propagation delay
HIGH to OFF-state
propagation delay
4.0 4.8[1]
4.0
3.3
3.5
0.7
0.7
5.0
LOW to OFF-state
propagation delay
4.0
4.7
tsu(H)
tsu(L)
th(H)
th(L)
tWH
set-up time HIGH
set-up time LOW
hold time HIGH
hold time LOW
-
-
-
-
-
-
-
+0.0 −0.5
+0.0 −0.5
-
-
pulse width HIGH
pulse width LOW
4.0
4.0
0.9
1.4
-
tWL
LE; see Figure 6
-
[1] This data sheet limit may vary among suppliers.
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
9 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
11. Waveforms
1 / f
max
V
I
CPBA or
CPAB
V
V
V
M
M
M
GND
t
t
WL
WH
t
PLH
t
PHL
V
OH
An or Bn
V
V
M
M
V
OL
001aae839
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay clock input to output and clock pulse width, maximum clock frequency
V
I
SBA or SAB,
An or Bn
V
V
M
M
GND
t
t
PHL
PLH
V
OH
An or Bn
V
M
V
M
V
OL
001aae895
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay, SAB to Bn or SBA to An, An to Bn or Bn to An
V
I
OE, DIR
An or Bn
V
V
M
M
GND
t
t
PHZ
PZH
V
OH
V
− 0.3 V
OH
V
M
GND
001aae896
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
10 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
V
I
OE, DIR
An or Bn
V
V
M
M
GND
3.5 V
t
t
PLZ
PZL
V
M
V
+ 0.3 V
OL
V
OL
001aae898
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level
V
I
V
V
V
V
M
An, Bn
M
M
M
GND
t
t
t
t
h(L)
su(H)
h(H)
su(L)
t
WL
V
I
CPBA or
CPAB
V
V
M
M
GND
001aae849
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Data set-up and hold times
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
11 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
EXT
V
V
M
M
V
CC
10 %
10 %
0 V
R
L
V
V
O
I
t
t
r
f
G
DUT
t
t
f
r
V
I
R
T
C
L
R
L
90 %
90 %
positive
pulse
V
M
V
M
mna616
10 %
10 %
0 V
t
W
001aai298
a. Input pulse definition
b. Test circuit
Test data is given in Table 8.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 11. Load circuitry for switching times
Table 8.
Input
VI
Test data
Load
CL
VEXT
fI
tW
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
tPZL, tPLZ
7.0 V
3.0 V
1 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
open
74ABT646A_3
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
12 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 12. Package outline SOT137-1 (SO24)
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
13 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT340-1
MO-150
Fig 13. Package outline SOT340-1 (SSOP24)
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
14 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 14. Package outline SOT355-1 (TSSOP24)
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
15 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
13. Abbreviations
Table 9.
Acronym
BiCMOS
DUT
Abbreviations
Description
Bipolar Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 10. Revision history
Document ID
74ABT646A_3
Modifications:
Release date
20100315
Data sheet status
Change notice
Supersedes
Product data sheet
-
74ABT646A_2
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12
“Package outline”.
74ABT646A_2
74ABT646A_1
19980217
19950906
Product specification
Product specification
-
-
74ABT646A_1
-
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
16 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
suitable for use in medical, military, aircraft, space or life support equipment,
15.2 Definitions
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
17 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
18 of 19
74ABT646A
NXP Semiconductors
Octal bus transceiver/register; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 March 2010
Document identifier: 74ABT646A_3
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