74ABT823DB-T [NXP]
ABT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, 5.30 MM, PLASTIC, MO-150, SOT340-1, SSOP-24;
| 型号： | 74ABT823DB-T |
| 厂家： | 
NXP |
| 描述： | ABT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, 5.30 MM, PLASTIC, MO-150, SOT340-1, SSOP-24 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总19页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
Rev. 02 — 7 February 2005
Product data sheet
1. General description
The 74ABT823 bus interface register is designed to eliminate the extra packages required
to buffer existing registers and provide extra data width for wider data and address paths
of buses carrying parity.
The 74ABT823 is a 9-bit wide buffered register with clock enable input (CE) and master
reset input (MR) which are ideal for parity bus interfacing in systems using many
microprocessors.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output Q of the flip-flop.
2. Features
■ High-speed parallel registers with positive edge-triggered D-type flip-flops
■ Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
■ Output capability: +64 mA and −32 mA
■ Latch-up protection:
◆ JESD78: exceeds 500 mA
■ ESD protection:
◆ MIL STD 883 method 3015: exceeds 2000 V
◆ Machine model: exceeds 200 V
■ Power-on 3-state
■ Power-on reset
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
4.3
4.4
4
Max Unit
tPLH
tPHL
CI
propagation delay CP to Qn CL = 50 pF; VCC = 5 V
propagation delay CP to Qn CL = 50 pF; VCC = 5 V
-
-
-
-
-
-
-
-
ns
ns
pF
pF
input capacitance
output capacitance
VI = 0 V or VCC
CO
outputs disabled;
VO = 0 V or VCC
7
ICC
quiescent supply current
outputs 3-state;
-
0.5
-
µA
VCC = 5.5 V;
VI = GND or VCC
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
4. Ordering information
Table 2:
Type number Package
Temperature range Name
Ordering information
Description
Version
74ABT823N
74ABT823D
−40 °C to +85 °C
−40 °C to +85 °C
DIP24
SO24
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
SOT137-1
plastic small outline package; 24 leads;
body width 7.5 mm
74ABT823DB −40 °C to +85 °C
74ABT823PW −40 °C to +85 °C
SSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
SOT355-1
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
5. Functional diagram
1
EN
11
R
11
1
14
13
G1
1C2
MR OE
2
3
23
22
21
20
19
18
17
16
15
D0
D1
D2
D3
D4
D5
D6
D7
D8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
4
2
23
2D
5
3
4
5
22
21
20
6
7
8
9
6
7
19
18
17
16
15
10
CP CE
8
13 14
9
001aaa847
10
001aaa848
Fig 1. Logic symbol
Fig 2. IEC logic symbol
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
2 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
D0
D1
D2
D3
D4
MR
CE
R
R
R
R
R
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF0
CP
FF1
CP
FF2
CP
FF3
CP
FF4
CP
OE
Q0
Q1
Q2
Q3
Q4
D5
D6
D7
D8
R
R
R
R
D
Q
D
Q
D
Q
D
Q
CP
FF5
CP
FF6
CP
FF7
CP
FF8
Q5
Q6
Q7
Q8
001aac444
Fig 3. Logic diagram
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
3 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
6. Pinning information
6.1 Pinning
V
1
2
24
23
22
21
20
19
18
17
16
15
14
13
OE
D0
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
CP
3
D1
4
D2
5
D3
6
D4
823
7
D5
8
D6
9
D7
10
11
12
D8
MR
GND
001aaa845
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
OE
D0
Pin description
Pin
1
Description
output enable input (active LOW)
data input 0
2
D1
3
data input 1
D2
4
data input 2
D3
5
data input 3
D4
6
data input 4
D5
7
data input 5
D6
8
data input 6
D7
9
data input 7
D8
10
11
12
13
14
15
16
17
18
19
20
21
data input 8
MR
GND
CP
master reset input (active LOW)
ground (0 V)
clock pulse input (active rising edge)
clock enable input (active LOW)
data output 8
CE
Q8
Q7
data output 7
Q6
data output 6
Q5
data output 5
Q4
data output 4
Q3
data output 3
Q2
data output 2
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
4 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
Table 3:
Symbol
Q1
Pin description …continued
Pin
22
23
24
Description
data output 1
Q0
data output 0
VCC
positive supply voltage
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Operating mode
Input
OE
L
Output
MR
L
CE
X
CP
X
Dn
X
h
Qn
L
Clear
Load and read data L
H
L
↑
H
l
L
Hold
L
H
X
H
X
NC
X
X
X
NC
Z
High-impedance
H
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
↑ = LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
5 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−1.2
−0.5
Max
+7.0
+7.0
+5.5
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
IIK
input diode current
output diode current
output current
VI < 0 V
-
−18
−50
128
150
+150
mA
mA
mA
°C
IOK
IO
VO < 0 V
-
output in LOW-state
-
[2]
Tj
junction temperature
storage temperature
-
Tstg
−65
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 150 °C.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
Conditions
Min
4.5
0
Typ
Max
5.5
VCC
-
Unit
V
VCC
VI
supply voltage
-
-
-
-
-
-
-
-
input voltage
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise or fall rate
ambient temperature
2.0
-
V
VIL
0.8
−32
64
V
IOH
-
mA
mA
ns/V
°C
IOL
-
∆t/∆V
Tamb
0
5
in free air
−40
+85
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
6 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max Unit
Tamb = 25 °C
VIK
input diode voltage
VCC = 4.5 V; IIK = −18 mA
-
−0.9 −1.2
V
VOH
HIGH-level output voltage
VI = VIL or VIH
VCC = 4.5 V; IOH = −3 mA
2.5
2.0
3.0
-
2.9
2.4
3.4
-
-
-
V
V
V
V
V
VCC = 4.5 V; IOH = −32 mA
VCC = 5.0 V; IOH = −3 mA
VOL
LOW-level output voltage
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH
VCC = 5.5 V; IO = 1 mA; VI = GND or VCC
0.42 0.55
0.13 0.55
[1]
[2]
VRST
restart LOW-level output
voltage
-
ILI
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
-
-
-
±0.01 ±1.0 µA
±5.0 ±100 µA
IOFF
power-down leakage current VCC = 0.0 V; VO or VI ≤ 4.5 V
IPU, IPD power-up or power-down
down 3-state output current
VCC = 2.0 V; VO = 0.5 V; VI = GND or VCC
OE = VCC
;
±5.0 ±50
µA
V
IOZ
3-state output current
VCC = 5.5 V; VI = VIL or VIH
output HIGH-state at VO = 2.7 V
output LOW-state at VO = 0.5 V
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC
-
-
-
5.0
−5.0 −50
5.0 50
50
µA
µA
µA
ICEX
output HIGH-state leakage
current
[3]
IO
output current
VCC = 5.5 V; VO = 2.5 V
VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state
−50
−100 −180 mA
ICC
quiescent supply current
-
-
-
-
0.5
27
250
34
µA
outputs LOW-state
mA
µA
outputs 3-state
0.5
0.5
250
1.5
[4]
∆ICC
additional quiescent supply
current per input pin
VCC = 5.5 V; one input at 3.4 V and other
inputs at VCC or GND
mA
CI
input capacitance
output capacitance
VI = 0 V or VCC
-
-
4
7
-
-
pF
pF
CO
outputs disabled; VO = 0 V or VCC
Tamb = −40 °C to +85 °C
VIK
input diode voltage
VCC = 4.5 V; IIK = −18 mA
-
-
−1.2
V
VOH
HIGH-level output voltage
VI = VIL or VIH
VCC = 4.5 V; IOH = −3 mA
2.5
2.0
3.0
-
-
-
-
-
-
-
V
V
V
V
V
VCC = 4.5 V; IOH = −32 mA
VCC = 5.0 V; IOH = −3 mA
-
-
VOL
LOW-level output voltage
VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH
VCC = 5.5 V; IO = 1 mA; VI = GND or VCC
0.55
0.55
[1]
[2]
VRST
restart LOW-level output
voltage
-
ILI
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
-
-
-
-
-
-
±1.0 µA
±100 µA
IOFF
power-down leakage current VCC = 0.0 V; VO or VI ≤ 4.5 V
IPU, IPD power-up or power-down
down 3-state output current
VCC = 2.0 V; VO = 0.5 V; VI = GND or VCC
OE = VCC
;
±50
µA
V
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
7 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max Unit
IOZ
3-state output current
VCC = 5.5 V; VI = VIL or VIH
output HIGH-state at VO = 2.7 V
output LOW-state at VO = 0.5 V
VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC
-
-
-
-
-
-
-
50
µA
µA
µA
−50
50
ICEX
output HIGH-state leakage
current
[3]
IO
output current
VCC = 5.5 V; VO = 2.5 V
VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state
−50
-
-
-
-
-
-
−180 mA
ICC
quiescent supply current
-
-
-
-
250
34
µA
outputs LOW-state
mA
µA
outputs 3-state
250
1.5
[4]
∆ICC
additional quiescent supply
current per input pin
VCC = 5.5 V; one input at 3.4 V and other
inputs at VCC or GND
mA
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a
transition time of up to 100 µs is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
11. Dynamic characteristics
Table 8:
Dynamic characteristics
GND = 0 V; for test circuit see Figure 9.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Tamb = 25 °C; VCC = 5 V
tPLH
tPHL
propagation delay CP to Qn
propagation delay
see Figure 5
2.1
4.3
5.9
ns
CP to Qn
see Figure 5
see Figure 6
see Figure 8
see Figure 8
see Figure 8
see Figure 8
see Figure 5
2.2
2.0
1.0
2.2
2.7
2.5
2.9
4.4
4.1
3.0
4.1
4.8
5.0
1.9
6.1
6.3
4.5
5.6
6.2
6.4
-
ns
ns
ns
ns
ns
ns
ns
MR to Qn
tPZH
tPZL
tPHZ
tPLZ
tWH
tWL
output enable time to HIGH-level
output enable time to LOW-level
output disable time from HIGH-level
output disable time from LOW-level
pulse width HIGH of CP
pulse width LOW
clock pulse CP
see Figure 5
see Figure 6
3.8
5.5
2.8
4.0
-
-
ns
ns
master reset MR
tsu(H)
set-up time HIGH
Dn to CP
see Figure 7
see Figure 7
2.1
2.0
0.5
-
-
ns
ns
CE to CP
−0.5
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
8 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
Table 8:
Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 9.
Symbol Parameter
Conditions
Min
Typ
Max Unit
tsu(L)
th(H)
th(L)
set-up time LOW
Dn to CP
see Figure 7
see Figure 7
2.1
3.3
0.2
1.5
-
-
ns
ns
CE to CP
hold time HIGH
Dn to CP
see Figure 7
see Figure 7
1.3
1.0
0.0
-
-
ns
ns
CE to CP
−1.4
hold time LOW
Dn to CP
see Figure 7
see Figure 7
see Figure 6
see Figure 5
1.3
2.0
2.5
125
−0.3
0.7
-
-
-
-
ns
CE to CP
ns
trec
recovery time MR to CP
maximum clock frequency
0.6
ns
fmax
200
MHz
Tamb = −40 °C to +85 °C; VCC = 5 V ± 0.5 V
tPLH
tPHL
propagation delay CP to Qn
propagation delay
CP to Qn
see Figure 5
2.1
-
6.8
ns
see Figure 5
see Figure 6
see Figure 8
see Figure 8
see Figure 8
see Figure 8
see Figure 5
2.2
2.0
1.0
2.2
2.7
2.5
2.9
-
-
-
-
-
-
-
6.7
7.1
5.3
6.3
6.9
6.9
-
ns
ns
ns
ns
ns
ns
ns
MR to Qn
tPZH
tPZL
tPHZ
tPLZ
tWH
tWL
output enable time to HIGH-level
output enable time to LOW-level
output disable time from HIGH-level
output disable time from LOW-level
pulse width HIGH of CP
pulse width LOW
clock pulse CP
see Figure 5
see Figure 6
3.8
5.5
-
-
-
-
ns
ns
master reset MR
set-up time HIGH
Dn to CP
tsu(H)
tsu(L)
th(H)
th(L)
see Figure 7
see Figure 7
2.1
2.0
-
-
-
-
ns
ns
CE to CP
set-up time LOW
Dn to CP
see Figure 7
see Figure 7
2.1
3.3
-
-
-
-
ns
ns
CE to CP
hold time HIGH
Dn to CP
see Figure 7
see Figure 7
1.3
1.0
-
-
-
-
ns
ns
CE to CP
hold time LOW
Dn to CP
see Figure 7
see Figure 7
see Figure 6
see Figure 5
1.3
2.0
2.5
125
-
-
-
-
-
-
-
-
ns
CE to CP
ns
trec
recovery time MR to CP
maximum clock frequency
ns
fmax
MHz
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
9 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
12. Waveforms
1/f
max
V
I
CP input
V
M
GND
t
t
WL
WH
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aac445
VM = 1.5 V.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 5. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and
maximum clock (CP) frequency
V
I
V
M
MR input
GND
t
t
rec
WL
V
I
CP input
V
M
GND
t
PHL
V
OH
V
Qn output
M
V
OL
001aac446
VM = 1.5 V.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Master reset (MR) pulse width, propagation delay master reset (MR) to output (Qn)
and recovery time master reset (MR) to clock (CP)
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
10 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
V
I
V
M
CP input
GND
t
t
su(L)
su(H)
t
t
h(L)
h(H)
V
I
V
Dn, CE input
M
GND
001aac447
VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 7. Set-up and hold times data output (Dn) to clock (CP) and clock enable input (CE) to
clock (CP)
V
I
OE input
Qn output
Qn output
V
M
t
GND
t
PZL
PLZ
V
V
M
M
V
+ 0.3 V
OL
V
OL
t
t
PHZ
PZH
V
OH
V
− 0.3 V
OH
0 V
001aac448
VM = 1.5 V.
VOL and VOH are typical voltage output drop that occur with the output load.
Fig 8. 3-state output (Qn) enable and disable times
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
11 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
0 V
t
(t )
f
t
(t )
TLH r
THL
t
(t )
t
(t )
THL f
TLH
r
V
I
90 %
positive
pulse
V
M
V
M
10 %
10 %
0 V
t
W
001aac221
VM = 1.5 V.
a. Input pulse definition
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
b. Test circuit
Fig 9. Load circuitry for switching times
Table 9:
Input
VI
Test data
Load
CL
VEXT
fi
1 MHz
tW
tr, tf
RL
tPHZ, tPZH tPLZ, tPZL tPLH, tPHL
3.0 V
500 ns
2.5 ns
50 pF
500 Ω
open
7.0 V
open
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
12 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
13. Package outline
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
D
M
E
seating
plane
A
2
A
L
A
1
c
w M
e
Z
b
1
(e )
1
M
H
b
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
min.
max.
max.
1.63
1.14
0.56
0.43
0.36
0.25
31.9
31.5
6.73
6.25
3.51
3.05
8.13
7.62
10.03
7.62
4.7
0.38
3.94
2.54
0.1
7.62
0.3
0.25
0.01
2.05
0.064
0.045
0.022
0.017
0.014
0.010
1.256
1.240
0.265
0.246
0.138
0.120
0.32
0.30
0.395
0.300
inches
0.185
0.015
0.155
0.081
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-03-12
SOT222-1
MS-001
Fig 10. Package outline SOT222-1 (DIP24)
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
13 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 11. Package outline SOT137-1 (SO24)
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
14 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT340-1
MO-150
Fig 12. Package outline SOT340-1 (SSOP24)
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
15 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 13. Package outline SOT355-1 (TSSOP24)
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
16 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
14. Revision history
Table 10: Revision history
Document ID
74ABT823_2
Modifications:
Release date Data sheet status
20050207 Product data sheet
Change notice Doc. number
Supersedes
-
9397 750 14551 74ABT823_1
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Section 2 “Features”: modified ‘JEDEC Std. 17’ into ‘JESD78’.
• Table 8 “Dynamic characteristics”: changed min value of tPLZ from 2.8 ns into 2.5 ns for both
conditions at Tamb = 25 °C; VCC = 5.0 V and at Tamb = −40 °C to +85 °C; VCC = 5.0 V ± 0.5 V
74ABT823_1
19960314
Product specification
-
-
-
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
17 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14551
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 February 2005
18 of 19
74ABT823
Philips Semiconductors
9-bit D-type flip-flop with reset and enable; 3-state
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information . . . . . . . . . . . . . . . . . . . . 18
9
10
11
12
13
14
15
16
17
18
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 7 February 2005
Document number: 9397 750 14551
Published in The Netherlands
相关型号：
74ABT823PW-T
IC ABT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, 4.40 MM, PLASTIC, MO-153, SOT355-1, TSSOP-24, Bus Driver/Transceiver
NXP
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