74ABT833DB,118 [NXP]
IC ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOT-108, SSOP-24, Bus Driver/Transceiver;型号: | 74ABT833DB,118 |
厂家: | NXP |
描述: | IC ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOT-108, SSOP-24, Bus Driver/Transceiver 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
文件: | 总13页 (文件大小:137K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT833
Octal transceiver with parity
generator/checker (3-State)
Product data
2002 Dec 17
Supersedes data of 1993 Jun 21
Philips
Semiconductors
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
FEATURES
• Low static and dynamic power dissipation with high speed and
When Output Enable A (OEA) is HIGH, it will place the A outputs in
a high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
high output drive
• Open-collector ERROR output with flag register
• Output capability: +64 mA / –32 mA
The parity generator creates an odd parity output (PARITY) when
OEB is LOW. When OEA is LOW, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
LOW-to-HIGH transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR) will go LOW. The error flag register is cleared with a LOW
pulse on the CLEAR input.
• Latch-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up/down 3-State
• Live insertion/extraction permitted
If both OEA and OEB are LOW, data will flow from the A bus to the
B bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
CONDITIONS
= 25 °C; GND = 0 V
SYMBOL
PARAMETER
TYPICAL
3.4
UNIT
ns
T
amb
t
t
Propagation delay
An to Bn or Bn to An
PLH
PHL
C = 50 pF; V = 5 V
L
CC
t
t
Propagation delay
An to PARITY
PLH
PHL
C = 50 pF; V = 5 V
7.4
ns
L
CC
C
Input capacitance
I/O capacitance
V = 0 V or V
CC
4
7
pF
pF
µA
IN
I
C
Outputs disabled; V = 0 V or V
O CC
I/O
I
Total supply current
Outputs disabled; V = 5.5 V
50
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
PART NUMBER
74ABT833D
DWG NUMBER
SOT137-1
24-Pin plastic SO
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT833DB
74ABT833PW
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
OEA
A0
1
2
3
4
5
24
23
22
21
20
V
CC
2, 3, 4, 5,
6, 7, 8, 9
A0 – A7
A port 3-State inputs/outputs
B0
B1
B2
B3
23, 22, 21, 20,
19, 18, 17, 16
A1
B0 – B7
B port 3-State inputs/outputs
A2
OEA
OEB
1
Enables the A outputs when LOW
Enables the B outputs when LOW
Parity output/input
A3
14
15
10
6
7
8
9
19 B4
18 B5
A4
A5
TOP VIEW
PARITY
ERROR
Error output (open collector)
A6
A7
17
16
15
14
B6
Clears the error flag register
when LOW
CLEAR
11
B7
ERROR 10
CLEAR 11
GND 12
PARITY
OEB
CP
13
12
24
Clock input
GND
Ground (0 V)
13 CP
V
CC
Positive supply voltage
SA00212
2
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
LOGIC SYMBOL
2
3
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7
OEB
14
1
15
10
PARITY
OEA
CLEAR
CP
11
13
ERROR
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
SA00213
FUNCTION TABLE
INPUTS
OUTPUTS
Bn
An
Σ of Highs
Bn + Parity
Σ of Highs
MODE
OEB
OEA
An
PARITY
Odd
Even
L
H
A data to B bus and generate odd parity output
L
H
(output)
(input)
An
1
B data to A bus and check for parity error
H
H
L
(output)
X
X
X
Bn
Z
(input)
Z
(input)
Z
2
A bus and B bus disabled
H
Odd
Even
H
L
A data to B bus and generate inverted parity output
L
L
(output)
(input)
An
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is LOW if the sum of A inputs is even or HIGH if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
CP
Internal node
Point ”P”
Output
Bn + Parity
Σ of Highs
Pre–state
ERRORn–1
ERROR
OUTPUT
MODE
CLEAR
H
H
H
H
L
↑
↑
Odd
Even
X
H
L
H
X
L
H
L
Sample
X
↑
X
X
X
L
Hold
X
X
X
NC
H
Clear
X
X
H
L
X
NC
Z
=
=
=
=
=
=
=
HIGH voltage level steady state
LOW voltage level steady state
Don’t care
No change
High impedance “off” state
LOW-to-HIGH clock transition
Not a LOW-to-HIGH clock transition
↑
↑
3
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
LOGIC DIAGRAM
8
8
A0 – A7
B0 – B7
8
OEB
OEA
PARITY
8
8
MUX
B
9–bit
Odd
Parity
Tree
}
}
9
”P”
A
Sel A/B
D
R
ERROR
CP
CLEAR
SA00214
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0 V
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0 V
mA
V
OK
3
V
DC output voltage
output in Off or HIGH state
output in LOW state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
5.5
V
DC supply voltage
Input voltage
V
V
CC
V
V
CC
I
V
HIGH-level input voltage
LOW-level input voltage
2.0
V
IH
V
0.8
5.5
–32
64
V
IL
V
HIGH-level output voltage, ERROR
HIGH-level output current
V
OH
OH
I
mA
mA
ns/V
°C
I
OL
LOW-level output current
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature range
0
5
T
amb
–40
+85
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40 °C
to +85 °C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25 °C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
= 4.5 V; I = –18 mA
–0.9
–1.2
–1.2
V
µA
V
IK
CC
CC
CC
CC
IK
HIGH-level output current
ERROR ONLY
I
= 5.5 V; V = 5.5 V; V = V or V
IH
20
20
OH
OH
I
IL
= 4.5 V; I = –3 mA; V = V or V
2.5
3.0
2.0
3.5
4.0
2.5
3.0
2.0
OH
I
IL
IH
IH
HIGH-level output voltage
All outputs except ERROR
V
OH
= 5.0 V; I = –3 mA; V = V or V
V
OH
I
IL
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V; I = –32 mA; V = V or V
IH
2.6
V
V
OH
I
IL
V
OL
LOW-level output voltage
= 4.5 V; I = 64 mA; V = V or V
IH
0.42
0.55
0.55
±1.0
±100
±100
OL
I
IL
I
Input leakage Control pins
= 5.5 V; V = GND or 5.5 V
±0.01 ±1.0
µA
µA
V
I
I
current
Data pins
= 5.5 V; V = GND or 5.5 V
±5
±100
±100
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0 V; V or V ≤ 4.5 V
±5.0
OFF
I
O
V
CC
V
OE
= 2.0 V; or V = 0.5 V; V = GND or V
CC
;
O
I
I
I
±5.0
±50
±50
V
PU PD
3
output current
= Don’t care
I
+ I
+ I
3-State output HIGH current
3-State output LOW current
Output High leakage current
V
V
V
V
V
V
V
V
= 5.5 V; V = 2.7 V; V = V or V
5.0
–5.0
5.0
–80
50
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
µA
IH
OZH
OZL
CC
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 5.5 V; V = 0.5 V; V = V or V
O I IL
IL
I
= 5.5 V; V = 5.5 V; V = GND or V
O I CC
CEX
1
I
O
Output current
= 5.5 V; V = 2.5 V
–50
–180
250
30
–50
–180
250
30
O
I
= 5.5 V; Outputs HIGH, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5 V; Outputs LOW, V = GND or V
20
CCL
I
CC
I
= 5.5 V; Outputs 3-State; V = GND or V
50
250
250
CCZ
I
CC
Additional supply current per
= 5.5 V; one input at 3.4 V,
∆I
CC
0.3
1.5
1.5
mA
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. This parameter is valid for any V between 0 V and 2.1 V, with a transition time of up to 10 msec. From V = 2.1 V to V = 5 V ± 10%, a
CC
CC
CC
transition of up to 100 µsec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design.
5
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
AC CHARACTERISTICS
GND = 0 V; t = t = 2.5 ns; C = 50 pF, R = 500 Ω
R
F
L
L
LIMITS
T
V
= +25 °C
= +5.0 V
T
= –40 °C to +85 °C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORMS
UNIT
= +5.0 V ±10%
CC
Min
Typ
Max
Min
Max
t
t
Propagation delay
An to Bn or Bn to An
1.2
1.0
3.4
2.6
4.8
4.0
1.2
1.0
5.3
4.5
PLH
PHL
2
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
An to PARITY
1
2
2.1
2.5
7.4
7.4
9.5
9.7
2.1
2.5
11.2
11.0
PLH
PHL
t
t
Propagation delay
OEA to PARITY
1
2
2.6
3.1
6.6
6.7
8.5
8.6
2.6
3.1
10.5
10.0
PLH
PHL
Propagation delay
CLEAR to ERROR
t
5
1
1.0
2.5
2.9
4.2
4.4
5.7
1.0
2.5
5.2
6.2
PLH
Propagation delay
CP to ERROR
t
PHL
PZH
t
Output enable time
OEA to An or OEB to Bn, PARITY
3
4
1.0
2.1
3.2
4.1
5.1
5.8
1.0
2.1
6.2
6.7
t
PZL
t
Output disable time
OEA to An or OEB to Bn, PARITY
3
4
3.1
3.2
5.1
5.6
7.3
7.7
3.1
3.2
7.9
8.1
PHZ
t
PLZ
AC SET-UP REQUIREMENTS
GND = 0 V; t = t = 2.5 ns; C = 50 pF, R = 500 Ω
R
F
L
L
LIMITS
T
V
= +25 °C
= +5.0 V
T
= –40 °C to +85 °C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORMS
UNIT
= +5.0 V ±10%
CC
Min
Typ
Min
t (H)
t (L)
s
Set-up time, High or Low
Bn or PARITY to CP
9.8
8.1
6.9
4.0
9.8
8.1
s
6
6
6
5
5
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
Bn or PARITY to CP
0.0
0.0
–3.7
–6.7
0.0
0.0
h
t (L)
h
t (H)
Pulse width, High or Low
CP
3.0
3.0
1.5
1.0
3.0
3.0
w
t (L)
w
Pulse width, Low
CLEAR
t (L)
w
3.0
2.0
1.0
3.0
2.0
Recovery time
CLEAR to CP
t
–0.3
rec
6
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
AC WAVEFORMS
V
M
= 1.5 V, V = GND to 3.0 V
IN
INPUT
INPUT
V
V
V
V
M
M
M
M
t
t
t
t
PHL
PHL
PLH
PLH
V
V
OUTPUT
V
M
V
M
OUTPUT
M
M
SA00216
SA00217
Waveform 1. Propagation Delay for Inverting Output
Waveform 2. Propagation Delay for Non-Inverting Output
V
OEA, OEB
OUTPUT
V
M
M
t
V
OEA, OEB
OUTPUT
M
V
M
t
PHZ
PZH
t
t
PLZ
PZL
V
–0.3V
0V
OH
V
M
V
M
V
+0.3V
0V
OL
SA00238
SA00239
Waveform 3. 3-State Output Enable Time to HIGH Level and
Output Disable Time from HIGH Level
Waveform 4. 3-State Output Enable Time to LOW Level and
Output Disable Time from LOW Level
V
V
M
CLEAR
M
V
V
V
V
M
Bn,
M
M
M
PARITY
t
w
(L)
t
REC
t (H)
s
t (L)
s
t (H)
h
t (L)
h
t
w
(H)
t (L)
w
V
M
CP
CP
V
V
V
M
M
M
t
PLH
ERROR
V
M
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SA00205
NOTE: The shaded areas indicate when the input is permitted to change
Waveform 6. Data Set-up and Hold Times and
Clock Pulse Width
for predictable output performance.
SA00240
Waveform 5. CLEAR Pulse Width, CLEAR to ERROR Delay and
CLEAR to Clock Recovery Time
7
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
18
16
14
12
t
PLH
10
8
6
4
t
PHL
2
0
0
100
200
300
400
500
600
Load resistor (Ω)
NOTE:
When using Open-Collector parts, the value of the pull–up resistor greatly affects the value of the t
. For example, changing the specified pull-up resistor value from
PLH
500Ω to 100Ω will improve the t
over 300% with only a slight change in the t
. However, if the value of the pull-up resistor is changed, the user must make certain
PHL
PLH
that the total I current through the resistor and the total I ’s of the receivers does not exceed the I maximum specification.
OL
IL
OL
SA00241
TEST CIRCUIT AND WAVEFORM
V
t
W
CC
AMP (V)
90%
90%
V
X
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
V
V
OUT
IN
R
R
X
L
0V
(t
PULSE
D.U.T
t
t
(t
(t
)
t
)
THL
F
TLH
R
GENERATOR
)
t
(t )
R
T
C
TLH
R
THL F
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
LOAD VALUES
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
OUTPUT
ERROR 100Ω
All other 500Ω 7.0V
R
V
X
X
Input Pulse Definition
t
PLZ
PZL
V
CC
t
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
74ABT
500ns 2.5ns 2.5ns
see AC CHARACTERISTICS for value.
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00242
8
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
9
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
10
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
11
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
REVISION HISTORY
Rev
Date
Description
_2
20021217
Product data (9397 750 10851); ECN 853-1619 29289 of 12 December 2002.
Supersedes data of 21 June 1993.
Modifications:
• Ordering information table: remove “North America” column; remove 74ABT833N package offering.
_1
19930621
Product specification. ECN 853-1619 10087 of 21 June 1993.
12
2002 Dec 17
Philips Semiconductors
Product data
Octal transceiver with parity generator/checker
(3-State)
74ABT833
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2002
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 12-02
9397 750 10851
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
相关型号:
74ABT834D-T
IC ABT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24, 0.300 INCH, PLASTIC, SOL-24, Bus Driver/Transceiver
NXP
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