74AHCT373PW [NXP]
Octal D-type transparent latch; 3-state; 八路D型透明锁存器;三态型号: | 74AHCT373PW |
厂家: | NXP |
描述: | Octal D-type transparent latch; 3-state |
文件: | 总20页 (文件大小:101K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC373; 74AHCT373
Octal D-type transparent latch;
3-state
Product specification
1999 Nov 23
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
FEATURES
The 74AHC/AHCT373 are octal D-type transparent
latches featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are
common to all latches.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
The ‘373’ consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the
Dn inputs enters the latches. In this condition the latches
are transparent, i.e. a latch output will change state each
time its corresponding D-input changes.
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accepts voltages higher than VCC
• Common 3-state output enable input
• Functionally identical to the ‘533’, ‘563’ and ‘573’
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and −40 to +125 °C.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
DESCRIPTION
The ‘373’ is functionally identical to the ‘533’, ‘563’ and
‘573’, but the ‘533’ and ‘563’ have inverted outputs and the
‘563’ and ‘573’ have a different pin arrangement.
The 74AHC/AHCT373 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
TYPICAL
SYMBOL
tPHL/tPLH
PARAMETER
CONDITIONS
UNIT
AHC
AHCT
propagation delay
Dn to Qn; LE to Qn
CL = 15 pF; VCC = 5 V
VI = VCC or GND
4.3
4.3
ns
CI
input capacitance
output capacitance
3.0
4.0
10
3.0
4.0
12
pF
pF
pF
CO
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
1999 Nov 23
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
INTERNAL
OPERATING MODES
LATCHES
OE
LE
Dn
Q0 to Q7
Enable and read register
(transparent mode)
L
L
H
H
L
L
H
I
L
H
L
L
H
L
Latch and read register
L
L
L
h
X
X
H
X
X
H
Z
Z
Latch register and
disable outputs
H
H
X
X
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGES
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PINS
PACKAGE
MATERIAL
CODE
74AHC373D
74AHC373D
20
20
20
20
SO
plastic
plastic
plastic
plastic
SOT163-1
SOT360-1
SOT163-1
SOT360-1
74AHC373PW
74AHCT373D
74AHCT373PW
74AHC373PW DH
74AHCT373D
TSSOP
SO
7AHCT373PW DH
TSSOP
PINNING
PIN
SYMBOL
DESCRIPTION
1
OE
output enable input (active LOW)
latch outputs
2, 5, 6, 9, 12, 15, 16
and 19
Q0 to Q7
3, 4, 7, 8, 13, 14, 17
and 18
D0 to D7
data inputs
10
11
20
GND
LE
ground (0 V)
latch enable input (active HIGH)
DC supply voltage
VCC
1999 Nov 23
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, halfpage
V
OE
1
2
20
19
18
17
16
15
14
13
12
11
CC
handbook, halfpage
11
LE
Q
0
Q
D
7
3
4
2
5
D
0
3
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
7
6
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
D
D
1
4
7
6
Q
Q
D
Q
1
8
9
5
6
5
373
13
14
17
18
12
15
16
19
Q
2
6
D
2
7
5
4
D
D
3
8
OE
Q
Q
3
9
4
1
MNA186
GND
LE
10
MNA185
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1
EN
11
C1
3
2
1D
4
7
8
5
6
9
13
14
17
18
12
15
16
19
MNA187
Fig.3 IEC logic symbol.
1999 Nov 23
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, halfpage
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
3
4
2
5
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
7
6
LE
handbook, halfpage
8
9
LATCH
1 to 8
3-STATE
OUTPUTS
13
14
17
18
12
15
16
19
LE
LE
D
Q
LE
11
1
MNA189
LE
OE
MNA184
Fig.4 Functional diagram.
Fig.5 Logic diagram (one latch).
D
D
D
D
D
4
D
D
D
7
0
1
2
3
5
6
a n d b o o k , f u l l p a g e w
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
MNA199
Fig.6 Logic diagram.
5
1999 Nov 23
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
RECOMMENDED OPERATING CONDITIONS
74AHC
74AHCT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC
VI
2.0
0
5.0
−
5.5
4.5
0
5.0
−
5.5
V
input voltage
5.5
5.5
V
VO
output voltage
0
−
VCC
+85
0
−
VCC
+85
V
Tamb
operating ambient temperature
see DC and AC
characteristics per
device
−40
−40
+25
+25
−40
+25
+25
°C
+125 −40
+125 °C
tr,tf (∆t/∆f) input rise and fall rates
VCC = 3.3 ±0.3 V
VCC = 5 ±0.5 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
ns/V
20
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX. UNIT
VCC
VI
−0.5 +7.0
−0.5 +7.0
V
input voltage
V
IIK
DC input diode current
DC output diode current
VI < −0.5 V; note 1
VO < −0.5 V or VO > VCC + 0.5 V; note 1
−
−20
±20
±25
±75
mA
mA
mA
mA
IOK
IO
−
DC output source or sink current −0.5 V < VO < VCC + 0.5 V
DC VCC or GND current
−
ICC
Tstg
PD
−
storage temperature
−65
−
+150 °C
500 mW
power dissipation per package
for temperature range: −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Nov 23
6
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
DC CHARACTERISTICS
Family 74AHC
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
OTHER
VCC (V)
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
1.5
2.1
3.85
−
−
−
1.5
2.1
3.85
−
−
1.5
2.1
3.85
−
−
V
V
V
V
V
V
V
V
V
V
−
−
−
−
−
−
−
−
VIL
LOW-level input
voltage
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
0.5
0.9
1.65
−
−
−
−
−
−
−
−
−
VOH
HIGH-level output VI = VIH or VIL;
voltage
1.9
2.9
4.4
2.58
2.0
3.0
4.5
−
1.9
2.9
4.4
2.48
1.9
2.9
4.4
2.40
IO = −50 µA
−
−
−
−
−
−
VI = VIH or VIL;
−
−
−
IO = −4.0 mA
VI = VIH or VIL;
4.5
3.94
−
−
3.8
−
3.70
−
V
IO = −8.0 mA
VOL
LOW-level output VI = VIH or VIL;
2.0
3.0
4.5
3.0
−
−
−
−
0
0
0
−
0.1
0.1
0.1
0.36
−
−
−
−
0.1
0.1
0.1
0.44
−
−
−
−
0.1
0.1
0.1
0.55
V
V
V
V
voltage
IO = 50 µA
VI = VIH or VIL;
IO = 4.0 mA
VI = VIH or VIL;
IO = 8.0 mA
4.5
−
−
−
−
−
−
−
−
−
3
0.36
0.1
−
−
0.44
1.0
±2.5
40
−
−
−
−
−
0.55
2.0
V
II
input leakage
current
VI = VCC or GND 5.5
µA
IOZ
ICC
CI
3-state output
OFF current
VI = VIH or VIL;
VO = VCC or GND
5.5
±0.25 −
±10.0 µA
quiescent supply VI = VCC or GND; 5.5
4.0
10
−
−
80
10
µA
current
IO = 0
input capacitance
−
10
pF
1999 Nov 23
7
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
Family 74AHCT
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
VIL
HIGH-level input
voltage
4.5 to 5.5 2.0
−
−
2.0
−
2.0
−
V
LOW-level input
voltage
4.5 to 5.5 −
−
0.8
−
−
0.8
−
−
0.8
−
V
VOH
HIGH-level output VI = VIH or VIL;
voltage
4.5
4.5
4.5
4.5
5.5
5.5
4.4 4.5
4.4
3.8
−
4.4
3.70
−
V
IO = −50 µA
VI = VIH or VIL;
IO = −8.0 mA
3.94
−
0
−
−
−
−
−
−
V
VOL
LOW-level output VI = VIH or VIL;
voltage
−
−
−
−
0.1
0.36
0.1
0.1
0.44
1.0
±2.5
0.1
0.55
2.0
V
IO = 50 µA
VI = VIH or VIL;
IO = 8.0 mA
−
−
V
II
input leakage
current
VI = VIH or VIL
−
−
µA
IOZ
3-state output
OFF current
VI = VIH or VIL;
VO = VCC or GND
per input pin;
±0.25 −
−
±10.0 µA
other inputs at
VCC or GND;
IO = 0
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
−
4.0
−
−
40
−
−
80
µA
∆ICC
additional
VI = VCC − 2.1 V 4.5 to 5.5 −
1.35
1.5
1.5
mA
quiescent supply
current per input
pin
other inputs at
VCC or GND;
IO = 0
CI
input capacitance
−
−
3
10
−
10
−
10
pF
1999 Nov 23
8
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
AC CHARACTERISTICS
74AHC373
Ground = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH propagation delay see Figs 7 and 11 15 pF
Dn to Qn
−
6.0
6.3
5.6
5.6
7.8
8.3
7.5
9.2
−
11.4 1.0
11.0 1.0
11.4 1.0
10.0 1.0
14.9 1.0
14.5 1.0
14.9 1.0
13.3 1.0
13.5 1.0
13.0 1.0
13.5 1.0
12.0 1.0
17.0 1.0
16.5 1.0
17.0 1.0
15.0 1.0
14.5 ns
14.0 ns
14.5 ns
13.0 ns
19.0 ns
18.5 ns
19.0 ns
17.0 ns
propagation delay see Figs 8 and 11
LE to Qn
−
t
t
t
PZH/tPZL propagation delay see Figs 9 and 11
−
OE to Qn
PHZ/tPLZ propagation delay
OE to Qn
−
PHL/tPLH propagation delay see Figs 7 and 11 50 pF
Dn to Qn
−
propagation delay see Figs 8 and 11
LE to Qn
−
tPZH/tPZL propagation delay see Figs 9 and 11
OE to Qn
−
tPHZ/tPLZ propagation delay
OE to Qn
−
tW
tsu
th
clock pulse width see Figs 8 and 11
HIGH or LOW
5.0
4.0
1.0
−
−
−
5.0
4.0
1.0
−
−
−
5.0
4.0
1.0
−
−
−
ns
ns
ns
set-up time
Dn to CP
see Figs 10 and 11
−
hold time
Dn to CP
−
1999 Nov 23
9
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
TEST CONDITIONS
T
amb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH propagation delay see Figs 7 and 11 15 pF
Dn to Qn
−
4.0
4.3
3.8
4.3
5.3
5.6
5.2
6.4
−
7.2
7.2
8.1
7.2
9.2
9.7
1.0
1.0
1.0
1.0
1.0
1.0
8.5
8.5
9.5
8.5
1.0
1.0
1.0
1.0
9.0
9.0
ns
ns
propagation delay see Figs 8 and 11
LE to Qn
−
t
t
t
PZH/tPZL propagation delay see Figs 9 and 11
−
10.5 ns
9.5 ns
OE to Qn
PHZ/tPLZ propagation delay
OE to Qn
−
PHL/tPLH propagation delay see Figs 7 and 11 50 pF
Dn to Qn
−
10.5 1.0
11.1 1.0
11.5 1.0
10.5 1.0
11.5 ns
12.5 ns
13.0 ns
11.5 ns
propagation delay see Figs 8 and 11
LE to Qn
−
tPZH/tPZL propagation delay see Figs 9 and 11
−
10.1 1.0
OE to Qn
tPHZ/tPLZ propagation delay
OE to Qn
−
9.2
−
1.0
5.0
4.0
1.0
tW
tsu
th
clock pulse width see Figs 8 and 11
HIGH or LOW
5.0
4.0
1.0
−
−
−
5.0
4.0
1.0
−
−
−
ns
ns
ns
set-up time
Dn to CP
see Figs 10 and 11
−
−
hold time
Dn to CP
−
−
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
1999 Nov 23
10
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
74AHCT373
Ground = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 −40 to +125 UNIT
WAVEFORMS
CL
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH propagation delay see Figs 7 and 11 15 pF
Dn to Qn
−
4.0
4.3
4.0
4.4
5.2
5.5
5.2
6.5
−
8.5
1.0
9.5
1.0
11.0 ns
15.5 ns
14.0 ns
13.0 ns
12.0 ns
17.0 ns
15.0 ns
14.0 ns
propagation delay see Figs 8 and 11
LE to Qn
−
12.3 1.0
10.9 1.0
10.2 1.0
13.5 1.0
12.5 1.0
11.0 1.0
10.5 1.0
14.5 1.0
13.5 1.0
12.0 1.0
t
t
PZH/tPZL propagation delay see Figs 9 and 11
OE to Qn
−
PHZ/tPLZ propagation delay
OE to Qn
−
tPHL/tPLH propagation delay see Figs 7 and 11 50 pF
Dn to Qn
−
9.5
1.0
propagation delay see Figs 8 and 11
LE to Qn
−
13.3 1.0
11.9 1.0
11.2 1.0
t
t
PZH/tPZL propagation delay see Figs 9 and 11
OE to Qn
−
PHZ/tPLZ propagation delay
OE to Qn
−
tW
tsu
th
clock pulse width see Figs 8 and 11
HIGH or LOW
6.5
3.5
1.5
−
−
−
6.5
3.5
1.5
−
−
−
6.5
3.5
1.5
−
−
−
ns
ns
ns
set-up time
Dn to CP
see Figs 10 and 11
−
hold time
Dn to CP
−
Note
1. Typical values at VCC = 5.0 V.
1999 Nov 23
11
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
AC WAVEFORMS
handbook, halfpage
V
D
input
M
n
t
t
PHL
PLH
V
Q
output
M
n
t
t
TLH
THL
MNA190
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
FAMILY
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
Fig.7 The input (Dn) to output (Qn) propagation delays and the output transition times.
V
LE input
M
t
W
t
t
PHL
PLH
V
Q
output
M
n
t
t
MNA191
TLH
THL
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
FAMILY
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
Fig.8 The Latch Enable (LE) input pulse width, the latch enable input to output (Qn) propagation delays and the
output transition times.
1999 Nov 23
12
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
V
I
(1)
t
V
OE input
M
GND
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
+ 0.3 V
V
OL
V
OL
t
t
PHZ
PZH
V
OH
− 0.3 V
OH
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA450
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
FAMILY
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
Fig.9 The 3-state enable and disable times.
V
D
input
M
n
t
t
h
h
t
t
su
su
V
LE input
M
MNA193
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
FAMILY
AHC
GND to VCC
50% VCC 50% VCC
1.5 V 50% VCC
AHCT
GND to 3.0 V
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig.10 The data set-up and hold times for Dn input to LE input.
13
1999 Nov 23
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
S1
V
CC
open
GND
V
CC
1000 Ω
V
I
V
O
PULSE
D.U.T.
GENERATOR
C
R
T
L
MNA183
TEST
PLH/tPHL
PLZ/tPZL
S1
open
t
t
Definitions for test circuit.
CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”).
T = termination resistance should be equal to the output impedance Zo of the pulse generator.
VCC
tPHZ/tPZH
GND
R
Fig.11 Test circuitry for switching times.
1999 Nov 23
14
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT163-1
075E04
MS-013AC
1999 Nov 23
15
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-06-16
95-02-04
SOT360-1
MO-153AC
1999 Nov 23
16
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Nov 23
17
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
REFLOW(1)
PACKAGE
WAVE
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Nov 23
18
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
NOTES
1999 Nov 23
19
Philips Semiconductors – a worldwide company
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/02/pp20
Date of release: 1999 Nov 23
Document order number: 9397 750 06298
相关型号:
74AHCT373PWDH
IC AHCT/VHCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20, Bus Driver/Transceiver
NXP
74AHCT374D-Q100
AHCT/VHCT/VT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20
NXP
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