74ALS109AD-T [NXP]
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| 型号： | 74ALS109AD-T |
| 厂家： | 
NXP |
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INTEGRATED CIRCUITS
74ALS109A
Dual J-K positive edge-triggered flip-flop
with set and reset
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual J-K positive edge triggered flip-flop
with set and reset
74ALS109A
DESCRIPTION
PIN CONFIGURATION
The 74ALS109A is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active-Low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K inputs must
be stable just one setup time prior to the Low-to-High transition of
the clock for predictable operation. The JK design allows operation
as a D flip-flop by tying J and K inputs together. Although the clock
input is level sensitive, the positive transition of the clock pulse
between the 0.8V and 2.0V levels should be equal to or less than
the clock to output delay time for reliable operation.
RD0
J0
1
2
3
4
5
16
V
CC
15 RD1
14 J1
K0
CP0
SD0
13 K1
12 CP1
11 SD1
10 Q1
Q0
Q0
6
7
8
GND
9
Q1
SF00135
TYPICAL
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
f
MAX
74ALS109A
150MHz
3.0mA
ORDERING INFORMATION
ORDER CODE
DRAWING
NUMBER
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
16-pin plastic DIP
16-pin plastic SO
74ALS109AN
74ALS109AD
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
J0, J1
K0, K1
J inputs
K inputs
1.0/2.0
1.0/2.0
1.0/2.0
1.0/4.0
1.0/4.0
20/80
20µA/0.2mA
20µA/0.2mA
20µA/0.2mA
20µA/0.4mA
20µA/0.4mA
0.4mA/8mA
CP0, CP1
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
Clock inputs (active rising edge)
Set inputs (active-Low)
Reset inputs (active-Low)
Data outputs
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
2
14
3 13
2
6
7
1J
C1
4
3
J1
K1
K0
4
5
CP0 J0
SD0
1K
R
1
5
1
RD0
S
12
11
15
CP1
14
10
9
2J
SD1
12
13
C2
Q0 Q0 Q1 Q1
RD1
2K
R
15
11
6
7
10
9
S
V
= Pin 16
CC
GND = Pin 8
SF00136
SF00137
2
1991 Feb 08
853–1275 01670
Philips Semiconductors
Product specification
Dual J-K positive edge triggered flip-flop
with set and reset
74ALS109A
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODE
5, 11
SD
SD RD CP
J
X
X
X
h
l
K
X
X
X
l
Q
H
L
Q
L
L
H
L
H
L
X
X
X
↑
Asynchronous set
H
Asynchronous reset
1, 15
4, 12
6, 10
7, 9
RD
CP
Q
Q
L
H*
q
H* Undetermined*
H
H
H
H
H
H
H
H
H
H
q
H
L
q
q
Toggle
↑
l
L
Load “0”
↑
h
l
h
h
h
H
q
Load “1”
2, 14
3, 13
J
↑
Hold “no change”
Hold “no change”
L
l
q
K
H
h
= High voltage level
=
High state must be present one setup time prior to
Low-to-High clock transition
L
l
=
=
Low voltage level
Low state must be present one setup time prior to
Low-to-High clock transition
V
= Pin 16
CC
GND = Pin 8
SC00042
q
=
Lower case indicate the state of the referenced output prior to
the Low-to-High clock transition
X
↑
*
=
=
=
Don’t care
Low-to-High clock transition
The output levels in this configuration are not guaranteed to
meet the minimum levels for V if the set and reset are near
OH
V
IN
maximum. Furthermore, this configuration is nonstable;
that is, it will not remain when either set or reset returns to its
inactive (High) level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
Supply voltage
V
I
CC
V
IN
Input voltage
Input current
V
mA
V
IN
V
OUT
Voltage applied to output in high output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
16
CC
I
mA
°C
°C
OUT
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
5.0
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
CC
Supply voltage
5.5
V
V
V
IH
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
IL
0.8
–18
–0.4
8
V
I
Ik
mA
mA
mA
°C
I
High-level output current
Low-level output current
OH
I
OL
T
amb
Operating free-air temperature range
0
+70
3
1991 Feb 08
Philips Semiconductors
Product specification
Dual J-K positive edge triggered flip-flop
with set and reset
74ALS109A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
= ±10%,
UNIT
2
MIN
TYP
MAX
V
V
CC
IL
V
OH
High-level output voltage
I
= –0.4mA
V
– 2
V
OH
CC
= MAX, V = MIN
IH
I
I
= 4mA
= 8mA
0.25
0.35
0.40
0.50
V
OL
V
V
= MIN, V = MAX,
IL
= MIN
CC
IH
V
Low-level output voltage
Input clamp voltage
OL
V
OL
V
V
CC
= MIN, I = I
IK
–0.73 –1.5
V
IK
I
Jn, Kn, CPn
SDn, RDn
Jn, Kn, CPn
SDn, RDn
Jn, Kn, CPn
SDn, RDn
0.1
0.2
mA
mA
µA
µA
mA
mA
mA
mA
Input current at maximum input
voltage
I
V
= MAX, V = 7.0V
I
I
CC
CC
CC
20
I
High–level input current
Low–level input current
V
V
= MAX, V = 2.7V
I
IH
40
–0.2
–0.4
–112
I
IL
= MAX, V = 0.4V
I
3
I
O
Output current
V
V
= MAX, V = 2.25V
–30
CC
O
4
I
Supply current (total)
= MAX
3.0
4.0
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, I
.
OS
4. Measure I with the clock input grounded and all outputs open, then with Q and Q outputs High in turn.
CC
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
SYMBOL
PARAMETER
TEST CONDITION
UNIT
C = 50pF, R = 500Ω
L
L
MIN
80
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
MHz
ns
MAX
t
t
Propagation delay
CPn to Qn or Qn
3.0
3.0
14.0
14.0
PLH
PHL
t
t
Propagation delay
SDn or RD to Qn or Qn
1.0
3.0
8.0
10.0
PLH
PHL
Waveform 2, 3
ns
AC SETUP REQUIREMENTS
LIMITS
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
SYMBOL
PARAMETER
TEST CONDITION
UNIT
C = 50pF, R = 500Ω
L
L
MIN
MAX
t
t
(H)
(L)
Setup time, High or Low
Jn, Kn to CPn
6.0
6.0
su
su
Waveform 1
Waveform 1
Waveform 1
ns
ns
ns
t (H)
Hold time, High or Low
Jn, Kn to CPn
0.0
0.0
h
t
h
(L)
t
t
(H)
(L)
CPn Pulse width
High or Low
6.0
6.0
w
w
SDn or RDn Pulse width
Low
t
(L)
Waveform 2, 3
Waveform 2, 3
6.0
6.0
ns
ns
w
t
Recovery time, SDn or RDn to CPn
rec
4
1991 Feb 08
Philips Semiconductors
Product specification
Dual J-K positive edge triggered flip-flop
with set and reset
74ALS109A
AC WAVEFORMS
For all waveforms, V = 1.3V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
Jn,
V
t
V
V
V
M
Kn
CPn
Qn
M
M
M
t
(H)
t (H)
h
(L)
t (L)
h
su
su
1/f
M
max
t
(L)
w
V
V
M
V
M
t
(H)
w
t
PHL
t
PLH
V
V
M
M
M
t
t
PHL
PLH
V
M
V
Qn
SC00043
Waveform 1. Propagation Delay for Data to Output,
Data Setup Time and Hold Times, Clock Width,
and Maximum Clock Frequency
Jn, Kn
Jn, Kn
t
(L)
t (L)
w
w
SDn
CPn
RDn
CPn
V
V
M
V
V
M
M
t
M
t
REC
REC
V
V
M
M
t
t
PLH
PLH
Qn
Qn
Qn
Qn
V
V
V
V
M
M
M
M
t
t
PHL
PHL
SC00044
SC00045
Waveform 2. Propagation Delay for Set to Output,
Set Pulse Width and Recovery Time for Set to Clock
Waveform 3. Propagation Delay for Reset to Output,
Reset Pulse Width and Recovery Time for Reset to Clock
5
1991 Feb 08
Philips Semiconductors
Product specification
Dual J-K positive edge triggered flip-flop
with set and reset
74ALS109A
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0.3V
PULSE
GENERATOR
D.U.T.
t
t )
f
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Totem-pole Outputs
10%
10%
0.3V
t
w
Input Pulse Definition
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
V
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
Family
Rep.Rate
t
w
t
t
THL
Amplitude
M
TLH
2.0ns
2.0ns
of
74ALS
3.5V
1.3V
1MHz
500ns
OUT
SC00005
6
1991 Feb 08
Philips Semiconductors
Product specification
Dual J-K positive edge-triggered flip-flop
with set and reset
74ALS109A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
7
1991 Feb 08
Philips Semiconductors
Product specification
Dual J-K positive edge-triggered flip-flop
with set and reset
74ALS109A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
8
1991 Feb 08
Philips Semiconductors
Product specification
Dual J-K positive edge-triggered flip-flop
with set and reset
74ALS109A
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips
Semiconductors
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