74ALVC162334ADGG,1_技术文档

74ALVC162334A

16-bit registered driver with inverted register enable and 30 Ω

termination resistors (3-state)

Rev. 03 — 13 December 2006

Product data sheet

1. General description

The 74ALVC162334A is a 16-bit universal bus driver. Data ﬂow is controlled by

active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP).

When LE is LOW, the A to Y data ﬂow is transparent. When LE is HIGH and CP is held at

LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is

stored in the latch/ﬂip-ﬂop.

The 74ALVC162334A is designed with 30 Ω series resistors in both HIGH or LOW output

stages.

When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the

high-impedance OFF-state. Operation of the OE input does not affect the state of the

latch/ﬂip-ﬂop.

To ensure the high-impedance state during power-up or power-down, OE should be tied to

V_CCthrough a pull-up resistor; the minimum value of the resistor is determined by the

current-sinking capability of the driver.

2. Features

I Wide supply voltage range of 1.2 V to 3.6 V

I Complies with JEDEC standard 8-1A

I CMOS low power consumption

I Direct interface with TTL levels

I Current drive: ±24 mA at 3.0 V

I MULTIBYTE ﬂow-through standard pinout architecture

I Low inductance multiple V_CCand GND pins for minimum noise and ground bounce

I Output drive capability 50 Ω transmission lines at 85 °C

I Integrated 30 Ω termination resistors

I Input diodes to accommodate strong drivers

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

3. Quick reference data

Table 1.

Quick reference data

V_CC= 3.3 V ± 0.3 V; GND = 0 V; t_r= t_f≤ 2.5 ns; C_L= 50 pF (see Figure 11).

Symbol Parameter

t_PHLHIGH-to-LOW propagation delay

Conditions

Min

1.0

1.3

1.4

1.0

1.3

1.4

150

-

Typ^[1]Max

Unit

ns

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

Figure 8

2.8

3.2

2.8

3.2

240

4.0

8.0

4.3

4.4

4.9

4.3

4.4

4.9

-

ns

t_PLH

LOW-to-HIGH propagation delay

ns

f_max

C_i

maximum input clock frequency

input capacitance

MHz

pF

-

C_io

C_PD

input/output capacitance

power dissipation capacitance

-

[2]

per buffer; V_I= GND to V_CC

transparent mode; output enabled

transparent mode; output disabled

clocked mode; output enabled

clocked mode; output disabled

-

10

3

-

pF

21

15

[1] All typical values are at T_amb= 25 °C.

[2] C_PDis used to determine the dynamic power dissipation (P_D) in µW.

P_D= C_PD× V_CC²× f_i+ Σ (C_L× V_CC²× f_o), where:

f_i= input frequency in MHz;

C_L= output load capacitance in pF;

f_o= output frequency in MHz;

V_CC= supply voltage in V;

Σ (C_L× V_CC²× f_o) = sum of outputs.

4. Ordering information

Table 2.

Ordering information

Type number

Temperature

range

Package

Name

Description

Version

SOT362-1

74ALVC162334ADGG

−40 °C to +85 °C

TSSOP48

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

2 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

5. Functional diagram

1

48

25

OE

CP

LE

EN1

2C3

C3

G2

2

3

47

A1

Y1

Y2

46

A2

5

44

A3

Y3

6

43

A4

Y4

1

3D

8

41

A5

Y5

9

40

A6

Y6

11

12

13

14

16

17

19

20

22

23

38

A7

Y7

37

A8

Y8

36

A9

Y9

35

Y10

Y11

Y12

Y13

Y14

Y15

Y16

A10

33

A11

32

A12

30

A13

29

A14

27

A15

26

A16

002aac723

Fig 1. Logic symbol (IEEE/IEC)

OE

CP

LE

A1

D

LE

CP

Y1

to the 15 other channels

002aac724

Fig 2. Logic diagram

V

CC

A1

002aac725

Fig 3. Typical input (data or control)

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

3 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

6. Pinning information

6.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

OE

Y1

CP

A1

3

Y2

A2

4

GND

Y3

GND

A3

5

6

Y4

A4

7

V

CC

V

CC

8

Y5

A5

9

Y6

A6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

GND

Y7

GND

A7

Y8

A8

74ALVC162334ADGG

Y9

A9

Y10

GND

Y11

Y12

A10

GND

A11

A12

V

CC

V

CC

Y13

Y14

GND

Y15

Y16

n.c.

A13

A14

GND

A15

A16

LE

002aac722

Fig 4. Pin conﬁguration for TSSOP48

6.2 Pin description

Table 3.

Symbol

Pin description

Description

OE

Y1

1

2

3

output enable input (active LOW)

data output 1

Y2

data output 2

GND

4, 10, 15, 21,

28, 34, 39, 45

ground supply (0 V)

Y3

Y4

V_CC

Y5

Y6

Y7

Y8

5

data output 3

6

data output 4

7, 18, 31, 42

positive supply voltage

data output 5

8

9

data output 6

11

12

data output 7

data output 8

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

4 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

Table 3.

Pin description …continued

Description

Symbol

Y9

13

14

16

17

19

20

22

23

24

25

26

27

29

30

32

33

35

36

37

38

40

41

43

44

46

47

48

data output 9

data output 10

data output 11

data output 12

data output 13

data output 14

data output 15

data output 16

not connected

Y10

Y11

Y12

Y13

Y14

Y15

Y16

n.c.

LE

latch enable input (active LOW)

data input 16

data input 15

data input 14

data input 13

data input 12

data input 11

data input 10

data input 9

A16

A15

A14

A13

A12

A11

A10

A9

A8

data input 8

A7

data input 7

A6

data input 6

A5

data input 5

A4

data input 4

A3

data input 3

A2

data input 2

A1

data input 1

CP

clock input

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

5 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

7. Functional description

Refer to Figure 1 “Logic symbol (IEEE/IEC)” and Figure 2 “Logic diagram”.

7.1 Function selection

Table 4.

Function selection

H = HIGH voltage level; L = LOW voltage level; X = Don’t care; Z = high-impedance OFF-state;

↑ = LOW to HIGH level transition.

Inputs

Outputs

OE

H

L

LE

X

CP

X

↑

An

X

Yn

Z

L

H

L

H

L

H

L

↑

H

X

H

[1]

L

H

L

Y₀

[2]

L

X

Y₀

[1] Output level before the indicated steady-state input conditions were established, provided that CP is HIGH

before LE goes LOW.

[2] Output level before the indicated steady-state input conditions were established.

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

6 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+4.6

−50

Unit

V

supply voltage

−0.5

input clamping current

input voltage

V_I< 0 V

-

mA

V

[1]

V_I

−0.5

+4.6

±50

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

-

mA

V

V_O

−0.5

V_CC+ 0.5

±50

I_{O(sink/source)}output sink or source current V_O= 0 V to V_CC

-

mA

°C

I_CC

supply current

-

±100

+150

600

I_GND

ground current

-

T_stg

storage temperature

−65

P_tot/pack

total power dissipation

per package

for temperature range −40 °C to +125 °C;

above +55 °C derate linearly with 8 mW/K

-

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

9. Recommended operating conditions

Table 6.

Symbol

V_CC

Operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

2.5 V range for maximum speed performance

at 30 pF output load

2.3

-

2.7

V

3.3 V range for maximum speed performance

at 50 pF output load

3.0

-

3.6

V

for low-voltage applications

1.2

0

-

3.6

V_CC

+85

20

V

V_I

input voltage

V

V_O

T_amb

t_r

output voltage

0

V

ambient temperature operating in free-air

−40

0

°C

rise time

V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

ns/V

0

10

t_f

fall time

0

20

0

10

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

7 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

10. Static characteristics

Table 7.

Static characteristics

T_amb= −40 °C to +85 °C; over recommended operating conditions; voltages are referenced to GND (ground = 0 V);

unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

1.7

2.0

-

Typ^[1]

1.2

Max

-

Unit

V

V_IH

HIGH-level input voltage V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

1.5

-

V

V_IL

LOW-level input voltage

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

1.2

0.7

0.8

V

-

1.5

V

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

V_CC= 2.3 V to 3.6 V; I_O= −100 µA

V

_CC− 0.2 V_CC

-

V

V_CC= 2.3 V; I_O= −4 mA

V_CC= 2.3 V; I_O= −6 mA

V_CC= 2.7 V; I_O= −4 mA

V_CC= 2.7 V; I_O= −8 mA

V_CC= 3.0 V; I_O= −6 mA

V_CC= 3.0 V; I_O= −12 mA

_CC− 0.4

_CC− 0.6

_CC− 0.5

_CC− 0.7

_CC− 0.6

_CC− 1.0

V

_CC− 0.11

_CC− 0.17

_CC− 0.09

_CC− 0.19

_CC− 0.13

_CC− 0.27

V_OL

LOW-level output voltage V_I= V_IHor V_IL

V_CC= 2.3 V to 3.6 V; I_O= 100 µA

V_CC= 2.3 V; I_O= 4 mA

V_CC= 2.3 V; I_O= 6 mA

V_CC= 2.7 V; I_O= 4 mA

V_CC= 2.7 V; I_O= 8 mA

V_CC= 3.0 V; I_O= 6 mA

V_CC= 3.0 V; I_O= 12 mA

-

GND

0.07

0.11

0.06

0.13

0.09

0.19

0.1

0.20

0.40

0.55

0.40

0.60

0.55

0.80

5

V

I_LI

input leakage current

off-state output current

supply current

V_CC= 2.3 V to 3.6 V;

V_I= V_CCor GND

µA

I_OZ

I_CC

∆I_CC

3-state; V_CC= 2.3 V to 3.6 V;

V_I= V_IHor V_IL; V_O= V_CCor GND

-

0.1

0.2

150

10

µA

V_CC= 2.3 V to 3.6 V;

V_I= V_CCor GND; I_O= 0 mA

40

additional supply current V_CC= 2.3 V to 3.6 V;

750

V_I= V_CC− 0.6 V; I_O= 0 mA

C_i

input capacitance

-

4.0

8.0

-

pF

C_io

C_PD

input/output capacitance

[2]

power dissipation

capacitance

per buffer; V_I= GND to V_CC

transparent mode; output enabled

transparent mode; output disabled

clocked mode; output enabled

clocked mode; output disabled

-

10

3

-

pF

21

15

[1] All typical values are at T_amb= 25 °C.

[2] C_PDis used to determine the dynamic power dissipation (P_D) in µW.

P_D= C_PD× V_CC²× f_i+ Σ (C_L× V_CC²× f_o), where:

f_i= input frequency in MHz;

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

8 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

C_L= output load capacitance in pF;

f_o= output frequency in MHz;

V_CC= supply voltage in V;

Σ (C_L× V_CC²× f_o) = sum of outputs.

11. Dynamic characteristics

Table 8.

Dynamic characteristics for V_CC= 2.3 V to 2.7 V range

V_CC= 2.3 V to 2.7 V; GND = 0 V; t_r= t_f≤ 2.0 ns; C_L= 30 pF (see Figure 11).

Symbol

Parameter

Conditions

Min

1.0

1.3

1.4

1.0

1.3

1.4

1.0

3.3

1.0

1.5

0.4

1.4

150

Typ^[1]

3.5

3.7

3.5

3.7

3.5

2.8

1.0

0.7

-

Max

5.0

5.4

5.0

5.4

5.0

4.5

-

Unit

ns

MHz

t_PHL

HIGH-to-LOW propagation delay

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

t_PLH

LOW-to-HIGH propagation delay

[2]

[3]

t_PZH

t_PZL

t_PHZ

t_PLZ

t_w

OFF-state to HIGH propagation delay OE to Yn; Figure 10

OFF-state to LOW propagation delay OE to Yn; Figure 10

HIGH to OFF-state propagation delay OE to Yn; Figure 10

LOW to OFF-state propagation delay OE to Yn; Figure 10

pulse width

CP HIGH or LOW; Figure 8

LE HIGH; Figure 6

An to CP; Figure 9

An to LE; Figure 7

An to CP; Figure 9

An to LE; Figure 7

Figure 8

-

t_su

set-up time

-

t_h

hold time

0.4

190

-

f_max

maximum input clock frequency

-

[1] All typical values are at V_CC= 2.5 V and T_amb= 25 °C.

[2] 3-state output enable time.

[3] 3-state output disable time.

Table 9.

Dynamic characteristics for V_CC= 2.7 V

V_CC= 2.7 V; GND = 0 V; t_r= t_f≤ 2.5 ns; C_L= 50 pF (see Figure 11).

Symbol

Parameter

Conditions

Min

1.0

1.3

1.4

1.0

1.3

1.4

1.1

1.3

Typ^[1]

3.3

3.4

3.8

3.3

3.4

3.8

3.7

3.5

Max

4.6

4.8

6.2

4.6

4.8

6.2

6.0

4.9

Unit

ns

t_PHL

HIGH-to-LOW propagation delay

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

t_PLH

LOW-to-HIGH propagation delay

[2]

[3]

t_PZH

t_PZL

t_PHZ

t_PLZ

OFF-state to HIGH propagation delay OE to Yn; Figure 10

OFF-state to LOW propagation delay OE to Yn; Figure 10

HIGH to OFF-state propagation delay OE to Yn; Figure 10

LOW to OFF-state propagation delay OE to Yn; Figure 10

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

9 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

Table 9.

Dynamic characteristics for V_CC= 2.7 V …continued

V_CC= 2.7 V; GND = 0 V; t_r= t_f≤ 2.5 ns; C_L= 50 pF (see Figure 11).

Symbol

Parameter

Conditions

Min

3.3

1.0

1.5

0.6

1.7

150

Typ^[1]

1.2

0.6

-

Max

Unit

ns

t_w

pulse width

CP HIGH or LOW; Figure 8

LE HIGH; Figure 6

An to CP; Figure 9

An to LE; Figure 7

An to CP; Figure 9

An to LE; Figure 7

Figure 8

-

ns

t_su

set-up time

ns

-

ns

t_h

hold time

0.3

0.4

190

ns

f_max

maximum input clock frequency

MHz

[1] All typical values are measured at T_amb= 25 °C.

[2] 3-state output enable time.

[3] 3-state output disable time.

Table 10. Dynamic characteristics for V_CC= 3.0 V to 3.6 V range

V_CC= 3.3 V ± 0.3 V; GND = 0 V; t_r= t_f≤ 2.5 ns; C_L= 50 pF (see Figure 11).

Symbol

Parameter

Conditions

Min

1.0

1.3

1.4

1.0

1.3

1.4

1.1

1.3

3.3

1.0

1.5

0.9

1.4

150

Typ^[1]

2.8

3.2

2.8

3.2

2.4

0.7

0.6

-

Max

4.3

4.4

4.9

4.3

4.4

4.9

4.5

4.8

-

Unit

ns

MHz

t_PHL

HIGH-to-LOW propagation delay

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

An to Yn; Figure 5

LE to Yn; Figure 6

CP to Yn; Figure 8

t_PLH

LOW-to-HIGH propagation delay

[2]

[3]

t_PZH

t_PZL

t_PHZ

t_PLZ

t_w

OFF-state to HIGH propagation delay OE to Yn; Figure 10

OFF-state to LOW propagation delay OE to Yn; Figure 10

HIGH to OFF-state propagation delay OE to Yn; Figure 10

LOW to OFF-state propagation delay OE to Yn; Figure 10

pulse width

CP HIGH or LOW; Figure 8

LE HIGH; Figure 6

An to CP; Figure 9

An to LE; Figure 7

An to CP; Figure 9

An to LE; Figure 7

Figure 8

-

t_su

set-up time

-

t_h

hold time

0.3

0.4

240

-

f_max

maximum input clock frequency

-

[1] All typical values are measured at V_CC= 3.3 V, T_amb= 25 °C.

[2] 3-state output enable time.

[3] 3-state output disable time.

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

10 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

11.1 AC waveforms

V_CC= 3.0 V to 3.6 V and V_CC= 2.7 V range:

V_M= 1.5 V; V_X= V_OL+ 0.3 V; V_Y= V_OH− 0.3 V; V_I= 2.7 V.

V_OLand V_OHare the typical output voltage drop that occur with the output load.

V_CC= 2.3 V to 2.7 V and V_CC< 2.3 V range:

V_M= 0.5 V; V_X= V_OL+ 0.15 V; V_Y= V_OH− 0.15 V; V_I= V_CC

.

V_OLand V_OHare the typical output voltage drop that occur with the output load.

V

I

An input

V

LE input

V

M

GND

t

w

t

PLH

t

PLH

PHL

t

PHL

V

OH

Yn output

V

Yn output

V

M

V

OL

002aac726

002aac727

Fig 5. Input (An) to output (Yn) propagation delay

Fig 6. LE input pulse width, LE input to Yn output

propagation delays

1 / f

max

V

I

An

input

V

CP input

V

M

t

M

GND

t

w

t

h

t

h

PLH

t

PHL

su

V

I

OH

LE

input

V

Yn output

V

M

GND

V

OL

002aac728

002aac729

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

Fig 7. Data set-up and hold times, An input to

LE input

Fig 8. CP to Yn propagation delays, clock pulse width,

and maximum clock frequency

V

I

OE input

V

M

GND

V

I

CP

input

t

PZL

PLZ

V

M

V

output

LOW-to-OFF

OFF-to-LOW

CC

GND

t

h

V

su

h

su

M

V

X

V

OL

V

I

An

input

t

PZH

PHZ

OH

GND

output

HIGH-to-OFF

OFF-to-HIGH

V

Y

V

M

GND

V

OH

Yn

output

outputs

enabled

outputs

disabled

outputs

enabled

OL

002aac730

002aac731

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

Fig 9. Data set-up and hold times, An input to

CP input

Fig 10. 3-state enable and disable times

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

11 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

12. Test information

S1

2 × V

open

GND

CC

V

R

L

CC

500 Ω

V

O

I

PULSE

GENERATOR

DUT

R

500 Ω

L

R

T

C

L

002aac732

Test data are given in Table 11.

R_L= load resistance.

C_L= load capacitance includes jig and probe capacitance.

R_T= termination resistance should be equal to Z_oof pulse generators.

Fig 11. Test circuitry for switching times

Table 11. Test data

Supply voltage Input

Load

C_L

Switch S1

t_PLH, t_PHL

open

V_CC

V_I

t_r, t_f

R_L

t_PZH, t_PHZ

t_PZL, t_PLZ

2.3 V to 2.7 V

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

500 Ω

GND (0 V) 2 × V_CC

2.7 V

open

3.0 V to 3.6 V

open

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

12 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

13. Package outline

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

E

D

A

X

c

H

v

M

A

y

E

Z

48

25

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

24

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

12.6

12.4

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.8

0.4

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT362-1

MO-153

Fig 12. Package outline SOT362-1 (TSSOP48)

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

13 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

14. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

14 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

14.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 13) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 13.

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

15 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 13. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

15. Abbreviations

Table 14. Abbreviations

Acronym

CMOS

TTL

Description

Complementary Metal Oxide Semiconductor

Transistor-Transistor Logic

16. Revision history

Table 15. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74ALVC162334A_3

Modiﬁcations:

20061213

Product data sheet

-

74ALVC162334A_2

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 1 “General description”, 1^stparagraph, 2^ndsentence: changed “OE” to “OE”

• Table 2 “Ordering information”: changed (SOT364-1; TSSOP56) package to (SOT362-1;

TSSOP48) package

• Table 3 “Pin description” corrected:

–

changed “Y₁to Y₁₈” to (Y1 to Y16, noted separately)

GND pins: added pins 4 and 39

V_CCpins changed from “7, 22, 35, 50” to “7, 18, 31, 42”

changed “A₁to A₁₈” to (A1 to A16, noted separately)

• Figure 1 “Logic symbol (IEEE/IEC)”: corrected pin number for Y15 from “21” to “22”

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

16 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

Table 15. Revision history …continued

Document ID

Release date

Data sheet status

Change notice

Supersedes

Modiﬁcations:

(continued)

• Figure 1 “Logic symbol (IEEE/IEC)”: corrected pin number for Y15 from “21” to “22”

• Figure 2 “Logic diagram”:

–

changed signal “A₀” to “A1”

changed signal “Y₀” to “Y1”

changed “to the 17 other channels” to “to the 15 other channels”

• Table 5 “Limiting values” (title changed from “Absolute maximum ratings”):

–

parameter deﬁnition of I_IKchanged from “DC input diode current” to “input clamping current”

–

parameter deﬁnition of I_OKchanged from “DC output diode current” to “output clamping

current”

–

symbol “I_O” (DC output source or sink current) changed to “I_{O(sink/source)}” (output sink or

source current)

removed P_tot/pack information for SSOP package

• Table 7 “Static characteristics” (title changed from “DC electrical characteristics”):

–

changed symbol “I_I” to “I_LI”

–

parameter deﬁnition of I_OZchanged from “3-State output OFF-state current” to “OFF-state

output current” (moved “3-state” to Conditions column)

–

parameter deﬁnition of I_CCchanged from “quiescent supply current” to “supply current”

parameter deﬁnition of ∆I_CCchanged from “additional quiescent supply current” to

“additional supply current”

–

added C_i, C_io, and C_PDparameters

• Section 11 “Dynamic characteristics”: table “AC characteristics for V_CC= 3.0 V to 3.6 V range

and V_CC= 2.7 V” separated into 2 tables

• Section 11.1 “AC waveforms”:

–

1^stparagraph, 2^ndline: changed “V_M= 1.5 V_CC” to “V_M= 1.5 V”

–

removed statement “V_M= 0.5V_CCat V_CC= 2.3 V to 2.7 V.” from Figure 5, Figure 6, Figure 7,

Figure 8, Figure 9 and Figure 10 as redundant (depends on voltage as stated above these

ﬁgures)

• Section 13 “Package outline”: replaced SOT364-1 (TSSOP56) package outline drawing with

Figure 12 “Package outline SOT362-1 (TSSOP48)”

74ALVC162334A_2

(9397 750 07246)

20000620

20000314

Product speciﬁcation

853-2197 23931

853-2197 23314

74ALVC162334A_1

-

74ALVC162334A_1

(9397 750 06963)

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

17 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

17.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

18. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

74ALVC162334A_3

Product data sheet

Rev. 03 — 13 December 2006

18 of 19

74ALVC162334A

NXP Semiconductors

16-bit registered driver (3-state)

19. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 6

Function selection. . . . . . . . . . . . . . . . . . . . . . . 6

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended operating conditions. . . . . . . . 7

Static characteristics. . . . . . . . . . . . . . . . . . . . . 8

Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 11

Test information. . . . . . . . . . . . . . . . . . . . . . . . 12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

9

10

11

11.1

12

13

14

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Introduction to soldering . . . . . . . . . . . . . . . . . 14

Wave and reﬂow soldering . . . . . . . . . . . . . . . 14

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 15

14.1

14.2

14.3

14.4

15

16

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 December 2006

Document identifier: 74ALVC162334A_3


型号：	74ALVC162334ADGG,1
厂家：	NXP
描述：	74ALVC162334A - 16-bit registered driver with inverted register enable and 30 Ohm termination resistors (3-state) TSSOP 48-Pin PC 驱动光电二极管逻辑集成电路
文件：	总19页 (文件大小：105K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74ALVC162334ADGG,1 [NXP]

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