74ALVCH162601DGG,1 [NXP]
74ALVCH162601 - 18-bit universal bus transceiver with 30 Ohm termination resistor; 3-state TSSOP 56-Pin;
| 型号： | 74ALVCH162601DGG,1 |
| 厂家： | 
NXP |
| 描述： | 74ALVCH162601 - 18-bit universal bus transceiver with 30 Ohm termination resistor; 3-state TSSOP 56-Pin 光电二极管 逻辑集成电路 |
| 文件： | 总20页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74ALVCH162601
18-bit universal bus transceiver with
30 Ω termination resistor; 3-state
Product specification
1999 Oct 14
File under Integrated Circuits, IC24
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
FEATURES
DESCRIPTION
• Complies with JEDEC standard
no. 8-1A
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting
3-state bus compatible outputs in both send and receive directions. Data flow
in each direction is controlled by output enable (OEAB and OEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus
• CMOS low power consumption
• Direct interface with TTL levels
• MULTIBYTE flow-through
standard pin-out architecture
data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB
.
When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs
are in the high-impedance state. The clocks can be controlled with the
clock-enable inputs (CEBA/CEAB).
• Low inductance multiple VCC and
ground pins for minimum noise and
ground bounce
• All data inputs have bus hold
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
circuitry
To ensure the high-impedance state during power-down, OEBA and OEAB
should be tied to VCC through a pull-up resistor, the minimum value of the
resistor is determined by the current-sinking/current-sourcing capability of the
driver.
• Integrated 30 Ω termination
resistors.
The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or
LOW output stage.
Active bus hold circuitry is provided to hold unused or floating data inputs at
a valid logic level.
QUICK REFERENCE DATA
Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns.
SYMBOL
PHL/tPLH
PARAMETER
CONDITIONS
TYPICAL
4.0
UNIT
t
propagation delay An, Bn to Bn, An CL = 30 pF; VCC = 2.5 V
CL = 50 pF; VCC = 3.3 V
ns
ns
pF
pF
3.1
8.0
4.0
CI/O
CI
input/output capacitance
input capacitance
CPD
power dissipation capacitance per notes 1 and 2
latch
outputs enabled
21
3
pF
pF
outputs disabled
Notes
1. PD is used to determine the dynamic power dissipation (PD in µW).
C
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC
.
1999 Oct 14
2
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
STATUS
disabled
CEXX
OEXX
LEXX
CPXX
An, Bn
X
H
X
X
X
Z
X
X
L
L
H
H
X
X
H
L
H
L
transparent
hold
H
L
L
X
X
NC
L
L
L
L
L
L
↑
↑
h
l
H
L
clock and display
L
L
L
L
L
L
L
H
X
X
NC
hold
Note
1. XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of CPXX
;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of CPXX
;
X = don’t care;
↑ = LOW-to-HIGH level transition;
NC = no change;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74ALVCH162601DGG
−40 to +85 °C
56
TSSOP
plastic
SOT364-1
1999 Oct 14
3
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
PINNING
PIN
SYMBOL
DESCRIPTION
output enable A-to-B
1
2
OEAB
LEAB
latch enable A-to-B
data inputs/outputs
3, 5, 6, 8, 9, 10, 12, 13, 14, 15, A0 to A17
16, 17, 19, 20, 21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46, 53
GND
VCC
ground (0 V)
7, 22, 35, 50
DC supply voltage
output enable B-to-A
latch enable B-to-A
clock enable B-to-A
clock input B-to-A
data inputs/outputs
27
28
29
30
OEBA
LEBA
CEBA
CPBA
31, 33, 34, 36, 37, 38, 40, 41,
42, 43, 44, 45, 47, 48, 49, 51,
52, 54
B17 to B0
55
56
CPAB
CEAB
clock input A-to-B
clock enable A-to-B
1999 Oct 14
4
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
handbook, halfpage
OE
LE
1
2
56 CE
AB
AB
AB
AB
CP
55
V
handbook, halfpage
CC
A
0
B
0
3
54
GND
53 GND
4
data
input
to internal circuit
B
52
A
1
5
1
B
A
2
6
51
50
49
48
47
2
V
V
B
B
B
7
MNA291
CC
CC
3
A
3
8
A
4
9
4
A
5
10
5
46 GND
B
GND 11
A
A
A
A
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
6
6
7
8
9
B
B
B
B
B
7
Fig.2 Bus hold circuit.
8
162601
9
A
10
11
10
11
A
GND
GND
A
B
12
12
A
B
13
13
A
B
14
14
V
V
CC
CC
A
B
15
15
A
B
16
16
GND
GND
A
B
17
17
OE
CP
BA
BA
BA
LE
CE
BA
MNA287
Fig.1 Pin configuration.
1999 Oct 14
5
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
OE
AB
CE
AB
LE
AB
CP
AB
CP
BA
LE
BA
CE
BA
OE
BA
CE
C1
B
n
CP
1D
A
n
CE
C1
CP
1D
18 IDENTICAL CHANNELS
MNA289
Fig.3 Logic diagram (one section).
1999 Oct 14
6
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
handbook, halfpage
1
EN1
G2
OE
CE
CP
LE
AB
AB
AB
AB
56
55
2
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
0
2C3
0
handbook, halfpage
3
5
54
B
1
C3
1
52
G2
B
2
2
6
51
27
29
30
28
EN4
G5
OE
CE
CP
LE
B
3
BA
BA
BA
BA
3
8
49
B
4
4
9
48
5C6
B
5
5
10
12
13
14
15
16
17
19
20
21
23
24
26
47
C6
G5
B
6
6
45
B
7
7
44
B
8
3
54
8
3D
4
1
A
0
B
43
0
B
9
9
6D
42
52
51
49
48
47
45
44
43
42
B
5
6
10
11
12
13
14
15
16
17
10
A
1
B
B
B
B
B
B
B
B
B
B
B
1
41
B
11
A
2
2
40
8
B
A
3
12
3
38
9
B
A
4
A
5
13
4
37
10
12
13
14
15
16
17
19
20
21
23
24
B
14
5
36
B
A
15
6
6
34
A
7
A
8
B
7
16
33
B
8
17
31
A
9
9
41
40
A
10
11
10
11
OE
LE
OE
BA
AB
1
2
27
A
LE
BA
AB
38
37
36
34
33
31
28
A
A
A
A
A
A
B
B
B
B
B
B
12
13
14
15
16
17
12
13
14
15
16
17
CP
CP
BA
AB
AB
55
56
30
CE
CE
BA
29
MNA288
26
MNA290
Fig.4 IEC logic symbol.
Fig.5 Logic symbol.
1999 Oct 14
7
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
for max. speed performance CL = 30 pF
for max. speed performance CL = 50 pF
for low-voltage applications
2.3
2.5
2.7
V
3.0
1.2
0
3.3
2.4
−
3.6
3.6
VCC
VCC
+85
20
V
V
VI
DC input voltage
V
VO
DC output voltage
0
−
V
Tamb
tr, tf
operating ambient temperature in free air
−40
0
−
°C
ns/V
ns/V
input rise and fall times
VCC = 2.3 to 3.0 V
CC = 3.0 to 3.6 V
−
V
0
−
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
−
MAX.
+4.6
UNIT
VCC
IIK
V
DC input diode current
DC input voltage
VI < 0
note 1
−50
mA
V
VI
−0.5
−
+4.6
IOK
VO
IO
DC output diode current
DC output voltage
VO > VCC or VO < 0
note 1
±50
mA
V
−0.5
−
VCC + 0.5
±50
DC output source or sink current VO = 0 to VCC
mA
mA
°C
ICC, IGND DC VCC or GND current
−
±100
+150
600
Tstg
Ptot
storage temperature
power dissipation
−65
−
for temperature range: −40 to +125 °C;
mW
note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of Ptot derates linearly with 8 mW/K.
1999 Oct 14
8
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
OTHER VCC (V)
2.3 to 2.7 1.7
2.7 to 3.6 2.0
Tamb = −40 TO +85 °C
SYMBOL
PARAMETER
UNIT
VI (V)
MIN.
TYP.(1)
1.2
MAX.
VIH
HIGH-level input voltage
−
V
V
V
1.5
−
VIL
LOW-level input voltage
2.3 to 2.7
2.7 to 3.6
−
−
V
V
V
V
V
V
V
−
−
−
−
−
−
−
−
1.2
0.7
0.8
−
1.5
VOH
HIGH-level output voltage VIH or VIL IO = −100 µA 2.3 to 3.6
CC − 0.2 VCC
IO = −4 mA
IO = −6 mA
IO = −4 mA
IO = −8 mA
IO = −6 mA
2.3
2.3
2.7
2.7
3.0
CC − 0.4 VCC − 0.11
−
CC − 0.6 VCC − 0.17
−
CC − 0.5 VCC − 0.09
−
CC − 0.7 VCC − 0.19
−
CC − 0.6 VCC − 0.13
−
IO = −12 mA 3.0
VIH or VIL IO = 100 µA 2.3 to 3.6
IO = 4 mA 2.3
CC − 1.0 VCC − 0.27
−
VOL
LOW-level output voltage
GND
0.07
0.11
0.06
0.13
0.09
0.19
0.1
0.20
0.40
0.55
0.40
0.60
0.55
0.80
5
V
IO = 6 mA
IO = 4 mA
IO = 8 mA
IO = 6 mA
IO = 12 mA
2.3
2.7
2.7
3.0
3.0
Il
input leakage current
VCC or
GND
2.3 to 3.6
µA
µA
µA
µA
IOZ
ICC
∆ICC
3-state output OFF-state
current
VIH or VIL VO = VCC or 2.3 to 3.6
GND
−
−
−
0.1
0.2
150
10
quiescent supply voltage
VCC or
GND
IO = 0
2.3 to 3.6
40
additional quiescent supply
current given per data I/O
pin with bus hold
V
CC − 0.6 IO = 0
2.3 to 3.6
750
IBHL
bus hold LOW sustaining
current
0.7(2)
0.8(2)
2.3(2)
3.0(2)
2.3(2)
3.0(2)
3.6(2)
45
−
−
−
−
−
−
µA
µA
75
150
IBHH
bus hold HIGH sustaining 1.7(2)
current
−45
−75
500
2.0(2)
−175
IBHLO
IBHHO
bus hold LOW overdrive
current
−
µA
µA
bus hold LOW overdrive
current
3.6(2)
−500
−
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Valid for data inputs of bus hold parts.
1999 Oct 14
9
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V
Ground = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF.
TEST CONDITIONS
Tamb = −40 TO +85 °C
UNIT
SYMBOL
tPHL/tPLH
PARAMETER
propagation delay
WAVEFORMS
VCC (V)
MIN. TYP.(1) MAX.
see Figs 6 and 10
2.3 to 2.7 1.3
2.3 to 2.7 1.0
2.3 to 2.7 1.5
2.3 to 2.7 1.6
2.3 to 2.7 1.8
2.3 to 2.7 3.3
2.3 to 2.7 3.3
2.3 to 2.7 +2.3
2.3 to 2.7 1.3
2.3 to 2.7 +2.0
2.3 to 2.7 1.2
2.3 to 2.7 1.3
2.3 to 2.7 1.1
2.3 to 2.7 150
4.0
4.5
4.7
3.9
2.6
1.6
2.0
−0.2
0.1
−0.4
0.3
0.2
0.4
190
5.3
6.0
6.4
6.1
5.7
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
An, Bn to Bn, An
propagation delay
LEAB, LEBA to Bn, An
see Figs 7 and 10
see Figs 7 and 10
see Figs 8 and 10
see Figs 8 and 10
propagation delay
CPAB, CPBA to Bn, An
t
PZH/tPZL
tPHZ/tPLZ
tW
3-state output enable time
OEAB, OEBA to Bn, An
3-state output disable time
OEAB, OEBA to Bn, An
clock pulse width HIGH LEAB see Figs 7 and 10
or LEBA
clock pulse width HIGH or
LOW CPAB or CPBA
see Figs 7 and 10
see Figs 9 and 10
see Figs 9 and 10
−
tsu
set-up time
An, Bn to CPAB, CPBA
−
set-up time
An, Bn to LEAB, LEBA
−
set-up time
CEAB, CEBA to CPAB, CPBA
−
th
hold time
An, Bn to CPAB, CPBA
see Figs 9 and 10
see Figs 9 and 10
−
hold time
An, Bn to LEAB, LEBA
−
hold time
CEAB, CEBA to CPAB, CPBA
−
fmax
maximum clock pulse
frequency
see Figs 7 and 10
−
Note
1. All typical values are measured at Tamb = 25 °C and VCC = 2.5 V.
1999 Oct 14
10
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 TO 3.6 V
Ground = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF.
TEST CONDITIONS
Tamb = −40 TO +85 °C
SYMBOL
tPHL/tPLH
PARAMETER
UNIT
WAVEFORMS
VCC (V)
MIN.
TYP.(1)
MAX.
5.2
propagation delay
An, Bn to Bn, An
see Figs 6 and 10 2.7
−
3.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
3.0 to 3.6 1.6
3.1(2)
4.5
5.9
5.1
6.3
5.5
6.7
5.7
5.3
4.8
−
propagation delay
LEAB, LEBA to Bn, An
see Figs 7 and 10 2.7
−
4.3
3.0 to 3.6 1.5
3.5(2)
4.5
3.7(2)
propagation delay
CPAB, CPBA to Bn, An
see Figs 7 and 10 2.7
−
3.0 to 3.6 1.6
tPZH/tPZL
3-state output enable time
OEAB, OEBA to Bn, An
see Figs 8 and 10 2.7
−
3.9
3.0 to 3.6 1.6
3.1(2)
3.2
2.9(2)
tPHZ/tPLZ
3-state output disable time see Figs 8 and 10 2.7
−
OEAB, OEBA to Bn, An
3.0 to 3.6 1.8
tW
clock pulse width
LEAB, LEBA to CPAB, CPBA
see Figs 7 and 10 2.7
3.3
0.7
3.0 to 3.6 3.3
0.9(2)
1.2
−
clock pulse width HIGH or
LOW CPAB, CPBA
see Figs 7 and 10 2.7
3.3
−
3.0 to 3.6 3.3
0.9(2)
−
tsu
set-up time
An, Bn to CPAB, CPBA
see Figs 9 and 10 2.7
2.4
0.0
−
3.0 to 3.6 +2.1
−0.2(2)
−0.2
0.3(2)
−0.7
−0.2(2)
0.3
−
set-up time
An, Bn to LEAB, LEBA
see Figs 9 and 10 2.7
3.0 to 3.6 1.1
2.7 +2.0
3.0 to 3.6 +1.7
+1.2
−
−
set-up time
CEAB, CEBA to CPAB, CPBA
−
−
th
hold time
An, Bn to CPAB, CPBA
see Figs 9 and 10 2.7
1.1
−
3.0 to 3.6 +1.0
−0.1(2)
−
hold time
An, Bn to LEAB, LEBA
see Figs 9 and 10 2.7
1.6
0.1
−
3.0 to 3.6 1.4
0.1(2)
0.6
−
hold time
CEAB, CEBA to CPAB, CPBA
2.7
1.2
−
3.0 to 3.6 1.1
0.4(2)
−
fmax
maximum clock pulse
frequency
see Figs 7 and 10 2.7
150
190
−
3.0 to 3.6 150
240(2)
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Typical values at VCC = 3.3 V.
1999 Oct 14
11
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
AC WAVEFORMS
V
handbook, halfpage
A , B
I
n
n
V
M
input
GND
t
t
PHL
PLH
V
OH
B , A
n
n
V
M
output
MNA292
V
OL
Fig.6 The input An, Bn to output Bn, An propagation delay times.
Notes: VCC = 2.3 to 2.7 V
M = 0.5VCC
V
;
VX = VOL + 150 mV;
VY = VOH − 150 mV;
VI = VCC
;
VOL and VOH are typical output voltage drop that occur with the output load.
Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V
VM = 1.5 V;
VX = VOL + 300 mV;
VY = VOH − 300 mV;
VI = 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
1999 Oct 14
12
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
1/f
max
V
I
LE , CP
XX
input
V
V
XX
M
t
M
t
GND
t
W
PHL
PLH
V
OH
V
B , A output
M
n
n
V
OL
MNA293
Fig.7 Latch enable input LEAB, LEBA and clock input CPAB, CPBA to output Bn, An propagation delay times;
pulse width and fmax of CPAB, CPBA
.
V
I
OE
input
V
XX
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA294
Fig.8 3-state enable and disable times.
13
1999 Oct 14
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
V
I
V
A
B input
n
M
n,
GND
t
t
h
h
t
t
su
su
V
I
V
CP
LE
input
XX
M
XX,
MNA295
GND
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.9 Data set-up and hold times for An and Bn inputs to LEAB, LEBA, CPAB or CPBA inputs.
S1
2 × V
CC
open
GND
V
CC
R
500 Ω
L
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
50 pF
R
L
500 Ω
L
R
T
MNA296
Definitions for test circuit.
L = load capacitance including jig and probe capacitance
(See Chapter “AC characteristics”).
TEST
S1
open
C
VCC
<2.7 V
2.7 to 3.6 V 2.7 V
VI
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL = load resistance.
VCC
2 × VCC
RT = termination resistance should be equal to the output impedance Zo
of the pulse generator.
GND
Fig.10 Load circuitry for switching times.
1999 Oct 14
14
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
PACKAGE OUTLINE
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.25
0.5
1.0
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-02-03
95-02-10
SOT364-1
MO-153EE
1999 Oct 14
15
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Oct 14
16
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Oct 14
17
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
NOTES
1999 Oct 14
18
Philips Semiconductors
Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
74ALVCH162601
NOTES
1999 Oct 14
19
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68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245004/01/pp20
Date of release: 1999 Oct 14
Document order number: 9397 750 05257
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