74ALVCH162601DLG4 [TI]
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS;
| 型号： | 74ALVCH162601DLG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总15页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
FEATURES
DGG OR DL PACKAGE
(TOP VIEW)
•
•
•
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
OEAB
LEAB
A1
1
56 CLKENAB
55 CLKAB
2
3
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B1
UBT™ (Universal Bus Transceiver) Combines
D-Type Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, Clocked,
or Clock-Enabled Modes
4
GND
A2
GND
B2
5
6
A3
B3
7
V
CC
V
CC
•
•
B-Port Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
8
A4
A5
B4
B5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A6
GND
A7
B6
GND
B7
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
A8
B8
•
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
A9
B9
A10
A11
A12
GND
A13
A14
A15
B10
B11
B12
GND
B13
B14
B15
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape-and-reel order entry, the DGGR package is
abbreviated to GR.
V
CC
V
CC
A16
A17
B16
B17
DESCRIPTION
GND
A18
OEBA
LEBA
GND
B18
CLKBA
CLKENBA
This 18-bit universal bus transceiver is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH162601 combines D-type latches
and D-type flip-flops to allow data flow in transparent,
latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is
stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active.
When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
The B-port outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162601 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, UBT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
FUNCTION TABLE(1)
INPUTS
OUTPUT
B
CLKENAB
OEAB
LEAB
CLKAB
A
X
L
X
X
X
H
H
L
H
L
L
L
L
L
L
L
X
H
H
L
X
Z
L
X
X
H
X
X
L
H
(2)
X
B0
(2)
L
X
B0
L
↑
↑
L
L
L
H
X
H
(2)
L
L
L or H
B0
(1) A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA,
LEBA, CLKBA, and CLKENBA.
(2) Output level before the indicated steady-state input conditions were
established
XXX
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OEAB
CLKENAB
CLKAB
LEAB
56
55
2
28
30
29
27
LEBA
CLKBA
CLKENBA
OEBA
CE
1D
C1
3
A1
54
B1
CLK
CE
1D
C1
CLK
To 17 Other Channels
2
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
MAX UNIT
VCC Supply voltage range
Except I/O ports(2)
4.6
4.6
V
VI
Input voltage range
V
I/O ports(2)(3)
-0.5 VCC + 0.5
VO
IIK
Output voltage range(2)(3)
Input clamp current
-0.5 VCC + 0.5
V
VI < 0
-50
-50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
±50
±100
81
DGG package
DL package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
74
Tstg
-65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51.
3
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX
3.6
UNIT
VCC
Supply voltage
1.65
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
0.35 × VCC
VIL
Low-level input voltage
0.7
0.8
VCC
VCC
-4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-12
-12
-24
-2
High-level output current (A port)
High-level output current (B port)
Low-level output current (A port)
Low-level output current (B port)
IOH
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-6
-8
-12
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
12
24
2
IOL
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
6
8
12
10
85
∆t/∆v Input transition rise or fall rate
TA Operating free-air temperature
ns/V
-40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1)
VCC - 0.2
MAX UNIT
IOH = -100 µA
IOH = -4 mA
IOH = -6 mA
1.2
2
A port
2.3 V
1.7
IOH = -12 mA
2.7 V
2.2
3 V
2.4
IOH = -24 mA
IOH = -100 µA
IOH = -2 mA
IOH = -4 mA
3 V
2
VOH
V
1.65 V to 3.6 V
1.65 V
2.3 V
VCC - 0.2
1.2
1.9
1.7
2.4
2
B port
A port
B port
2.3 V
IOH = -6 mA
3 V
IOH = -8 mA
IOH = -12 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
2.7 V
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
IOL = 100 µA
IOL = 2 mA
IOL = 4 mA
3 V
0.55
VOL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
V
2.3 V
0.55
0.55
0.6
IOL = 6 mA
3 V
IOL = 8 mA
2.7 V
IOL = 12 mA
VI = VCC or GND
VI = 0.58 V
3 V
0.8
II
3.6 V
±5
µA
µA
25
-25
45
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
-45
75
VI = 0.8 V
VI = 2 V
-75
VI = 0 to 3.6 V(2)
VO = VCC or GND
VI = VCC or GND,
3.6 V
3.6 V
±500
±10
40
(3)
IOZ
µA
µA
µA
pF
pF
ICC
∆ICC
Ci
IO = 0
3.6 V
One input at VCC - 0.6 V,
VI = VCC or GND
Other inputs at VCC or GND
3 V to 3.6 V
3.3 V
750
Control inputs
A or B ports
4
8
Cio
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
5
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
140
MIN
MAX
150
MIN
MAX
150
(1)
fclock
tw
Clock frequency
Pulse duration
MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
LE high
3.3
3.3
2.3
2
3.3
3.3
2.4
1.6
1.2
2
3.3
3.3
2.1
1.6
1.1
1.7
0.8
1.4
1.7
0.6
CLK high or low
Data before CLK↑
CLK high
CLK low
tsu
Setup time
Hold time
Data before LE↓
ns
ns
1.3
2
CLKEN before CLK↑
Data after CLK↑
0.7
1.3
1.7
0.3
0.7
1.6
2
CLK high
CLK low
th
Data after LE↓
CLKEN after CLK↑
0.5
(1) This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP MIN
MAX MIN
150
MAX MIN
MAX
(1)
fmax
x
140
1.3
1
150
1.6
1
MHz
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
A
B
A
B
A
B
A
B
B
A
A
4.8
4.3
5.5
5
5.2
4.6
5.9
5.3
6.3
5.8
6.7
5.3
6.1
4.8
4.5
4.1
5.1
4.7
5.5
5
B
LEAB
LEBA
CLKAB
CLKBA
OEAB
OEAB
OEBA
OEBA
1
1.5
1
tpd
ns
1
1.5
1.3
1.6
1.8
1.1
1.3
6.1
5.6
6.1
5.7
5.5
5.2
1.6
1.4
1.6
1.8
1.1
1.6
ten
tdis
ten
tdis
5.7
4.8
5.2
4.4
ns
ns
ns
ns
(1) This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
(1)
TYP
41
6
TYP
50
6
Outputs enabled
Outputs disabled
Power dissipation
capacitance
Cpd
CL = 50 pF, f = 10 MHz
pF
(1)
(1) This information was not available at the time of publication.
6
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × V
CC
S1
Open
1 kΩ
From Output
Under Test
TEST
S1
GND
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
1 kΩ
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
7
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuit and Voltage Waveforms
8
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES026H–JULY 1995–REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
TEST
S1
6 V
S1
t
Open
6 V
GND
pd
500 Ω
Open
From Output
Under Test
t
t
/t
/t
PLZ PZL
GND
PHZ PZH
C = 50 pF
(see Note A)
L
500 Ω
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
Data
Input
1.5 V
1.5 V
Output
Control
(low-level
enabling)
2.7 V
0 V
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
(see Note B)
t
t
PZH
t
t
PLH
PHL
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
74ALVCH162601DLG4
74ALVCH162601DLRG4
74ALVCH162601GRE4
74ALVCH162601GRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
56
56
56
56
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
TSSOP
TSSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALVCH162601DGGR OBSOLETE TSSOP
DGG
DL
56
56
TBD
Call TI
Call TI
SN74ALVCH162601DL
SN74ALVCH162601DLR
SN74ALVCH162601GR
ACTIVE
ACTIVE
ACTIVE
SSOP
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
56
56
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ALVCH162601DLR SSOP
SN74ALVCH162601GR TSSOP
DL
56
56
1000
2000
330.0
330.0
32.4
24.4
11.35
8.6
18.67
15.6
3.1
1.8
16.0
12.0
32.0
24.0
Q1
Q1
DGG
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALVCH162601DLR
SN74ALVCH162601GR
SSOP
DL
56
56
1000
2000
346.0
346.0
346.0
346.0
49.0
41.0
TSSOP
DGG
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
74ALVCH162601GRE4
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
TI
74ALVCH162601GRG4
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
TI
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