74ALVCH16269DGGRE4 [TI]
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS; 12位至24位寄存总线交换器具有三态输出
| 型号： | 74ALVCH16269DGGRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS |
| 文件： | 总16页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
FEATURES
DGG OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEA
OEB1
2B3
GND
2B2
•
•
•
•
Operates From 1.65 V to 3.6 V
Max tpd of 5 ns at 3.3 V
OEB2
CLKENA2
2B4
GND
2B5
2
3
±24-mA Output Drive at 3.3 V
4
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
5
6
2B1
2B6
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
7
V
CC
V
CC
8
A1
A2
A3
GND
A4
A5
2B7
2B8
2B9
9
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
DESCRIPTION/ORDERING INFORMATION
A6
A7
A8
A9
GND
A10
A11
A12
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16269 is used in applications in
which two separate ports must be multiplexed onto,
or demultiplexed from, a single port. The device is
particularly suitable as an interface between
synchronous
microprocessors.
1B8
1B7
DRAMs
and
high-speed
V
CC
V
CC
Data is stored in the internal B-port registers on the
low-to-high transition of the clock (CLK) input when
the appropriate clock-enable (CLKENA) inputs are
low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit
word on the B port. For data transfer in the B-to-A
direction, a single storage register is provided. The
select (SEL) line selects 1B or 2B data for the A
outputs. The register on the A output permits the
fastest possible data transfer, extending the period
during which the data is valid on the bus. The control
terminals are registered so that all transactions are
synchronous with CLK. Data flow is controlled by the
active-low output enables (OEA, OEB1, OEB2).
1B1
1B2
GND
1B3
NC
1B6
1B5
GND
1B4
CLKENA1
CLK
SEL
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74ALVCH16269DL
TOP-SIDE MARKING
ALVCH16269
ALVCH16269
VH269
Tube
SSOP - DL
Tape and reel
Tape and reel
SN74ALVCH16269DLR
SN74ALVCH16269DGGR
SN74ALVCH16269KR
-40°C to 85°C
TSSOP - DGG
VFBGA - GQL
Tape and reel
VFBGA - ZQL (Pb-free)
74ALVCH16269ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as
possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the
outputs cannot be determined before the arrival of the first clock pulse.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
TERMINAL ASSIGNMENTS
1
2
OEB1
2B2
A1
3
4
5
6
A
B
C
D
A
B
C
D
E
F
2B3
2B1
A2
OEA
GND
VCC
OEB2 CLKENA2
2B4
2B6
2B8
2B10
2B12
1B12
1B10
1B8
1B6
1B4
GND
VCC
2B5
2B7
A4
A3
GND
GND
2B9
A6
A5
2B11
1B11
1B9
E
F
A7
A8
G
H
J
A9
A10
A12
1B2
NC
GND
VCC
GND
VCC
G
H
J
A11
1B1
1B3
1B7
GND
SEL
GND
CLK
1B5
K
CLKENA1
K
2
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
FUNCTION TABLES
OUTPUT ENABLE
INPUTS
CLK OEA OEB
OUTPUTS
A
Z
1B, 2B
Z
↑
↑
↑
↑
H
H
L
H
L
Z
Active
Z
H
L
Active
Active
L
Active
A-TO-B STORAGE (OEB = L)
INPUTS
OUTPUTS
CLKENA1
CLKENA2
CLK
A
L
1B 2B
(1)
L
L
H
H
L
↑
↑
↑
↑
↑
↑
X
L
H
2B0
2B0
L
(1)
H
L
L
L
L
L
H
L
H
H
(1)
(1)
(1)
H
H
H
L
1B0
1B0
1B0
L
L
H
X
H
(1)
H
2B0
(1) Output level before the indicated steady-state input conditions were
established
B-TO-A STORAGE (OEA = L)
INPUTS
CLK SEL 1B
OUTPUT
A
2B
X
(1)
X
X
↑
H
L
X
A0
(1)
X
L
X
A0
H
H
L
X
L
H
L
↑
H
X
X
X
↑
L
↑
L
H
H
(1) Output level before the indicated
steady-state input conditions
were established
3
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
29
2
CLK
C1
1D
OEB1
C1
1D
56
30
55
28
1
OEB2
CLKENA1
CLKENA2
SEL
C1
1D
OEA
1D
1 of 12 Channels
C1
G1
C1
23
8
1B1
1
1
A1
1D
CE
C1
1D
6
2B1
CE
C1
1D
Pin numbers shown are for the DGG and DL packages.
4
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
-0.5
-0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range
V
Except I/O ports(2)
I/O ports(2)(3)
4.6
V
VCC + 0.5
VCC + 0.5
-50
VO
IIK
Output voltage range(2)(3)
Input clamp current
V
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
-50
Continuous output current
Continuous current through each VCC or GND
±50
±100
81
DGG package
DL package
θJA
Package thermal impedance(4)
74
°C/W
GQL/ZQL package
42
Tstg
Storage temperature range
-65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
0.35 × VCC
0.7
0.8
VCC
VCC
-4
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-12
-12
-24
4
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
-40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN
TYP(1)
MAX UNIT
IOH = -100 µA
IOH = -4 mA
IOH = -6 mA
VCC - 0.2
1.2
2
VOH
2.3 V
1.7
2.2
2.4
2
V
IOH = -12 mA
2.7 V
3 V
IOH = -24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
V
VOL
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
VI = VCC or GND
VI = 0.58 V
3 V
0.55
II
3.6 V
±5
µA
µA
1.65 V
1.65 V
2.3 V
25
-25
45
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
2.3 V
-45
75
VI = 0.8 V
3 V
VI = 2 V
3 V
-75
VI = 0 to 3.6 V(2)
3.6 V
±500
±10
40
(3)
IOZ
VO = VCC or GND
3.6 V
µA
µA
µA
pF
pF
ICC
∆ICC
Ci
VI = VCC or GND, IO = 0
3.6 V
One input at VCC - 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
3.3 V
750
Control inputs VI = VCC or GND
A or B ports VO = VCC or GND
3.5
9
Cio
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
6
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
(1)
fclock
tw
Clock frequency
135
135
3.3
135 MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Pulse duration, CLK high or low
3.3
2
3.3
1.7
1.8
1.3
0.9
1.3
0.6
0.6
0.7
1.1
0.8
A data before CLK↑
2
B data before CLK↑
SEL before CLK↑
2.2
1.6
1
2.1
tsu
Setup time
Hold time
1.6
ns
ns
CLKENA1 or CLKENA2 before CLK↑
OE before CLK↑
1.2
1.5
0.7
0.7
1.1
1
1.6
A data after CLK↑
0.6
B data after CLK↑
0.6
th
SEL after CLK↑
0.7
CLKENA1 or CLKENA2 after CLK↑
OE after CLK↑
0.8
0.8
0.8
(1) This information was not available at the time of publication.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MIN
MAX
MIN
MAX
MIN
135
1
MAX
(1)
fmax
tpd
135
1
135
MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
B
A
B
A
B
A
8.2
6.4
7.9
7.6
8.1
7.5
7.3
5.8
6.7
6.2
6.9
6.8
6.2
5
CLK
CLK
CLK
1
1
1
1
6.1
5.9
6.1
5.6
ten
ns
ns
1
1
1
1
tdis
1
1
(1) This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
87
TYP
120
118
(1)
All outputs enabled
All outputs disabled
Power dissipation
capacitance per exchanger
Cpd
CL = 50 pF, f = 10 MHz
pF
(1)
80.5
(1) This information was not available at the time of publication.
7
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
www.ti.com
SCES019N–JULY 1995–REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
S1
GND
t
Open
V
LOAD
GND
pd
/t
/t
C
t
t
L
PLZ PZL
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
V
/2
/2
2 × V
2 × V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3 V ± 0.3 V
0.3 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
V + V
∆
OL
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
74ALVCH16269DGGRE4
74ALVCH16269DGGRG4
74ALVCH16269DLG4
74ALVCH16269DLRG4
74ALVCH16269ZQLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
ZQL
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74ALVCH16269DGGR
SN74ALVCH16269DL
SN74ALVCH16269DLR
SN74ALVCH16269KR
ACTIVE
ACTIVE
ACTIVE
NRND
TSSOP
SSOP
SSOP
DGG
DL
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
(mm)
16
74ALVCH16269ZQLR
ZQL
56
56
56
56
56
SITE 32
SITE 41
SITE 41
SITE 32
SITE 60
4.8
8.6
7.3
15.6
18.67
7.3
1.45
1.8
8
12
16
8
16
24
32
16
16
Q1
Q1
Q1
Q1
Q1
SN74ALVCH16269DGGR DGG
24
SN74ALVCH16269DLR
SN74ALVCH16269KR
SN74ALVCH16269KR
DL
32
11.35
4.8
3.1
GQL
GQL
16
1.45
1.5
16
4.8
7.3
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
74ALVCH16269ZQLR
SN74ALVCH16269DGGR
SN74ALVCH16269DLR
SN74ALVCH16269KR
SN74ALVCH16269KR
ZQL
DGG
DL
56
56
56
56
56
SITE 32
SITE 41
SITE 41
SITE 32
SITE 60
346.0
346.0
346.0
346.0
342.9
346.0
346.0
346.0
346.0
336.6
33.0
41.0
49.0
33.0
28.58
GQL
GQL
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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