74AVC16836ADGV [NXP]

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State); 与倒寄存器的20位驱动程序注册的启用和动态控制的输出(三态)
74AVC16836ADGV
型号: 74AVC16836ADGV
厂家: NXP    NXP
描述:

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs (3-State)
与倒寄存器的20位驱动程序注册的启用和动态控制的输出(三态)

驱动
文件: 总11页 (文件大小:119K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
74AVC16836A  
20-bit registered driver with inverted  
register enable and  
Dynamic Controlled Outputs (3-State)  
Product data  
2002 Aug 02  
Supersedes data of 2000 Aug 03  
Philips  
Semiconductors  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
FEATURES  
PIN CONFIGURATION  
Wide supply voltage range of 1.2 V to 3.6 V  
OE  
1
2
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
CP  
Complies with JEDEC standard no. 8-1A/5/7.  
CMOS low power consumption  
Y
Y
A
A
0
1
0
1
3
Input/output tolerant up to 3.6 V  
GND  
4
GND  
Y
2
5
A
2
DCO (Dynamic Controlled Output) circuit dynamically changes  
output impedance, resulting in noise reduction without speed  
degradation  
Y
6
A
V
A
A
A
3
3
V
7
CC  
CC  
4
Y
4
8
Low inductance multiple V and GND pins for minimum noise  
CC  
and ground bounce  
Y
Y
9
5
6
5
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
6
Power off disables 74AVC16836A outputs, permitting Live  
GND  
GND  
Insertion  
Y
Y
Y
A
A
A
A
A
A
7
8
9
7
Integrated input diodes to minimize input overshoot and  
undershoot  
8
9
Full PC133 solution provided when used with PCK2509S or  
Y
PCK2510S and CBT16292  
10  
10  
11  
12  
Y
11  
12  
Y
DESCRIPTION  
GND  
GND  
The 74AVC16836A is a 20-bit universal bus driver. Data flow is  
controlled by output enable (OE), latch enable (LE) and clock inputs  
(CP).  
Y
Y
Y
A
A
A
V
A
A
13  
14  
15  
13  
14  
15  
CC  
16  
17  
This product is designed to have an extremely fast propagation  
delay and a minimum amount of power consumption.  
V
CC  
Y
16  
17  
To ensure the high-impedance state during power up or power down,  
Y
OE should be tied to V through a pullup resistor (Live Insertion).  
CC  
GND  
GND  
A Dynamic Controlled Output (DCO) circuitry is implemented to  
support termination line drive during transient. See the graphs on  
page 8 for typical curves.  
Y
Y
A
A
18  
19  
18  
19  
NC  
LE  
SH00159  
QUICK REFERENCE DATA  
GND = 0 V; T  
= 25 °C; t = t 2.0 ns; C = 30 pF.  
amb  
r
f
L
SYMBOL  
PARAMETER  
CONDITIONS  
TYPICAL  
UNIT  
V
V
V
= 1.8 V  
= 2.5 V  
= 3.3 V  
2.4  
1.7  
1.5  
CC  
CC  
CC  
Propagation delay  
An to Yn  
t
t
/t  
ns  
PHL PLH  
Propagation delay  
LE to Yn;  
CP to Yn  
V
CC  
V
CC  
V
CC  
= 1.8 V  
= 2.5 V  
= 3.3 V  
2.7  
2.1  
1.7  
/t  
ns  
PHL PLH  
C
C
Input capacitance  
3.8  
25  
6
pF  
pF  
I
Outputs enabled  
Output disabled  
1
Power dissipation capacitance per buffer  
V = GND to V  
I CC  
PD  
NOTE:  
1. C is used to determine the dynamic power dissipation (P in µW):  
PD  
D
2
2
P
= C × V  
× f + S (C × V  
× f ) where: f = input frequency in MHz; C = output load capacitance in pF;  
CC o i L  
D
PD  
CC  
i
L
2
f = output frequency in MHz; V = supply voltage in V; S (C × V  
o
× f ) = sum of outputs.  
o
CC  
L
CC  
ORDERING INFORMATION  
TEMPERATURE  
RANGE  
DRAWING  
NUMBER  
PACKAGES  
ORDER CODE  
56-Pin Plastic 0.5 mm pitch TSSOP  
56-Pin Plastic 0.4 mm pitch TVSOP  
–40 to +85 °C  
–40 to +85 °C  
74AVC16836ADGG  
74AVC16836ADGV  
SOT364-1  
SOT481-2  
2
2002 Aug 02  
853-2211 28696  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
PIN DESCRIPTION  
LOGIC SYMBOL (IEEE/IEC)  
PIN NUMBER  
SYMBOL NAME AND FUNCTION  
1
56  
29  
28  
NC  
No connection  
OE  
CP  
LE  
EN1  
2C3  
2, 3, 5, 6, 8, 9, 10, 12,  
13, 14, 15, 16, 17, 19,  
20, 21, 23, 24, 26, 27  
Y to Y  
Data outputs  
C3  
G2  
0
19  
4, 11, 18, 25, 32, 35, 39,  
46, 53  
GND  
Ground (0V)  
55  
2
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
54  
52  
51  
49  
48  
47  
45  
44  
43  
42  
7, 22, 35, 50  
V
CC  
Positive supply voltage  
5
Output enable input  
(active LOW)  
1
OE  
6
1
1
3D  
8
Latch enable input  
(active LOW)  
29  
56  
LE  
9
10  
12  
13  
CP  
Clock input  
55, 54, 52, 51, 49, 48,  
47, 45, 44, 43, 42, 41,  
40, 38, 37, 36, 34, 33,  
31, 30  
A to A  
0
Data inputs  
19  
14  
15  
16  
17  
19  
20  
21  
23  
Y
A
A
A
A
A
A
A
A
A
A
A
9
9
Y
10  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
41  
40  
38  
37  
36  
34  
33  
31  
30  
Y
11  
12  
13  
14  
15  
16  
17  
18  
19  
LOGIC SYMBOL  
Y
Y
Y
Y
Y
Y
Y
Y
OE  
24  
26  
27  
CP  
LE  
SH00160  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
OE  
H
L
LE  
X
CP  
X
X
X
A
X
L
Z
L
A
D
1
L
Y
1
L
L
H
L
H
L
LE  
L
H
H
H
H
CP  
L
H
X
X
H
1
L
H
L
Y
0
Y
0
2
L
TO THE 17 OTHER CHANNELS  
H
L
X
Z
=
=
=
=
=
HIGH voltage level  
LOW voltage level  
Don’t care  
High impedance “off” state  
LOW-to-HIGH level transition  
SH00201  
TYPICAL INPUT (DATA OR CONTROL)  
NOTES:  
V
CC  
1. Output level before the indicated steady-state input conditions  
were established, provided that CP is high before LE goes low.  
2. Output level before the indicated steady-state input conditions  
were established.  
A1  
SH00200  
3
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
168-pin SDR SDRAM DIMM  
BACK SIDE  
FRONT SIDE  
AVC16836A  
AVC16836A  
AVC16836A  
PCK2509S or PCK2510S  
The PLL clock distribution device and AVC registered drivers reduce  
signal loads on the memory controller and prevent timing delays and  
waveform distortions that would cause unreliable operation  
SW00409  
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
MAX  
UNIT  
1.65  
2.3  
3.0  
1.95  
2.7  
3.6  
DC supply voltage (according to JEDEC Low Voltage Standards)  
V
V
CC  
DC supply voltage (for low voltage applications)  
DC Input voltage range  
1.2  
0
3.6  
3.6  
3.6  
V
V
V
I
DC output voltage range; output 3-State  
DC output voltage range; output HIGH or LOW state  
Operating free-air temperature range  
0
V
O
V
0
V
CC  
T
amb  
–40  
0
+85  
30  
°C  
V
= 1.65 to 2.3 V  
= 2.3 to 3.0 V  
= 3.0 to 3.6 V  
CC  
V
0
20  
t , t  
r
Input rise and fall times  
ns/V  
CC  
f
V
0
10  
CC  
ABSOLUTE MAXIMUM RATINGS  
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).  
SYMBOL PARAMETER CONDITIONS RATING  
DC supply voltage  
UNIT  
V
V
I
–0.5 to +4.6  
–50  
CC  
DC input diode current  
V t0  
I
mA  
V
IK  
1
V
DC input voltage  
For all inputs  
–0.5 to 4.6  
"50  
I
I
DC output diode current  
V
O
uV or V t 0  
mA  
V
OK  
CC  
O
V
DC output voltage; output 3-State  
DC output voltage; output HIGH or LOW state  
DC output source or sink current  
Note 1  
Note 1  
–0.5 to 4.6  
O
V
I
–0.5 to V +0.5  
V
O
CC  
V
O
= 0 to V  
CC  
mA  
mA  
°C  
"50  
"100  
O
I
, I  
DC V or GND current  
GND CC  
CC  
T
stg  
Storage temperature range  
–65 to +150  
Power dissipation per package  
–plastic thin-medium-shrink (TSSOP)  
For temperature range: –40 to +125 °C  
above +55°C derate linearly with 8 mW/K  
P
TOT  
mW  
600  
NOTE:  
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
4
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
DC ELECTRICAL CHARACTERISTICS  
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).  
LIMITS  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
Temp = -40°C to +85°C  
UNIT  
1
MIN  
TYP  
MAX  
V
V
V
V
V
V
V
V
V
= 1.2 V  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
= 1.65 to 1.95 V  
= 2.3 to 2.7 V  
= 3.0 to 3.6 V  
= 1.2 V  
0.65V  
0.9  
1.2  
1.5  
CC  
V
HIGH level Input voltage  
V
IH  
1.7  
2.0  
GND  
= 1.65 to 1.95 V  
= 2.3 to 2.7 V  
= 3.0 to 3.6 V  
0.9  
1.2  
1.5  
0.35V  
0.7  
CC  
V
LOW level Input voltage  
HIGH level output voltage  
V
V
IL  
0.8  
= 1.65 to 3.6 V; V = V or V ;  
= –100 µA  
I
IH  
IL  
V
*0.20  
V
CC  
CC  
I
O
V
CC  
V
CC  
V
CC  
V
CC  
= 1.65 V; V = V or V ; I = –4 mA  
V
V
V
0.45  
V
V
V
0.10  
*
*
*
*
I
IH  
IL  
O
CC  
CC  
CC  
CC  
V
OH  
= 2.3 V; V = V or V ; I = –8 mA  
0.55  
0.70  
0.28  
0.32  
*
*
I
IH  
IL  
O
CC  
CC  
= 3.0 V; V = V or V ; I = –12 mA  
I
IH  
IL  
O
= 1.65 to 3.6 V; V = V or V ;  
= 100 µA  
I
IH  
IL  
GND  
0.20  
I
O
V
V
V
V
= 1.65 V; V = V or V ; I = 4 mA  
0.10  
0.26  
0.36  
0.45  
0.55  
0.70  
CC  
CC  
CC  
CC  
I
IH  
IL  
O
V
LOW level output voltage  
V
OL  
= 2.3 V; V = V or V ; I = 8 mA  
I
IH  
IL  
O
= 3.0 V; V = V or V ; I = 12 mA  
I
IH  
IL  
O
= 3.6 V;  
CC  
I
Input leakage current  
0.1  
0.1  
0.1  
2.5  
"10  
5
µA  
µA  
I
V = V or GND  
I
I
3-State output OFF-state current  
V
CC  
= 0 V; V or V = 3.6 V  
I O  
OFF  
V
V
= 1.65 to 2.7 V; V = V or V ;  
I IH IL  
CC  
O
= V or GND  
CC  
I
3-State output OFF-state current  
Quiescent supply current  
µA  
µA  
OZ  
V
V
= 3.0 to 3.6 V; V = V or V ;  
I IH IL  
CC  
O
0.1  
10  
= V or GND  
CC  
V
= 1.65 to 2.7 V; V = V or GND; I = 0  
0.1  
0.2  
20  
40  
CC  
CC  
I
CC  
O
I
CC  
V
= 3.0 to 3.6 V; V = V or GND; I = 0  
I
CC  
O
NOTE:  
1. All typical values are at T  
= 25 °C.  
amb  
5
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
AC CHARACTERISTICS  
GND = 0 V; t = t 2.0 ns; C = 30 pF  
r
f
L
LIMITS  
V = 1.8 ± 0.15 V  
CC  
V
=
V
1.2 V  
=
CC  
CC  
WAVEFORM  
SYMBOL  
PARAMETER  
V
CC  
= 3.3 ± 0.3 V  
V
CC  
= 2.5 ± 0.2 V  
UNIT  
1.5 ± 0.1 V  
1
1
1
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
MIN  
MAX  
TYP  
Propagation  
delay  
An to Yn  
1, 7  
2, 7  
3, 7  
6, 7  
6, 7  
0.7  
1.5  
2.7  
3.4  
3.0  
3.6  
4.8  
0.8  
1.7  
3.2  
3.5  
3.2  
4.0  
4.7  
1.0  
2.4  
4.4  
5.0  
4.1  
5.4  
7.5  
2.0  
5.3  
4.7  
5.0  
5.7  
6.0  
6.6  
ns  
ns  
ns  
ns  
ns  
Propagation  
delay  
LE to Yn  
t
/t  
0.7  
0.7  
1.0  
1.0  
1.7  
1.6  
1.9  
2.5  
1.0  
0.8  
1.0  
1.0  
2.1  
1.7  
2.4  
2.1  
1.5  
1.2  
1.5  
1.5  
2.7  
2.3  
3.0  
3.7  
2.0  
2.0  
2.5  
2.5  
5.6  
4.7  
6.8  
7.6  
PHL PLH  
Propagation  
delay  
CP to Yn  
3-State output  
enable time  
OE to Yn  
t
t
/t  
PZH PZL  
3-State output  
disable time  
OE to Yn  
/t  
PHZ PLZ  
CP pulse width  
HIGH or LOW  
3, 7  
2, 7  
5, 7  
4, 7  
5, 7  
4, 7  
3, 7  
1.0  
1.0  
0.2  
0.3  
1.2  
1.0  
500  
1.2  
1.2  
0.3  
0.6  
0.6  
0.5  
400  
2.0  
2.0  
0.2  
0.9  
0.6  
0.4  
250  
ns  
ns  
t
W
LE pulse width  
HIGH  
Set-up time  
An to CP  
0
0
0
0.3  
1.3  
0.6  
0.2  
0
ns  
t
SU  
Set-up time  
An to LE  
0
0.2  
0.2  
0.1  
0.4  
0.2  
0
1.2  
0.1  
–0.7  
ns  
Hold time  
An to CP  
0.5  
0.5  
ns  
t
h
Hold time  
An to LE  
ns  
Maximum clock  
pulse frequency  
f
MHz  
max  
NOTE:  
1. All typical values are measured at T  
= 25°C and at V = 1.8 V, 2.5 V, 3.3 V.  
amb  
CC  
6
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
AC WAVEFORMS FOR V = 3.0 V TO 3.6 V RANGE  
CC  
V
I
V
V
V
V
= 0.5 V  
M
X
Y
CC  
An  
INPUT  
V
= V + 0.300 V  
= V – 0.300 V  
M
OL  
OH  
GND  
and V are the typical output voltage drop that occur with the  
OL  
OH  
th  
th  
output load.  
V = V  
t
t
SU  
SU  
I
CC  
V
I
LE  
INPUT  
V
M
AC WAVEFORMS FOR V = 2.3 V TO 2.7 V AND  
CC  
GND  
V
< 2.3 V RANGE  
CC  
NOTE: The shaded areas indicate when the input is permitted to change  
V
V
V
V
= 0.5 V  
M
X
Y
OL  
CC  
for predictable output performance.  
V = 0.5V at V = 2.3 to 2.7 V  
= V + 0.15 V  
OL  
M CC CC  
= V – 0.15 V  
SH00166  
OH  
and V are the typical output voltage drop that occur with the  
OH  
Waveform 4. Data set-up and hold times for the An input to  
the LE input  
output load.  
V = V  
I
CC  
V
I
V
I
V
CP INPUT  
M
A
n
V
M
INPUT  
GND  
GND  
t
su  
t
su  
t
t
PLH  
PHL  
t
h
t
h
V
Y
OH  
n
V
I
An INPUT  
V
M
OUTPUT  
GND  
V
OL  
NOTE: V = 0.5V at V = 2.3 to 2.7 V  
M
CC  
CC  
V
OH  
SH00132  
V
M
Yn OUTPUT  
Waveform 1. Input (An) to output (Yn) propagation delay  
V
OL  
NOTE: The shaded areas indicate when the input is permitted to change  
for predictable output performance.  
V
I
V
= 0.5V at V = 2.3 to 2.7 V  
M
CC CC  
SH00136  
V
V
M
M
LE INPUT  
GND  
Waveform 5. Data set-up and hold times for the An input to  
the clock CP input  
t
W
t
t
PLH  
PHL  
V
OH  
V
I
V
M
Yn OUTPUT  
V
OL  
nOE INPUT  
GND  
V
M
NOTE: V = 0.5 V at V = 2.3 to 2.7 V  
M
CC  
CC  
SH00165  
Waveform 2. Latch enable input (LE) pulse width, the latch  
enable input to output (Yn) propagation delays.  
t
t
PZL  
PLZ  
V
CC  
OUTPUT  
LOW-to-OFF  
OFF-to-LOW  
V
M
1/f  
MAX  
V
X
V
V
I
OL  
V
V
M
M
CP INPUT  
GND  
t
t
PZH  
PHZ  
t
W
V
OH  
t
t
PLH  
PHL  
OUTPUT  
V
Y
HIGH-to-OFF  
OFF-to-HIGH  
V
M
V
OH  
V
Yn OUTPUT  
M
GND  
outputs  
enabled  
outputs  
disabled  
outputs  
enabled  
V
OL  
NOTE: V = 0.5V at V = 2.3 to 2.7 V  
M
CC  
CC  
SH00135  
NOTE: V = 0.5V at V = 2.3 to 2.7 V  
M
CC  
CC  
SH00137  
Waveform 3. The clock (CP) to Yn propagation delays, the  
clock pulse width and the maximum clock frequency.  
Waveform 6. 3-State enable and disable times  
7
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
TEST CIRCUIT  
GRAPHS  
S
1
2 * V  
V
CC  
CC  
3.5  
3
Open  
GND  
R
R
L
L
2.5  
2
V
V
O
I
V
= 3.3 V  
CC  
PULSE  
GENERATOR  
D.U.T.  
1.5  
1
R
T
C
V
CC  
L
= 2.5 V  
V
CC  
0.5  
= 1.8 V  
Test Circuit for switching times  
0
0
50  
100  
I
OUTPUT CURRENT (mA)  
OL  
150  
200  
250  
DEFINITIONS  
R
L
C
L
R
T
= Load resistor  
= Load capacitance includes jig and probe capacitance  
= Termination resistance should be equal to Z of pulse generators.  
OUT  
SH00204  
SWITCH POSITION  
TEST  
S
V
V
R
L
1
CC  
I
Figure 1. Output voltage (V ) vs. output current (I  
)
OL  
OL  
t
t
Open  
< 2.3 V  
2.3–2.7 V  
3.0 V  
V
V
1000  
500 Ω  
500 Ω  
PLH/ PHL  
CC  
CC  
t
t
t
PLZ/ PZL  
2 < V  
CC  
t
GND  
V
CC  
PHZ/ PZH  
3.5  
SV01018  
3.0  
2.5  
2.0  
Waveform 7. Load circuitry for switching times  
1.5  
1.0  
V
= 3.3 V  
CC  
0.5  
V
CC  
V
CC  
= 2.5 V  
–150  
= 1.8 V  
0.0  
–50  
–250  
–200  
–100  
0
I
OUTPUT CURRENT (mA)  
OH  
SH00205  
Figure 2. Output voltage (V ) vs. output current (I  
)
OH  
OH  
A Dynamic Controlled Output (DCO) circuit is designed in. During  
the transition, it initially lowers the output impedance to effectively  
drive the load and, subsequently, raises the impedance to reduce  
noise. Figures 1 and 2 show V vs. I and V vs. I curves to  
OL  
OL  
OH  
OH  
illustrate the output impedance and drive capability of the circuit. At  
the beginning of the signal transition, the DCO circuit provides a  
maximum dynamic drive that is equivalent to a high drive standard  
output device.  
8
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm  
SOT364-1  
9
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 4.4 mm  
SOT481-2  
10  
2002 Aug 02  
Philips Semiconductors  
Product data  
20-bit registered driver with inverted register enable  
and Dynamic Controlled Outputs (3-State)  
74AVC16836A  
Data sheet status  
Product  
status  
Definitions  
[1]  
Data sheet status  
[2]  
Objective data  
Development  
This data sheet contains data from the objective specification for product development.  
Philips Semiconductors reserves the right to change the specification in any manner without notice.  
Preliminary data  
Product data  
Qualification  
Production  
This data sheet contains data from the preliminary specification. Supplementary data will be  
published at a later date. Philips Semiconductors reserves the right to change the specification  
without notice, in order to improve the design and supply the best possible product.  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply.  
Changes will be communicated according to the Customer Product/Process Change Notification  
(CPCN) procedure SNW-SQ-650A.  
[1] Please consult the most recently issued data sheet before initiating or completing a design.  
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL  
http://www.semiconductors.philips.com.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Koninklijke Philips Electronics N.V. 2002  
Contact information  
All rights reserved. Printed in U.S.A.  
For additional information please visit  
http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
Date of release: 08-02  
9397 750 10178  
For sales offices addresses send e-mail to:  
sales.addresses@www.semiconductors.philips.com.  
Document order number:  
Philips  
Semiconductors  

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