74HC373BQ [NXP]
Octal D-type transparent latch; 3-state; 八路D型透明锁存器;三态
| 型号： | 74HC373BQ |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparent latch; 3-state |
| 文件： | 总26页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 5 — 13 December 2011
Product data sheet
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
D input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to:
• 74HC563; 74HCT563: but inverted outputs and different pin arrangement
• 74HC573; 74HCT573: but different pin arrangement
2. Features and benefits
3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74HC373N
40 C to +125 C
40 C to +125 C
40 C to +125 C
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
SOT339-1
SOT360-1
74HCT373N
74HC373D
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
74HCT373D
74HC373DB
74HCT373DB
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
74HC373PW 40 C to +125 C
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
74HCT373PW
74HC373BQ
40 C to +125 C
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
74HCT373BQ
body 2.5 4.5 0.85 mm
4. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
2
4
7
5
6
8
9
LATCH
1 TO 8
3-STATE
OUTPUTS
13
14
17
18
12
15
16
19
LE
11
1
OE
001aae050
Fig 1. Functional diagram
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
2 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
1
OE
LE
EN
C1
11
11
3
2
1D
D0
Q0
LE
3
4
2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
D1
D2
D3
Q1
Q2
Q3
5
7
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
D4
D5
D6
D7
Q4
Q5
Q6
Q7
OE
1
001aae048
001aae049
Fig 2. Logic symbol
Fig 3. IEC logic symbol
LE
LE
LE
LE
D
Q
001aae051
Fig 4. Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 5. Logic diagram
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
3 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
74HC373
74HCT373
74HC373
74HCT373
terminal 1
index area
1
2
20
19
18
17
16
15
14
13
12
11
OE
Q0
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
3
D0
4
D1
5
Q1
6
Q2
7
D2
(1)
GND
8
D3
9
Q3
10
GND
001aae047
Transparent top view
001aae046
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 6. Pin configuration DIP20, SO20, SSOP20 and
TSSOP20
Fig 7. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
3-state output enable input (active LOW)
3-state latch output
data input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
2, 5, 6, 9, 12, 15, 16, 19
D0, D1, D2, D3, D4, D5, D6, D7
3, 4, 7, 8, 13, 14, 17, 18
GND
LE
10
11
20
ground (0 V)
latch enable input (active HIGH)
supply voltage
VCC
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
4 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
6. Functional description
6.1 Function table
Table 3.
Function table[1]
Operating mode
Control
Input
Internal latches
Output
OE
LE
Dn
L
Qn
L
Enable and read register
(transparent mode)
L
H
L
H
l
H
L
H
L
Latch and read register
L
L
h
H
X
H
Z
Latch register and disable
outputs
H
X
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
35
+70
70
+150
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
65
[1]
[2]
[3]
[3]
[4]
DIP20 package
-
-
750
500
500
500
500
mW
mW
mW
mW
mW
SO20 package
SSOP20 package
TSSOP20 package
DHVQFN20 package
-
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
5 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC373
74HCT373
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
V
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
VCC
VCC
VO
output voltage
0
-
+25
-
0
-
+25
-
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
40
+125 C
-
-
-
-
-
-
-
ns/V
1.67
-
1.67
-
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 6.
Static characteristics 74HC373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 C
VIH HIGH-level input voltage
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
3.15
4.2
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
V
V
V
V
V
V
VCC = 4.5 V
-
VCC = 6.0 V
-
VIL
LOW-level input voltage
HIGH-level output voltage
VCC = 2.0 V
0.5
VCC = 4.5 V
-
1.35
VCC = 6.0 V
-
1.8
VOH
VI = VIH or VIL
-
-
-
-
-
-
-
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
V
V
V
V
V
VOL
LOW-level output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
0
0.1
V
0
0.1
V
0
0.1
V
0.15
0.26
0.26
0.1
0.5
V
0.16
V
II
input leakage current
-
-
A
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
ICC
supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
-
-
8.0
-
A
CI
input capacitance
3.5
pF
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
6 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 6.
Static characteristics 74HC373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 40 C to +85 C
VIH HIGH-level input voltage
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-level input voltage
HIGH-level output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
4.4
5.9
3.84
5.34
VOL
LOW-level output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
0.1
V
0.33
0.33
1.0
5.0
V
V
II
input leakage current
A
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
ICC
supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
80
A
T
amb = 40 C to +125 C
VIH
HIGH-level input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-level input voltage
HIGH-level output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
7 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 6.
Static characteristics 74HC373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
V
V
V
V
V
II
input leakage current
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
10.0 A
ICC
supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
-
160
A
Table 7.
Static characteristics 74HCT373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
VIH
VIL
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
2.0
-
1.6
1.2
-
V
V
LOW-level input voltage
HIGH-level output voltage
0.8
VOH
IO = 20 A; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VIH or VIL
4.4
4.5
-
-
V
V
3.98
4.32
VOL
LOW-level output voltage
IO = 20 A; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
-
-
0.0
0.1
V
0.16
0.26
0.1
0.5
V
II
input leakage current
-
-
A
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
A
ICC
additional supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
LE
OE
-
-
-
-
30
108
540
360
-
A
A
A
pF
150
100
3.5
CI
input capacitance
Tamb = 40 C to +85 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
V
V
0.8
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
8 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 7.
Static characteristics 74HCT373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 4.5 V
IO = 6.0 A; VCC = 4.5 V
VI = VIH or VIL
4.4
-
-
-
-
V
V
3.84
VOL
LOW-level output voltage
IO = 20 A; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
-
-
-
-
-
-
0.1
V
0.33
1.0
5.0
V
II
input leakage current
A
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
80
A
ICC
additional supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
LE
OE
-
-
-
-
-
-
135
675
450
A
A
A
Tamb = 40 C to +125 C
VIH
VIL
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
2.0
-
-
-
-
V
V
LOW-level input voltage
HIGH-level output voltage
0.8
VOH
IO = 20 A; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VIH or VIL
4.4
3.7
-
-
-
-
V
V
VOL
LOW-level output voltage
IO = 20 A; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
-
-
-
-
-
-
0.1
V
0.4
V
II
input leakage current
1.0
10
A
A
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
160
A
ICC
additional supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
LE
OE
-
-
-
-
-
-
147
735
490
A
A
A
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
9 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 8.
Dynamic characteristics 74HC373
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 2.0 V
-
-
-
-
41
15
12
12
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
LE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
-
50
18
15
14
175
35
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
30
[2]
[3]
[4]
ten
tdis
tt
enable time
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
44
16
13
150
30
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
disable time
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
47
17
14
150
30
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
transition time
pulse width
Qn; see Figure 8 and Figure 9
VCC = 2.0 V
-
-
-
14
5
60
12
10
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
tW
tsu
th
LE HIGH; see Figure 9
VCC = 2.0 V
80
16
14
17
6
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
set-up time
Dn to LE; see Figure 11
VCC = 2.0 V
50
10
9
14
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
hold time
Dn to LE; see Figure 11
VCC = 2.0 V
+5
+5
+5
-
8
3
2
45
-
-
-
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
[5]
CPD
power dissipation capacitance
per latch; VI = GND to VCC
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
10 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 2.0 V
-
-
-
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
33
LE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
-
-
-
220
44
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
37
[2]
[3]
[4]
ten
tdis
tt
enable time
disable time
transition time
pulse width
set-up time
hold time
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
33
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
-
-
-
190
38
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
33
Qn; see Figure 8 and Figure 9
VCC = 2.0 V
-
-
-
-
-
-
75
15
13
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
tW
tsu
th
LE HIGH; see Figure 9
VCC = 2.0 V
100
20
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
17
Dn to LE; see Figure 11
VCC = 2.0 V
65
13
11
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
Dn to LE; see Figure 11
VCC = 2.0 V
5
5
5
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
11 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
LE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
-
-
-
265
53
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
45
[2]
[3]
[4]
ten
tdis
tt
enable time
disable time
transition time
pulse width
set-up time
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
Qn; see Figure 8 and Figure 9
VCC = 2.0 V
-
-
-
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
tW
LE HIGH; see Figure 9
VCC = 2.0 V
120
24
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
20
tsu
Dn to LE; see Figure 11
VCC = 2.0 V
75
15
13
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
74HC_HCT373
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
12 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
th hold time
Conditions
Min
Typ
Max
Unit
Dn to LE; see Figure 11
VCC = 2.0 V
5
5
5
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
Table 9.
Dynamic characteristics 74HCT373
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 4.5 V
-
-
17
14
30
-
ns
ns
VCC = 5 V; CL = 15 pF
LE to Qn; see Figure 9
VCC = 4.5 V
-
-
16
13
32
-
ns
ns
VCC = 5 V; CL = 15 pF
OE to Qn; see Figure 10
VCC = 4.5 V
[2]
[3]
[4]
ten
tdis
tt
enable time
-
19
18
5
32
30
12
-
ns
ns
ns
ns
ns
disable time
OE to Qn; see Figure 10
VCC = 4.5 V
-
transition time
pulse width
Qn; see Figure 8 and Figure 9
VCC = 4.5 V
-
tW
tsu
th
LE HIGH; see Figure 9
VCC = 4.5 V
16
12
4
set-up time
Dn to LE; see Figure 11
VCC = 4.5 V
6
-
hold time
Dn to LE; see Figure 11
VCC = 4.5 V
4
-
1
-
-
ns
[5]
CPD
power dissipation capacitance
per latch;
41
pF
VI = GND to (VCC 1.5 V)
74HC_HCT373
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
13 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 9.
Dynamic characteristics 74HCT373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +85 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 4.5 V
-
-
-
-
-
-
-
-
-
38
40
40
38
15
-
ns
ns
ns
ns
ns
ns
ns
ns
LE to Qn; see Figure 9
VCC = 4.5 V
-
[2]
[3]
[4]
ten
tdis
tt
enable time
disable time
transition time
pulse width
set-up time
hold time
OE to Qn; see Figure 10
VCC = 4.5 V
-
OE to Qn; see Figure 10
VCC = 4.5 V
-
Qn; see Figure 8 and Figure 9
VCC = 4.5 V
-
tW
tsu
th
LE HIGH; see Figure 9
VCC = 4.5 V
20
15
4
Dn to LE; see Figure 11
VCC = 4.5 V
-
Dn to LE; see Figure 11
VCC = 4.5 V
-
Tamb = 40 C to +125 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 4.5 V
-
-
-
-
-
-
-
-
45
48
48
45
18
-
ns
ns
ns
ns
ns
ns
ns
LE to Qn; see Figure 9
VCC = 4.5 V
-
[2]
[3]
[4]
ten
tdis
tt
enable time
OE to Qn; see Figure 10
VCC = 4.5 V
-
disable time
OE to Qn; see Figure 10
VCC = 4.5 V
-
transition time
pulse width
Qn; see Figure 8 and Figure 9
VCC = 4.5 V
-
tW
LE HIGH; see Figure 9
VCC = 4.5 V
24
18
tsu
set-up time Dn to LE
Dn to LE; see Figure 11
VCC = 4.5 V
-
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
14 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 9.
Dynamic characteristics 74HCT373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
th
hold time Dn to LE
Dn to LE; see Figure 11
VCC = 4.5 V
4
-
-
ns
[1] tpd is the same as tPLH and tPHL
.
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
Dn input
V
M
t
t
PHL
PLH
90 %
V
M
Qn output
10 %
TLH
t
t
THL
001aae082
Measurement points are given in Table 10.
Fig 8. Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
LE input
V
M
t
W
t
t
PHL
PLH
90 %
Qn output
V
M
10 %
t
t
TLH
THL
001aae083
Measurement points are given in Table 10.
Fig 9. Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn)
74HC_HCT373
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
15 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
V
I
OE input
output
V
M
GND
t
t
PZL
PLZ
V
CC
V
LOW-to-OFF
OFF-to-LOW
M
10%
V
OL
t
t
PZH
PHZ
V
OH
90%
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 10.
Fig 10. 3-state enable and disable time
V
h
LE input
M
t
t
su
su
t
t
h
V
Dn input
M
001aae084
Measurement points are given in Table 10.
Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE)
Table 10. Measurement points
Type
Input
VM
Output
VM
74HC373
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT373
74HC_HCT373
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
16 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
Table 11. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC373
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT373
open
GND
VCC
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
17 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
12. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 13. Package outline SOT146-1 (DIP20)
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
18 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 14. Package outline SOT163-1 (SO20)
74HC_HCT373
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
19 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 15. Package outline SOT339-1 (SSOP20)
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
20 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 16. Package outline SOT360-1 (TSSOP20)
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
21 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
C
1
y
e
b
v
M
C
C
A
B
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 17. Package outline SOT764-1 (DHVQFN20)
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
22 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
13. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 13. Revision history
Document ID
Release date Data sheet status
20111213 Product data sheet
• Legal pages updated.
Change notice
Supersedes
74HC_HCT373 v.5
Modifications:
-
74HC_HCT373 v.4
74HC_HCT373 v.4
74HC_HCT373 v.3
74HC_HCT373_CNV v.2
20100903
20060120
19970827
Product data sheet
-
-
-
74HC_HCT373 v.3
Product data sheet
74HC_HCT373_CNV v.2
-
Product specification
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
23 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
24 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 13 December 2011
25 of 26
74HC373; 74HCT373
NXP Semiconductors
Octal D-type transparent latch; 3-state
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
6.1
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 December 2011
Document identifier: 74HC_HCT373
相关型号：
74HC373D-T
IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver
NXP
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