74HC373D [NXP]
Octal D-type transparent latch; 3-state; 八路D型透明锁存器;三态
| 型号： | 74HC373D |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparent latch; 3-state |
| 文件： | 总8页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT373
Octal D-type transparent latch;
3-state
September 1993
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT373
input and an output enable (OE) input are common to all
latches.
FEATURES
• 3-state non-inverting outputs for bus oriented
The “373” consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the Dn
inputs enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
applications
• Common 3-state output enable input
• Functionally identical to the “563”, “573” and “533”
• Output capability: bus driver
• ICC category: MSI
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
GENERAL DESCRIPTION
The 74HC/HCT373 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “373” is functionally identical to the “533”, “563” and
“573”, but the “563” and “533” have inverted outputs and
the “563” and “573” have a different pin arrangement.
The 74HC/HCT373 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PHL/ tPLH
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
t
CL = 15 pF; VCC = 5 V
Dn to Qn
12
14
13
3.5
41
ns
ns
pF
pF
LE to Qn
15
3.5
45
CI
input capacitance
power dissipation capacitance per latch
CPD
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
2
∑ (CL × VCC × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT373
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
OE
3-state output enable input (active LOW)
3-state latch outputs
2, 5, 6, 9, 12, 15, 16, 19
Q0 to Q7
D0 to D7
GND
LE
3, 4, 7, 8, 13, 14, 17, 18
data inputs
10
11
20
ground (0 V)
latch enable input (active HIGH)
positive supply voltage
VCC
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT373
FUNCTION TABLE
INPUTS
OE LE Dn
OUTPUTS
INTERNAL
OPERATING
MODES
LATCHES
Q0 to Q7
enable and
read
L
H
L
L
L
register
L
H
H
H
H
(transparent
mode)
latch and
read register
L
L
L
L
l
h
L
H
L
H
latch register
and disable
outputs
H
H
X
X
X
X
X
X
Z
Z
Notes
Fig.4 Functional diagram.
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
Fig.5 Logic diagram (one latch).
Fig.6 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT373
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
41
15
12
150
30
26
190
38
33
225
45
38
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
t
t
t
t
PHL/ tPLH propagation delay
LE to Qn
50
18
14
175
35
30
220
44
37
265
53
45
2.0 Fig.8
4.5
6.0
PZH/ tPZL 3-state output enable time
OE to Qn
44
16
13
150
30
26
190
38
33
225
45
38
2.0 Fig.9
4.5
6.0
PHZ/ tPLZ 3-state output disable time
OE to Qn
47
17
14
150
30
26
190
38
33
225
45
38
2.0 Fig.9
4.5
6.0
THL/ tTLH output transition time
14
5
4
60
12
10
75
15
13
90
18
15
2.0 Fig.7
4.5
6.0
tW
tsu
th
LE pulse width
HIGH
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.8
4.5
6.0
set-up time
Dn to LE
50
10
9
14
5
4
65
13
11
75
15
13
2.0 Fig.10
4.5
6.0
hold time
Dn to LE
5
5
5
−8
−3
−2
5
5
5
5
5
5
2.0 Fig.10
4.5
6.0
September 1993
5
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT373
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
Dn
LE
OE
0.30
1.50
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
17
16
19
18
5
30
32
32
30
12
38
40
40
38
15
45
48
48
45
18
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.8
4.5 Fig.9
4.5 Fig.9
4.5 Fig.7
4.5 Fig.8
4.5 Fig.10
4.5 Fig.10
tPHL/ tPLH propagation delay
LE to Qn
t
PZH/ tPZL 3-state output enable time
OE to Qn
tPHZ/ tPLZ 3-state output disable time
OE to Qn
tTHL/ tTLH output transition time
tW
tsu
th
LE pulse width
HIGH
16
12
4
4
20
15
4
24
18
4
set-up time
Dn to LE
6
hold time
Dn to LE
−1
September 1993
6
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT373
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the latch enable input
(LE) pulse width, the latch enable input to
output (Qn) propagation delays and the
output transition times.
Fig.7 Waveforms showing the input (Dn) to output
(Qn) propagation delays and the output
transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the 3-state enable and disable times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for Dn input to LE input.
September 1993
7
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT373
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
8
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