首页 |元器件品牌

74HC3G14DC-Q100H [NXP]

74HC(T)3G14-Q100 - Triple inverting Schmitt trigger SSOP 8-Pin;
74HC3G14DC-Q100H
型号： 74HC3G14DC-Q100H
厂家： NXP    NXP
描述：

74HC(T)3G14-Q100 - Triple inverting Schmitt trigger SSOP 8-Pin
文件： 总20页 (文件大小：149K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
74HC3G14-Q100;  
74HCT3G14-Q100  
Triple inverting Schmitt trigger  
Rev. 2 — 9 December 2013  
Product data sheet  
1. General description  
The 74HC3G14-Q100; 74HCT3G14-Q100 is a triple inverter with Schmitt-trigger inputs.  
Inputs include clamp diodes that enable the use of current limiting resistors to interface  
inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input  
signals into sharply defined jitter-free output signals.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Complies with JEDEC standard no. 7A  
Wide supply voltage range from 2.0 V to 6.0 V  
Input levels:  
For 74HC3G14-Q100: CMOS level  
For 74HCT3G14-Q100: TTL level  
High noise immunity  
Low power dissipation  
Balanced propagation delays  
Unlimited input rise and fall times  
Multiple package options  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
3. Applications  
Wave and pulse shaper for highly noisy environments  
Astable multivibrators  
Monostable multivibrators  
 
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
4. Ordering information  
Table 1.  
Ordering information  
Package  
Temperature range Name  
Type number  
Description  
Version  
74HC3G14DP-Q100 40 C to +125 C  
74HCT3G14DP-Q100  
TSSOP8  
plastic thin shrink small outline package; 8 leads;  
body width 3 mm; lead length 0.5 mm  
SOT505-2  
74HC3G14DC-Q100 40 C to +125 C  
74HCT3G14DC-Q100  
VSSOP8  
plastic very thin shrink small outline package; 8  
leads; body width 2.3 mm  
SOT765-1  
5. Marking  
Table 2.  
Marking  
Type number  
Marking code[1]  
74HC3G14DP-Q100  
74HCT3G14DP-Q100  
74HC3G14DC-Q100  
74HCT3G14DC-Q100  
H14  
T14  
H14  
T14  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
6. Functional diagram  
1A  
3Y  
2A  
1Y  
3A  
2Y  
A
Y
001aah728  
001aah729  
mna025  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
Fig 3. Logic diagram  
(one Schmitt trigger)  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
2 of 20  
 
 
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
7. Pinning information  
7.1 Pinning  
ꢀꢁ+&ꢂ*ꢃꢁꢄ4ꢃꢅꢅ  
ꢀꢁ+&7ꢂ*ꢃꢁꢄ4ꢃꢅꢅ  
ꢀ
ꢂ
ꢁ
ꢃ
ꢆ
ꢇ
ꢄ
ꢅ
ꢀ$  
ꢁ<  
9
&&  
ꢀ<  
ꢁ$  
ꢂ<  
ꢂ$  
*1'  
DDDꢀꢁꢁꢂꢃꢄꢅ  
Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)  
7.2 Pin description  
Table 3.  
Symbol  
1A, 2A, 3A  
GND  
Pin description  
Pin  
Description  
data input  
1, 3, 6  
4
ground (0 V)  
data output  
supply voltage  
1Y, 2Y, 3Y  
VCC  
7, 5, 2  
8
8. Functional description  
Table 4.  
Function table[1]  
Input  
nA  
L
Output  
nY  
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level.  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
3 of 20  
 
 
 
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
9. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Max  
+7.0  
20  
20  
25  
+50  
-
Unit  
V
VCC  
IIK  
supply voltage  
0.5  
[1]  
[1]  
[1]  
[1]  
[1]  
input clamping current  
output clamping current  
output current  
VI < 0.5 V or VI > VCC + 0.5 V  
VO < 0.5 V or VO > VCC + 0.5 V  
VO = 0.5 V to VCC + 0.5 V  
-
mA  
mA  
mA  
mA  
mA  
C  
IOK  
IO  
-
-
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
50  
65  
-
storage temperature  
total power dissipation  
+150  
300  
[2]  
mW  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.  
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.  
10. Recommended operating conditions  
Table 6.  
Recommended operating conditions  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter Conditions  
74HC3G14-Q100  
74HCT3G14-Q100  
Unit  
Min  
Typ  
5.0  
-
Max  
Min  
Typ  
5.0  
-
Max  
VCC  
VI  
supply voltage  
input voltage  
2.0  
0
6.0  
VCC  
VCC  
+125  
4.5  
0
5.5  
VCC  
VCC  
V
V
V
VO  
output voltage  
ambient temperature  
0
-
0
-
Tamb  
40  
+25  
40  
+25  
+125 C  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
4 of 20  
 
 
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
11. Static characteristics  
Table 7.  
Static characteristics  
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C.  
Symbol Parameter  
Conditions  
25 C  
40 C to +85 C 40 C to +125 C Unit  
Min Typ Max  
Min  
Max  
Min  
Max  
74HC3G14-Q100  
VOH  
HIGH-level  
VI = VT+ or VT  
output voltage  
IO = 20 A; VCC = 2.0 V  
IO = 20 A; VCC = 4.5 V  
IO = 20 A; VCC = 6.0 V  
IO = 4.0 mA; VCC = 4.5 V  
IO = 5.2 mA; VCC = 6.0 V  
VI = VT+ or VT  
1.9  
4.4  
5.9  
2.0  
4.5  
6.0  
-
-
-
-
-
1.9  
4.4  
-
-
-
-
-
1.9  
4.4  
5.9  
3.7  
5.2  
-
-
-
-
-
V
V
V
V
V
5.9  
4.18 4.32  
5.68 5.81  
4.13  
5.63  
VOL  
LOW-level  
output voltage  
IO = 20 A; VCC = 2.0 V  
IO = 20 A; VCC = 4.5 V  
IO = 20 A; VCC = 6.0 V  
IO = 4.0 mA; VCC = 4.5 V  
IO = 5.2 mA; VCC = 6.0 V  
-
-
-
-
-
-
0
0
0
0.1  
0.1  
0.1  
-
-
-
-
-
-
0.1  
0.1  
-
-
-
-
-
-
0.1  
0.1  
0.1  
0.4  
0.4  
1.0  
V
V
0.1  
V
0.15 0.26  
0.16 0.26  
0.33  
0.33  
1.0  
V
V
II  
input leakage VI = VCC or GND; VCC = 6.0 V  
current  
-
0.1  
1.0  
-
A  
ICC  
CI  
supply current per input pin; VCC = 6.0 V;  
VI = VCC or GND; IO = 0 A;  
-
-
-
-
-
10  
-
-
-
20  
-
A  
input  
2.0  
pF  
capacitance  
74HCT3G14-Q100  
VOH  
HIGH-level  
VI = VT+ or VT  
output voltage  
IO = 20 A; VCC = 4.5 V  
IO = 4.0 mA; VCC = 4.5 V  
VI = VIH or VIL  
4.4  
4.5  
-
-
4.4  
-
-
4.4  
3.7  
-
-
V
V
4.18 4.32  
4.13  
VOL  
LOW-level  
output voltage  
IO = 20 A; VCC = 4.5 V  
IO = 4.0 mA; VCC = 4.5 V  
-
-
-
0
0.1  
-
-
-
0.1  
-
-
-
0.1  
0.4  
V
0.15 0.26  
0.33  
1.0  
V
II  
input leakage VI = VCC or GND; VCC = 5.5 V  
current  
-
-
-
0.1  
1.0  
A  
ICC  
ICC  
supply current per input pin; VCC = 5.5 V;  
VI = VCC or GND; IO = 0 A;  
-
-
1.0  
-
-
10  
-
-
20  
A  
A  
additional  
per input;  
300  
375  
410  
supply current VCC = 4.5 V to 5.5 V;  
VI = VCC 2.1 V; IO = 0 A  
CI  
input  
-
2.0  
-
-
-
-
-
pF  
capacitance  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
5 of 20  
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
Table 8.  
Transfer characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 10.  
Symbol Parameter  
Conditions  
25 C  
40 C to +125 C  
Unit  
Min  
Typ Max  
Min  
Max  
Max  
(85 C) (125 C)  
74HC3G14-Q100  
VT+  
VT  
VH  
positive-going  
threshold voltage  
see Figure 5, Figure 6  
VCC = 2.0 V  
1.00 1.18 1.50 1.00  
2.30 2.60 3.15 2.30  
3.00 3.46 4.20 3.00  
1.50  
3.15  
4.20  
1.50  
3.15  
4.20  
V
V
V
VCC = 4.5 V  
VCC = 6.0 V  
negative-going  
threshold voltage  
see Figure 5, Figure 6  
VCC = 2.0 V  
0.30 0.60 0.90 0.30  
1.13 1.47 2.00 1.13  
1.50 2.06 2.60 1.50  
0.90  
2.00  
2.60  
0.90  
2.00  
2.60  
V
V
V
VCC = 4.5 V  
VCC = 6.0 V  
hysteresis voltage  
(VT+ VT); see Figure 5,  
Figure 6 and Figure 8  
VCC = 2.0 V  
VCC = 4.5 V  
VCC = 6.0 V  
0.30 0.60 1.00 0.30  
0.60 1.13 1.40 0.60  
0.80 1.40 1.70 0.80  
1.00  
1.40  
1.70  
1.00  
1.40  
1.70  
V
V
V
74HCT3G14-Q100  
VT+  
VT  
VH  
positive-going  
threshold voltage  
see Figure 5, Figure 6  
VCC = 4.5 V  
1.20 1.58 1.90 1.20  
1.40 1.78 2.10 1.40  
1.90  
2.10  
1.90  
2.10  
V
V
VCC = 5.5 V  
negative-going  
threshold voltage  
see Figure 5, Figure 6  
VCC = 4.5 V  
0.50 0.87 1.20 0.50  
0.60 1.11 1.40 0.60  
1.20  
1.40  
1.20  
1.40  
V
V
VCC = 5.5 V  
hysteresis voltage  
(VT+ VT); see Figure 5,  
Figure 6 and Figure 7  
VCC = 4.5 V  
VCC = 5.5 V  
0.40 0.71  
0.40 0.67  
-
-
0.40  
0.40  
-
-
-
-
V
V
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
6 of 20  
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
11.1 Waveforms transfer characteristics  
V
O
V
T+  
V
I
V
H
V
T−  
V
I
V
V
O
H
V
V
T+  
T−  
mna207  
mna208  
Fig 5. Transfer characteristic  
Fig 6. Definition of VT+, VTand VH  
mna031  
mna032  
2.0  
3.0  
I
CC  
I
CC  
(mA)  
(mA)  
2.0  
1.0  
1.0  
0
0
0
2.5  
5.0  
0
3.0  
6.0  
V (V)  
I
V (V)  
I
a. VCC = 4.5 V.  
Fig 7. Typical 74HCT3G14-Q100 transfer characteristics  
b. VCC = 5.5 V.  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
7 of 20  
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
mna029  
mna028  
1.0  
100  
I
CC  
(mA)  
I
CC  
(μA)  
0.8  
0.6  
0.4  
0.2  
0
50  
0
0
2.5  
5.0  
0
1.0  
2.0  
V (V)  
I
V (V)  
I
a. VCC = 2.0 V  
b. VCC = 4.5 V  
mna030  
1.6  
I
CC  
(mA)  
0.8  
0
0
3.0  
6.0  
V (V)  
I
c.  
VCC = 6.0 V  
Fig 8. Typical 74HC3G14-Q100 transfer characteristics  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
8 of 20  
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
12. Dynamic characteristics  
Table 9.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 10.  
Symbol Parameter  
Conditions  
25 C  
40 C to +125 C  
Unit  
Min  
Typ Max  
Min  
Max  
Max  
(85 C) (125 C)  
74HC3G14-Q100  
[1]  
[2]  
[3]  
tpd  
propagation delay  
nA to nY; see Figure 9  
VCC = 2.0 V  
-
-
-
53  
16  
13  
125  
25  
-
-
-
155  
31  
190  
38  
ns  
ns  
ns  
VCC = 4.5 V  
VCC = 6.0 V  
21  
26  
32  
tt  
transition time  
nY; see Figure 9  
VCC = 2.0 V  
-
-
-
-
20  
7
75  
15  
13  
-
-
-
-
-
95  
19  
16  
-
110  
22  
19  
-
ns  
ns  
ns  
pF  
VCC = 4.5 V  
VCC = 6.0 V  
5
CPD  
power dissipation  
capacitance  
VI = GND to VCC  
10  
74HCT3G14-Q100  
tpd propagation delay  
[1]  
[2]  
[3]  
nA to nY; see Figure 9  
VCC = 4.5 V  
-
21  
32  
-
40  
48  
ns  
tt  
transition time  
nY; see Figure 9  
VCC = 4.5 V  
-
-
6
15  
-
-
-
19  
-
22  
-
ns  
CPD  
power dissipation  
capacitance  
VI = GND to VCC 1.5 V  
10  
pF  
[1] tpd is the same as tPLH and tPHL  
[2] tt is the same as tTLH and tTHL  
[3] CPD is used to determine the dynamic power dissipation (PD in W).  
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
(CL VCC2 fo) = sum of the outputs.  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
9 of 20  
 
 
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
13. Waveforms  
V
I
V
V
M
nA input  
GND  
M
t
t
PHL  
PLH  
V
OH  
90 %  
V
V
nY output  
M
M
10 %  
V
OL  
t
t
TLH  
THL  
mna722  
Measurement points are given in Table 10.  
OL and VOH are typical voltage output levels that occur with the output load.  
V
Fig 9. The data input (nA) to output (nY) propagation delays and output transition times  
Table 10. Measurement points  
Type  
Input  
VM  
Output  
VM  
74HC3G14-Q100  
74HCT3G14-Q100  
0.5VCC  
1.3 V  
0.5VCC  
1.3 V  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
10 of 20  
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
CC  
V
CC  
V
V
O
I
R
L
S1  
G
open  
DUT  
R
T
C
L
001aad983  
Test data is given in Table 11.  
Definitions for test circuit:  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
CL = Load capacitance including jig and probe capacitance.  
RL = Load resistance.  
S1 = Test selection switch.  
Fig 10. Test circuit for measuring switching times  
Table 11. Test data  
Type  
Input  
VI  
Load  
CL  
S1 position  
tPHL, tPLH  
open  
tr, tf  
RL  
74HC3G14-Q100 GND to VCC  
74HCT3G14-Q100 GND to 3.0 V  
6 ns  
6 ns  
50 pF  
50 pF  
1 k  
1 k  
open  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
11 of 20  
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
14. Application information  
The slow input rise and fall times cause additional power dissipation, which can be  
calculated using the following formula:  
Padd = fi (tr  ICC(AV) + tf  ICC(AV)) VCC where:  
Padd = additional power dissipation (W);  
fi = input frequency (MHz);  
tr = input rise time (ns); 10 % to 90 %;  
tf = input fall time (ns); 90 % to 10 %;  
ICC(AV) = average additional supply current (A).  
ICC(AV) differs with positive or negative input transitions, as shown in Figure 11 and  
Figure 12.  
An example of a relaxation circuit using the 74HC3G14-Q100/74HCT3G14-Q100 is  
shown in Figure 13.  
mna036  
200  
ΔI  
CC(AV)  
(μA)  
150  
positive-going  
edge  
100  
50  
negative-going  
edge  
0
0
2.0  
4.0  
6.0  
V
(V)  
CC  
linear change of VI between 0.1VCC to 0.9VCC  
.
Fig 11. ICC(AV) as a function of VCC for 74HC3G14-Q100  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
12 of 20  
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
mna058  
200  
ΔI  
CC(AV)  
(μA)  
150  
100  
50  
positive-going  
edge  
negative-going  
edge  
0
0
2
4
6
V
(V)  
CC  
linear change of VI between 0.1VCC to 0.9VCC  
.
Fig 12. ICC(AV) as a function of VCC for 74HCT3G14-Q100  
R
C
mna035  
1
T
1
-- ---------------------  
For 74HC3G14-Q100: f =  
0.8 RC  
1
T
1
-- ------------------------  
For 74HCT3G14-Q100: f =  
0.67 RC  
For K-factor, see Figure 14  
Fig 13. Relaxation oscillator  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
13 of 20  
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
DDDꢀꢁꢁꢄꢆꢁꢂ  
DDDꢀꢁꢁꢄꢆꢇꢁ  
ꢂꢋꢌ  
.
ꢀꢋꢂ  
ꢀꢋꢌ  
ꢌꢋꢆ  
ꢌꢋꢄ  
ꢌꢋꢃ  
ꢌꢋꢂ  
ꢌ
.
ꢀꢋꢅ  
ꢀꢋꢌ  
ꢌꢋꢅ  
ꢌ
ꢂ
ꢁ
ꢃ
ꢅ
ꢄ
ꢃꢋꢅ  
ꢅꢋꢌ  
ꢅꢋꢅ  
9
ꢈꢉ9ꢊ  
&&  
9
ꢈꢉ9ꢊ  
&&  
K-factor for 74HC3G14-Q100  
K-factor for 74HCT3G14-Q100  
Fig 14. Typical K-factor for relaxation oscillator  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
14 of 20  
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
15. Package outline  
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm  
SOT505-2  
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
detail X  
1
4
e
w
M
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
max.  
0.15  
0.00  
0.95  
0.75  
0.38  
0.22  
0.18  
0.08  
3.1  
2.9  
3.1  
2.9  
4.1  
3.9  
0.47  
0.33  
0.70  
0.35  
8°  
0°  
mm  
1.1  
0.65  
0.25  
0.5  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-01-16  
SOT505-2  
- - -  
Fig 15. Package outline SOT505-2 (TSSOP8)  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
15 of 20  
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm  
SOT765-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )  
3
pin 1 index  
θ
L
p
L
detail X  
1
4
e
w
M
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT  
v
w
y
Z
θ
1
2
3
p
E
max.  
0.15  
0.00  
0.85  
0.60  
0.27  
0.17  
0.23  
0.08  
2.1  
1.9  
2.4  
2.2  
3.2  
3.0  
0.40  
0.15  
0.21  
0.19  
0.4  
0.1  
8°  
0°  
mm  
1
0.5  
0.12  
0.4  
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-06-07  
SOT765-1  
MO-187  
Fig 16. Package outline SOT765-1 (VSSOP8)  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
16 of 20  
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
16. Abbreviations  
Table 12. Abbreviations  
Acronym  
CMOS  
DUT  
Description  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Military  
ESD  
HBM  
MIL  
MM  
Machine Model  
17. Revision history  
Table 13. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice Supersedes  
- 74HC_HCT3G14_Q100 v.1  
74HC_HCT3G14_Q100 v.2 20131209  
Product data sheet  
Modifications:  
• Figure 14 added (typical K-factor for relaxation oscillator).  
74HC_HCT3G14_Q100 v.1 20131115  
Product data sheet  
-
-
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
17 of 20  
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
18. Legal information  
18.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use in automotive applications — This NXP  
18.2 Definitions  
Semiconductors product has been qualified for use in automotive  
applications. Unless otherwise agreed in writing, the product is not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer's own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
18.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
18 of 20  
 
 
 
 
 
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
18.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
19. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74HC_HCT3G14_Q100  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 9 December 2013  
19 of 20  
 
 
NXP Semiconductors  
74HC3G14-Q100; 74HCT3G14-Q100  
Triple inverting Schmitt trigger  
20. Contents  
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
7
7.1  
7.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
8
Functional description . . . . . . . . . . . . . . . . . . . 3  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 4  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Waveforms transfer characteristics . . . . . . . . . 7  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Application information. . . . . . . . . . . . . . . . . . 12  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17  
9
10  
11  
11.1  
12  
13  
14  
15  
16  
17  
18  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
18.1  
18.2  
18.3  
18.4  
19  
20  
Contact information. . . . . . . . . . . . . . . . . . . . . 19  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2013.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 9 December 2013  
Document identifier: 74HC_HCT3G14_Q100  
 

相关型号：

74HC3G14DP

 Inverting Schmitt-triggers
NXP

74HC3G14DP

 Triple inverting Schmitt triggerProduction
NEXPERIA

74HC3G14DP,118

 74HC(T)3G14 - Triple inverting Schmitt trigger TSSOP 8-Pin
NXP

74HC3G14DP,125

 74HC(T)3G14 - Triple inverting Schmitt trigger TSSOP 8-Pin
NXP

74HC3G14DP-Q100

 Triple inverting Schmitt trigger
NEXPERIA

74HC3G14DP-Q100H

 74HC(T)3G14-Q100 - Triple inverting Schmitt trigger TSSOP 8-Pin
NXP

74HC3G14GD

 Triple inverting Schmitt trigger
NXP

74HC3G16DP

 HC/UH SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PDSO8
NXP

74HC3G16DP

 Triple buffer gateProduction
NEXPERIA

74HC3G16GD

 HC/UH SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PDSO8
NXP

74HC3G34

 Triple Buffer Gate
NXP

74HC3G34-Q100

 Triple buffer gate
NEXPERIA
©2020 ICPDF网 联系我们和版权申明