74HC4017PW [NXP]
Johnson decade counter with 10 decoded outputs; 10解码输出约翰逊十进制计数器
| 型号： | 74HC4017PW |
| 厂家： | 
NXP |
| 描述： | Johnson decade counter with 10 decoded outputs |
| 文件： | 总12页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4017
Johnson decade counter with 10
decoded outputs
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
CP1) and an overriding asynchronous master reset input
(MR).
FEATURES
• Output capability: standard
• ICC category: MSI
The counter is advanced by either a LOW-to-HIGH
transition at CP0 while CP1 is LOW or a HIGH-to-LOW
transition at CP1 while CP0 is HIGH (see also function
table).
GENERAL DESCRIPTION
The 74HC/HCT4017 are high-speed Si-gate CMOS
devices and are pin compatible with the “4017” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
When cascading counters, the Q5-9 output, which is LOW
while the counter is in states 5, 6, 7, 8 and 9, can be used
to drive the CP0 input of the next counter.
A HIGH on MR resets the counter to zero
(Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the
clock inputs (CP0 and CP1).
The 74HC/HCT4017 are 5-stage Johnson decade
counters with 10 decoded active HIGH outputs (Q0 to Q9),
an active LOW output from the most significant flip-flop
(Q5-9), active HIGH and active LOW clock inputs (CP0 and
Automatic code correction of the counter is provided by an
internal circuit: following any illegal code the counter
returns to a proper counting mode within 11 clock pulses.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
ns
HC
HCT
21
tPHL/ tPLH
fmax
propagation delay CP0, CP1 to Qn
maximum clock frequency
CL = 15 pF; VCC = 5 V 20
77
67
3.5
36
MHz
pF
CI
input capacitance
3.5
35
CPD
power dissipation capacitance per package
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi+∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
3, 2, 4, 7, 10, 1, 5, 6, 9, 11 Q0 to Q9
decoded outputs
ground (0 V)
8
GND
Q5-9
CP1
CP0
MR
12
13
14
15
16
carry output (active LOW)
clock input (HIGH-to-LOW, edge-triggered)
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active HIGH)
positive supply voltage
VCC
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.1 Pin configuration.
December 1990
3
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Fig.4 Functional diagram.
FUNCTION TABLE
MR
CP0
CP1
OPERATION
H
X
X
Q0 = Q5-9 = H; Q1 to Q9 = L
L
L
L
L
L
L
H
↑
L
X
H
↓
↓
counter advances
counter advances
no change
no change
no change
L
X
H
↑
L
no change
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
↓ = HIGH-to-LOW clock transition
December 1990
4
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded
outputs
74HC/HCT4017
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
5
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
December 1990
6
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to+85
−40 to+125
min. typ. max. min. max. min. max.
tPHL/ tPLH
propagation delay
CP0 to Qn
63
23
18
230
46
39
290
58
49
345
69
59
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
2.0
4.5
6.0
Fig.9
Fig.9
Fig.9
Fig.9
Fig.8
Fig.8
Fig.9
Fig.8
Fig.8
Fig.8
Fig.7
Fig.7
Fig.8
tPHL/ tPLH
propagation delay
CP0 to Q5-9
63
23
18
230
46
39
290
58
49
345
69
59
2.0
4.5
6.0
t
PHL/ tPLH
propagation delay
CP1 to Qn
61
22
18
250
50
43
315
63
54
375
75
64
2.0
4.5
6.0
tPHL/ tPLH
propagation delay
CP1 to Q5-9
61
22
18
250
50
43
315
63
54
375
75
64
2.0
4.5
6.0
tPHL
propagation delay
MR to Q1−9
52
19
15
230
46
39
290
58
49
345
69
59
2.0
4.5
6.0
tPLH
propagation delay
MR to Q5−9, Q0
55
20
16
230
46
39
290
58
49
345
69
59
2.0
4.5
6.0
t
THL/ tTLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0
4.5
6.0
tW
master reset pulse
width; HIGH
80
16
14
19
7
6
100
20
17
120
24
20
2.0
4.5
6.0
trem
tsu
th
removal time
MR to CP0, CP1
5
5
5
−17
−6
−5
5
5
5
5
5
5
2.0
4.5
6.0
set-up time
CP1 to CP0;
CP0 to CP1
50
10
9
−8
−3
−2
65
13
11
75
15
13
2.0
4.5
6.0
hold time
CP0 to CP1;
CP1 to CP0
50
10
9
17
6
5
65
13
11
75
15
13
2.0
4.5
6.0
fmax
maximum clock
pulse frequency
6.0
30
25
23
70
83
4.8
24
28
4.0
20
24
2.0
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
CP1
CP0
MR
0.40
0.25
0.50
December 1990
8
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to+85
−40 to+125
min. typ. max. min.
max.
min.
max.
tPHL/ tPLH
propagation delay
CP0 to Qn
25
25
25
25
22
20
7
46
46
50
50
46
46
15
58
69
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.9
Fig.9
Fig.9
Fig.9
Fig.8
Fig.8
Fig.9
Fig.8
Fig.8
Fig.8
Fig.7
t
t
PHL/ tPLH
PHL/ tPLH
propagation delay
CP0 to Q5-9
58
63
63
58
58
19
69
75
75
69
69
22
propagation delay
CP1 to Qn
tPHL/ tPLH
tPHL
propagation delay
CP1 to Q5-9
propagation delay
MR to Q1−9
tPLH
propagation delay
MR to Q5−9, Q0
t
THL/ tTLH
output transition time
tW
clock pulse width
HIGH or LOW
16
16
5
7
20
20
5
24
tW
master reset pulse
width; HIGH
4
24
5
trem
tsu
removal time
MR to CP0, CP1
−5
−3
set-up time
CP1 to CP0;
CP0 to CP1
10
13
15
th
hold time
CP0 to CP1;
CP1 to CP0
10
6
13
24
15
20
ns
ns
4.5
4.5
Fig.7
Fig.8
fmax
maximum clock pulse 30
frequency
61
December 1990
9
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the hold and set-up times for CP0 to CP1 and CP1 to CP0.
Conditions:
CP1 = LOW while CP0 is triggered on a LOW-to-HIGH
transition and CP0 = HIGH, while CP1 is triggered on a
HIGH-to-LOW transition.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the minimum pulse widths for CP0, CP1 and MR inputs; the recovery time for MR and
the propagation delays for MR to Qn and Q5-9 outputs.
December 1990
10
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Conditions:
CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition
and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW
transition.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition times.
December 1990
11
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
APPLICATION INFORMATION
Some applications for the “4017” are:
• Decade counter with decimal decoding
• 1 out of n decoding counter (when cascaded)
• Sequential controller
• Timer
Figure 10 shows a technique for extending the number of decoded output states for the “4017”. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
It is essential not to enable the counter on CP1
when CP0 is HIGH, or on CP0 when CP1 is LOW,
as this would cause an extra count.
Fig.10 Counter expansion
Figure 11 shows an example of a divide-by 2 through divide-by 10 circuit using one “4017”. Since “4017” has an
asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths
can be enlarged by inserting a RC network at the MR input.
Fig.11 Divide-by 2 through divide-by 10.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
12
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