74HC7597NB [NXP]
IC HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, Shift Register;
| 型号： | 74HC7597NB |
| 厂家： | 
NXP |
| 描述： | IC HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, Shift Register 移位寄存器 锁存器 |
| 文件： | 总12页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7597
8-bit shift register with input latches
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
The 74HC/HCT7597 both consist of an 8-bit storage latch
feeding a parallel-in, serial-out 8-bit shift register.
FEATURES
• 8-bit parallel input latches
When LE is LOW, data at the Dn inputs enter the latches.
In this condition the latches are transparent, i.e. a latch
output will change state each time its corresponding
D-input changes.
• Shift register has direct overriding load and clear
• Output capability: standard
• ICC category: MSI
When LE is HIGH the latches store the information that
was present at the D-inputs, a set-up time preceding the
LOW-to-HIGH transition of LE.
GENERAL DESCRIPTION
The 74HC/HCT7597 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The shift register has a positive edge-triggered clock,
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
SHCP to Q
CL = 15 pF; VCC = 5 V
15
17
ns
LE to Q
22
20
20
99
3.5
29
27
23
24
79
3.5
30
ns
PL to Q
ns
D7 to Q
ns
fmax
CI
maximum clock frequency SHCP
input capacitance
MHz
pF
pF
CPD
power dissipation capacitance per package notes 1, 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
ground (0 V)
8
GND
Q
9
serial data output
10
MR
asynchronous reset input (active LOW)
11
SHCP
LE
shift clock input (LOW-to-HIGH, edge-triggered)
latch enable input (active LOW)
parallel load input (active LOW)
serial data input
12
13
PL
14
DS
15, 1, 2, 3, 4, 5, 6, 7
16
D0 to D7
VCC
parallel data inputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
FUNCTION TABLE
LE
L
SHCP PL MR
FUNCTION
X
X
X
X
X
↑
X
X
L
X
X
H
L
data enabled to input latches (transparent)
data stored into latches (non-transparent)
data transferred from input latches to shift register
H
X
X
L
invalid logic, state of shift register indeterminate when signals removed
shift register cleared
X
H
H
L
X
H
shift register clocked Qn = Qn-1, Q0 = DS
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
Fig.4 Functional diagram.
December 1990
4
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
Fig.6 Timing diagram.
December 1990
6
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
SHCP to Q
50
18
14
175
35
30
220
44
37
265
53
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
tPHL
propagation delay
MR to Q
52
19
15
175
35
30
220
44
37
265
53
45
2.0 Fig.7
4.5
6.0
t
t
t
PHL/ tPLH propagation delay
72
26
21
250
50
43
315
63
54
375
75
64
2.0 Fig.7
4.5
6.0
LE to Q
PHL/ tPLH propagation delay
PL to Q
63
23
18
190
38
32
240
48
41
285
57
48
2.0 Fig.7
4.5
6.0
PHL/ tPLH propagation delay
D7 to Q
63
23
18
190
38
32
240
48
41
285
57
48
2.0 Fig.7
4.5
6.0
tTHL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
2.0 Fig.7
4.5
6.0
tW
SHCP pulse width
HIGH or LOW
80
16
14
11
4
3
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
tW
LE pulse width
LOW
80
16
14
11
4
3
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
tW
MR pulse width
LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
tW
PL pulse width
LOW
80
16
14
17
6
5
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
trem
removal time
MR to SHCP
50
10
9
−3
−1
−1
65
13
11
75
15
13
2.0 Fig.7
4.5
6.0
December 1990
7
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
trem
tsu
tsu
tsu
th
removal time
MR to PL
100 22
125
25
21
150
30
26
ns
ns
ns
ns
ns
ns
ns
2.0 Fig.7
4.5
6.0
20
17
8
6
set-up time
Dn to LE
80
16
14
6
2
2
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
set-up time
DS to SHCP
80
16
14
11
4
3
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
set-up time
PL to SHCP
80
16
14
8
3
2
100
20
17
120
24
20
2.0 Fig.7
4.5
6.0
hold time
Dn to LE
4
4
4
−3
−1
−1
4
4
4
4
4
4
2.0 Fig.7
4.5
6.0
th
hold time
DS to SHCP
2
2
2
−8
−3
−2
2
2
2
2
2
2
2.0 Fig.7
4.5
6.0
th
hold time
PL to SHCP
2
2
2
−8
−3
−2
2
2
2
2
2
2
2.0 Fig.7
4.5
6.0
fmax
maximum pulse frequency 6.0 30
4.8
24
28
4.0
20
24
MHz 2.0 Fig.7
SHCP
30
35
90
4.5
6.0
107
December 1990
8
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
DS
Dn
PL, MR
LE, SHCP
0.25
0.40
1.50
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
t
PHL/ tPLH propagation delay
SHCP to Q
20
25
31
27
28
7
35
42
53
46
49
15
44
53
66
58
61
19
53
63
80
69
74
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
tPHL
propagation delay
MR to Q
t
PHL/ tPLH propagation delay
LE to Q
tPHL/ tPLH propagation delay
PL to Q
t
PHL/ tPLH propagation delay
D7 to Q
t
THL/ tTLH output transition time
tW
SHCP pulse width
HIGH or LOW
16
16
20
18
10
20
6
20
20
25
23
13
25
24
24
30
27
15
30
tW
LE pulse width
LOW
7
tW
MR pulse width
LOW
11
9
tW
PL pulse width
LOW
trem
trem
removal time
MR to SHCP
−1
9
removal time
MR to PL
December 1990
9
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
T
amb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
(V)
+25
−40 to +85 −40 to +125
WAVEFORMS
min. typ. max. min. max. min. max.
tsu
tsu
tsu
th
set-up time
Dn to LE
16
16
16
4
5
20
20
20
4
24
24
24
4
ns
ns
ns
ns
ns
ns
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
4.5 Fig.7
set-up time
DS to SHCP
5
set-up time
PL to SHCP
3
hold time
Dn to LE
−2
−4
−3
72
th
hold time
DS to SHCP
2
2
2
th
hold time
PL to SHCP
2
2
2
fmax
maximum pulse frequency 30
SHCP
24
20
MHz 4.5 Fig.7
December 1990
10
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the SHCP input to Q
output propagation delays, the SHCP pulse
width and maximum clock pulse frequency.
Fig.8 Waveforms showing the MR input to Q
output propagation delay and the MR pulse
width.
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the PL input to Q
output propagation delays, PL pulse width
and output transition times.
Fig.9 Waveforms showing the LE input to Q
output propagation delays and the LE pulse
width.
December 1990
11
Philips Semiconductors
Product specification
8-bit shift register with input latches
74HC/HCT7597
(1) HC : VM = 50%; VI = GND to VCC
.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the D7 input to Q
output propagation delays and output
transition times.
Fig.12 Waveforms showing the MR input to PL,
SHCP removal times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing set-up and hold times
for PL input to SHCP input.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing hold and set-up times
for DS, Dn inputs to SHCP, LE inputs.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
12
相关型号：
74HC7597PW-T
IC HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, Shift Register
NXP
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