74HCT138N [NXP]
3-to-8 line decoder/demultiplexer; inverting; 3至8线译码器/多路分解器;反相
| 型号： | 74HCT138N |
| 厂家： | 
NXP |
| 描述： | 3-to-8 line decoder/demultiplexer; inverting |
| 文件： | 总7页 (文件大小：54K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT138
3-to-8 line decoder/demultiplexer;
inverting
September 1993
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74HC/HCT138
The 74HC/HCT138 decoders accept three binary
FEATURES
weighted address inputs (A0, A1, A2) and when enabled,
provide 8 mutually exclusive active LOW outputs (Y0 to
Y7).
• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Active LOW mutually exclusive outputs
• Output capability: standard
• ICC category: MSI
The “138” features three enable inputs: two active LOW
(E1 and E2) and one active HIGH (E3). Every output will be
HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel
expansion of the “138” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “138” ICs and one inverter.
The ”138” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
GENERAL DESCRIPTION
The 74HC/HCT138 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The ”138” is identical to the “238” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
CL = 15 pF; VCC = 5 V
t
PHL/ tPLH
An to Yn
12
14
17
19
ns
ns
tPHL/ tPLH
E3 to Yn
En to Yn
CI
input capacitance
3.5
67
3.5
67
pF
pF
CPD
power dissipation capacitance per package notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74HC/HCT138
PIN DESCRIPTION
PIN NO.
SYMBOL
A0 to A2
E1, E2
E3
NAME AND FUNCTION
1, 2, 3
address inputs
4, 5
enable inputs (active LOW)
enable input (active HIGH)
ground (0 V)
6
8
GND
15, 14, 13, 12, 11, 10, 9, 7
16
Y0 to Y7
VCC
outputs (active LOW)
positive supply voltage
handbook, halfpage
1
A
Y
Y
Y
Y
Y
Y
Y
Y
15
14
13
12
11
10
9
0
1
2
0
1
2
3
4
5
6
7
2
3
A
A
E
E
E
1
2
3
4
5
6
7
MLB312
Fig.1 Pin configuration.
Fig.2 Logic symbol.
(a)
(b)
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74HC/HCT138
FUNCTION TABLE
INPUTS
OUTPUTS
E1
E2
E3
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Fig.5 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74HC/HCT138
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
41
15
12
150
30
26
190
38
33
225
45
38
2.0
4.5
6.0
propagation delay
An to Yn
tPHL/ tPLH
ns
Fig.6
47
17
14
150
30
26
190
38
33
225
45
38
2.0
4.5
6.0
propagation delay
E3 to Yn
t
t
t
PHL/ tPLH
PHL/ tPLH
THL/ tTLH
ns
ns
ns
Fig.6
47
17
14
150
30
26
190
38
33
225
45
38
2.0
4.5
6.0
propagation delay
En to Yn
Fig.7
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
output transition
time
Figs 6 and 7
September 1993
5
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74HC/HCT138
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To
determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
An
En
E3
1.50
1.25
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
propagation delay
An to Yn
tPHL/ tPLH
20
18
19
7
35
40
40
15
44
50
50
19
53
60
60
22
ns
4.5
4.5
4.5
4.5
Fig.6
propagation delay
E3 to Yn
t
t
PHL/ tPLH
PHL/ tPLH
ns
ns
ns
Fig.6
propagation delay
En to Yn
Fig.7
output transition
time
tTHL/ tTLH
Figs 6 and 7
September 1993
6
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74HC/HCT138
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and
the output transition times.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition
times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
September 1993
7
相关型号：
74HCT138PW-T
IC HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16, Decoder/Driver
NXP
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