74HCT74 [NXP]
Dual D-type flip-flop with set and reset; positive-edge trigger; 双D- FL型IP- FL运算与置位和复位;正边沿触发
| 型号： | 74HCT74 |
| 厂家： | 
NXP |
| 描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 文件： | 总22页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HC74; 74HCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
2003 Jul 10
Supersedes data of 1998 Feb 23
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
FEATURES
GENERAL DESCRIPTION
• Wide supply voltage range from 2.0 to 6.0 V
• Symmetrical output impedance
• High noise immunity
The 74HC/HCT74 is a high-speed Si-gate CMOS device
and is pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
• Low power dissipation
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (SD) and reset (RD) inputs; also complementary
Q and Q outputs.
• Balanced propagation delays
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/tPLH
CL = 15 pF; VCC = 5 V
nCP to nQ, nQ
14
15
16
76
15
ns
nSD to nQ, nQ
18
18
59
3.5
29
ns
nRD to nQ, nQ
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
3.5
24
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. For 74HC74 the condition is VI = GND to VCC
.
For 74HCT74 the condition is VI = GND to VCC − 1.5 V.
2003 Jul 10
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
FUNCTION TABLES
Table 1 See note 1
INPUT
OUTPUT
SD
RD
CP
D
Q
Q
L
H
L
H
L
L
X
X
X
X
X
X
H
L
L
H
H
H
Table 2 See note 1
INPUT
OUTPUT
SD
RD
CP
D
Qn+1
Qn+1
H
H
H
H
↑
↑
L
L
H
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
MATERIAL
CODE
RANGE
74HC74N
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
14
14
14
14
14
14
14
14
14
14
DIP14
DIP14
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
SOT27-1
SOT27-1
74HCT74N
74HC74D
SO14
SOT108-1
SOT108-1
SOT337-1
SOT337-1
SOT402-1
SOT402-1
SOT762-1
SOT762-1
74HCT74D
74HC74DB
74HCT74DB
74HC74PW
74HCT74PW
74HC74BQ
74HCT74BQ
SO14
SSOP14
SSOP14
TSSOP14
TSSOP14
DHVQFN14
DHVQFN14
2003 Jul 10
3
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
PINNING
PIN
SYMBOL
1RD
DESCRIPTION
asynchronous reset-direct input (active LOW)
1
2
1D
data input
3
1CP
1SD
1Q
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop output
4
5
6
1Q
complement flip-flop output
ground (0 V)
7
GND
2Q
8
complement flip-flop output
true flip-flop output
9
2Q
10
11
12
13
14
2SD
2CP
2D
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
2RD
VCC
asynchronous reset-direct input (active LOW)
positive supply voltage
V
1RD
1
handbook, halfpage
CC
14
handbook, halfpage
1RD
1
2
3
4
5
6
7
14
13
12
11
V
CC
1D
2
3
13 2RD
12 2D
1D
1CP
1SD
1Q
2RD
2D
1CP
(1)
2CP
74
1SD
1Q
4
5
6
11 2CP
10 2SD
GND
10 2SD
1Q
9
8
2Q
2Q
1Q
9
2Q
GND
7
8
MNA417
GND 2Q
Top view
MNB038
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration DIP14, SO14 and
(T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
2003 Jul 10
4
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
4
3
2
1
handbook, halfpage
4 10
handbook, halfpage
S
5
6
1SD 2SD
C1
SD
1D
R
1Q
2Q
5
9
2
12
3
1D
2D
1CP
2CP
D
Q
Q
CP
11
10
11
12
13
FF
S
1Q
2Q
6
8
9
C1
RD
1D
R
8
1RD 2RD
1 13
MNA418
MNA419
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
handbook, halfpage
1SD
4
SD
1Q
1Q
1D
2
3
Q
Q
D
5
6
1CP
CP
FF
RD
1RD
2SD
1
10
SD
2Q
2Q
2D
9
8
12
11
D
Q
Q
2CP
CP
FF
RD
2RD
MNA420
13
Fig.5 Functional diagram.
2003 Jul 10
5
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
Q
C
C
C
C
C
C
C
D
Q
C
RD
SD
MNA421
CP
C
C
Fig.6 Logic diagram (one flip-flop).
2003 Jul 10
6
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
RECOMMENDED OPERATING CONDITIONS
74HC74
74HCT74
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN.
2.0
TYP.
5.0
−
MAX.
6.0
MIN.
4.5
TYP.
MAX.
VCC
VI
supply voltage
input voltage
output voltage
5.0
5.5
V
0
VCC
0
−
VCC
V
VO
0
−
VCC
0
−
VCC
V
Tamb
operating ambient
temperature
−40
+25
+125
−40
+25
+125
°C
tr, tf
input rise and fall
times
VCC = 2.0 V
−
−
−
−
1000
500
−
−
−
−
500
500
500
ns
ns
ns
VCC = 4.5 V
CC = 6.0 V
6.0
−
6.0
−
V
400
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+7.0
UNIT
VCC
IIK
V
input diode current
VI < −0.5 V or VI > VCC + 0.5 V;
−
±20
mA
note 1
IOK
output diode current
VO < −0.5 V or VO > VCC + 0.5 V;
−
±20
mA
note 1
IO
CC, IGND
output source or sink current
VCC or GND current
storage temperature
power dissipation
−0.5 V < VO < VCC + 0.5 V; note 1 −
±25
mA
mA
°C
I
−
±100
+150
500
Tstg
Ptot
−65
Tamb = −40 to +125 °C; note 2
−
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
For DIP14 packages: above 70 °C derate linearly with 12 mW/K.
2003 Jul 10
7
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
DC CHARACTERISTICS
Family 74HC
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C; note 1
VIH
HIGH-level input
voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.5
1.2
−
−
−
V
V
V
V
V
V
3.15
4.2
−
2.4
3.2
0.8
2.1
2.8
VIL
LOW-level input voltage
0.5
−
1.35
1.8
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −4.0 mA
IO = −5.2 mA
VI = VIH or VIL
IO = 4.0 mA
4.5
6.0
3.84
5.34
4.32
5.81
−
−
V
V
VOL
LOW-level output
voltage
4.5
6.0
6.0
6.0
−
−
−
−
0.15
0.16
−
0.33
0.33
±1.0
40
V
V
IO = 5.2 mA
ILI
input leakage current
VI = VCC or GND
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
−
Tamb = −40 to +125 °C
VIH HIGH-level input
2.0
4.5
6.0
2.0
4.5
6.0
1.5
3.15
4.2
−
−
−
−
−
−
−
−
V
V
V
V
V
V
voltage
−
−
VIL
LOW-level input voltage
0.5
1.35
1.8
−
−
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = −4.0 mA
IO = −5.2 mA
VI = VIH or VIL
IO = 4.0 mA
4.5
6.0
3.7
5.2
−
−
−
−
V
V
VOL
LOW-level output
voltage
4.5
6.0
6.0
6.0
−
−
−
−
−
−
−
−
0.4
0.4
±1.0
80
V
IO = 5.2 mA
V
ILI
input leakage current
VI = VCC or GND
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
Note
1. All typical values are measured at Tamb = 25 °C.
2003 Jul 10
8
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
Family 74HCT
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C; note 1
VIH
HIGH-level input
voltage
4.5 to 5.5 2.0
1.6
−
V
VIL
LOW-level input voltage
4.5 to 5.5
4.5
−
1.2
0.8
V
V
VOH
HIGH-level output
voltage
VI = VIH or VIL;
IO = −4.0 mA
3.84
4.32
−
VOL
LOW-level output
voltage
VI = VIH or VIL;
IO = 4.0 mA
4.5
0.33
0.15
−
V
ILI
input leakage current
VI = VCC or GND
5.5
5.5
−
−
−
−
±1.0
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
40
∆ICC
additional quiescent
VI = VCC −2.1 V other
4.5 to 5.5
−
100
450
µA
supply current per input inputs at VCC or GND;
IO = 0
Tamb = −40 to +125 °C
VIH
HIGH-level input
4.5 to 5.5 2.0
−
−
V
voltage
VIL
LOW-level input voltage
4.5 to 5.5
4.5
−
−
−
0.8
V
V
VOH
HIGH-level output
voltage
VI = VIH or VIL;
IO = −4.0 mA
3.7
−
VOL
LOW-level output
voltage
VI = VIH or VIL;
IO = 4.0 mA
4.5
−
−
0.4
V
ILI
input leakage current
VI = VCC or GND
5.5
5.5
−
−
−
−
±1.0
µA
µA
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
80
∆ICC
additional quiescent
VI = VCC −2.1 V other
4.5 to 5.5
−
−
490
µA
supply current per input inputs at VCC or GND;
IO = 0
Note
1. All typical values are measured at Tamb = 25 °C.
Remark to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input,
multiply this value by the unit load coefficient shown in the table.
INPUT
UNIT LOAD COEFFICIENT
nD
0.70
0.70
0.80
0.80
nRD
nSD
nCP
2003 Jul 10
9
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
AC CHARACTERISTICS
Family 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay
nCP to nQ, nQ
see Fig.7
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
47
220
ns
17
14
50
18
14
52
19
15
19
7
44
37
250
50
43
250
50
43
95
19
16
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
propagation delay
nSD to nQ, nQ
see Fig.8
see Fig.8
see Fig.7
see Fig.7
propagation delay
nRD to nQ, nQ
tTHL/tTLH
output transition time
6
tW
clock pulse width
HIGH or LOW
100
20
17
100
20
17
40
8
19
7
−
6
−
set or reset pulse width see Fig.8
LOW
19
7
−
−
6
−
trem
removal time set or
reset
see Fig.8
3
−
1
−
7
1
−
tsu
set-up time nD to nCP see Fig.7
75
15
13
3
6
−
2
−
2
−
th
hold time nCP to nD
see Fig.7
see Fig.7
−6
−2
−2
23
69
82
−
3
−
3
−
fmax
maximum clock pulse
frequency
4.8
24
28
−
−
−
2003 Jul 10
10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
TEST CONDITIONS
WAVEFORMS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
CC (V)
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay
see Fig.7
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
265
ns
nCP to nQ, nQ
53
45
300
60
51
300
60
51
110
22
19
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
propagation delay
nSD to nQ, nQ
see Fig.8
see Fig.8
see Fig.7
propagation delay
nRD to nQ, nQ
t
THL/tTLH
output transition time
tW
clock pulse width HIGH see Fig.7
or LOW
120
24
20
120
24
20
45
9
−
−
tW
set or reset pulse width see Fig.8
LOW
−
−
−
trem
tsu
th
removal time set or
reset
see Fig.8
−
−
8
−
set-up time nD to nCP see Fig.7
90
18
15
3
−
−
−
hold time nCP to nD
see Fig.7
see Fig.7
−
3
−
3
−
fmax
maximum clock pulse
frequency
4.0
20
24
−
−
−
2003 Jul 10
11
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
Family 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to +85 °C
tPHL/tPLH
propagation
delay nCP to nQ, nQ
see Fig.7
4.5
4.5
4.5
−
−
−
−
18
44
ns
propagation
delay nSD to nQ, nQ
see Fig.8
see Fig.8
see Fig.7
23
24
50
50
ns
ns
propagation
delay nRD to nQ, nQ
tTHL/tTLH
output transition time
4.5
4.5
7
9
19
ns
ns
tW
clock pulse width HIGH see Fig.7
or LOW
23
20
8
−
set or reset pulse width see Fig.8
LOW
4.5
4.5
9
1
−
−
ns
ns
trem
removal time set or
reset
see Fig.8
tsu
th
set-up time nD to nCP see Fig.7
4.5
4.5
4.5
15
+3
22
5
−
−
−
ns
hold time nCP to nD
see Fig.7
see Fig.7
−3
54
ns
fmax
maximum clock pulse
frequency
MHz
Tamb = −40 to +125 °C
tPHL/tPLH
propagation
delay nCP to nQ, nQ
see Fig.7
see Fig.8
see Fig.8
see Fig.7
4.5
4.5
4.5
−
−
−
−
−
−
53
60
60
ns
ns
ns
propagation
delay nSD to nQ, nQ
propagation
delay nRD to nQ, nQ
tTHL/tTLH
tW
output transition time
4.5
4.5
−
−
−
22
ns
ns
clock pulse width HIGH see Fig.7
or LOW
27
−
set or reset pulse width see Fig.8
LOW
4.5
4.5
24
9
−
−
−
−
ns
ns
trem
removal time set or
reset
see Fig.8
tsu
th
set-up time nD to nCP see Fig.7
4.5
4.5
4.5
18
3
−
−
−
−
−
−
ns
hold time nCP to nD
see Fig.7
see Fig.7
ns
fmax
maximum clock pulse
frequency
18
MHz
2003 Jul 10
12
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
AC WAVEFORMS
V
I
V
nD input
M
GND
t
t
h
h
t
t
su
su
1/f
max
V
I
V
nCP input
M
GND
t
W
t
t
PLH
PHL
V
OH
V
nQ output
nQ output
M
V
OL
V
OH
V
M
V
OL
MNA422
t
t
PHL
PLH
The shaded areas indicate when the input is permitted to change for predictable output performance.
74HC74: VM = 50%; VI = GND to VCC
74HCT74: VM = 1.3 V; VI = GND to 3 V.
.
Fig.7 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,
the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
2003 Jul 10
13
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
V
I
V
nCP input
M
GND
t
rem
V
I
V
nSD input
nRD input
M
GND
t
t
W
W
V
I
V
M
GND
t
t
PHL
PLH
V
OH
nQ output
nQ output
V
V
M
V
OL
V
OH
M
t
V
OL
MNA423
t
PHL
PLH
74HC74: VM = 50%; VI = GND to VCC
.
74HCT74: VM = 1.3 V; VI = GND to 3 V.
Fig.8 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRD, nRD to nCP removal time.
2003 Jul 10
14
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
S1
V
CC
open
GND
V
CC
R
=
L
1 kΩ
V
I
V
O
PULSE
D.U.T.
GENERATOR
C
R
T
L
MNA183
TEST
tPZH
S1
GND
VCC
tPZL
tPHZ
tPLZ
Definitions for test circuit:
RL = Load resistor.
GND
VCC
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.9 Load circuitry for switching times.
2003 Jul 10
15
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
PACKAGE OUTLINES
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
2003 Jul 10
16
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
2003 Jul 10
17
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
2003 Jul 10
18
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
2003 Jul 10
19
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
2003 Jul 10
20
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 10
21
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/03/pp22
Date of release: 2003 Jul 10
Document order number: 9397 750 11259
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