74LV02N [NXP]
Quad 2-input NOR gate; 四路2输入NOR门
| 型号： | 74LV02N |
| 厂家： | 
NXP |
| 描述： | Quad 2-input NOR gate |
| 文件： | 总10页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LV02
Quad 2-input NOR gate
Product specification
1998 Apr 20
Supersedes data of 1997 Feb 03
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
FEATURES
• Wide operating voltage: 1.0 to 5.5 V
• Optimized for low voltage applications: 1.0 to 5.5 V
DESCRIPTION
The 74LV02 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT02.
The 74LV02 provides the 2-input NOR function.
• Accepts TTL input levels between V = 2.7 V and V = 3.6 V
CC
CC
• Typical V
(output ground bounce) < 0.8 V at V = 3.3 V,
OLP
= 25°C
CC
T
amb
• Typical V
(output V undershoot) > 2 V at V = 3.3 V,
OHV
= 25°C
OH
CC
T
amb
• Output capability: standard
• I category: SSI
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; t = t ≤ 2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
nA, nB to nY
C = 15 pF;
L
t
t
6
ns
PHL/ PLH
V
CC
= 3.3 V
C
Input capacitance
3.5
22
pF
pF
I
C
Power dissipation capacitance per gate
See Notes 1 and 2
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C × V
× f )ȍ (C V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacitance in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
ȍ (C V
f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LV02 N
PKG. DWG. #
SOT27-1
14-Pin Plastic DIL
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
74LV02 N
74LV02 D
14-Pin Plastic SO
74LV02 D
SOT108-1
SOT337-1
SOT402-1
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
74LV02 DB
74LV02 PW
74LV02 DB
74LV02PW DH
PIN DESCRIPTION
FUNCTION TABLE
PIN
INPUTS
OUTPUTS
nY
SYMBOL
NUMBER
FUNCTION
nA
nB
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9, 12
1Y – 4Y
1A – 4A
1B – 4B
GND
Data outputs
Data inputs
Data inputs
Ground (0 V)
L
L
L
H
L
H
L
L
H
7
H
H
L
14
V
CC
Positive supply voltage
NOTES:
H = HIGH voltage level
L
= LOW voltage level
2
1998 Apr 20
853–1899 19257
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
2
3
≥1
≥1
≥1
≥1
1Y
1A
1
2
3
4
5
6
7
14
13
12
11
10
9
V
CC
1
4
4Y
4B
4A
3Y
3B
3A
5
6
1B
2Y
8
9
10
2A
11
12
13
2B
SV00391
GND
8
SV00389
LOGIC DIAGRAM (ONE GATE)
LOGIC SYMBOL
A
B
Y
2
3
1A
1B
1Y
2Y
3Y
4Y
1
SV00393
5
6
2A
2B
4
8
9
3A
3B
10
13
11
12
4A
4B
SV00390
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
1.0
0
TYP.
3.3
–
MAX
5.5
UNIT
V
CC
DC supply voltage
See Note 1
V
V
V
V
I
Input voltage
V
CC
CC
V
O
Output voltage
0
–
V
See DC and AC
characteristics
–40
–40
+85
+125
T
Operating ambient temperature range in free air
Input rise and fall times
°C
amb
V
V
V
V
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
= 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50
CC
CC
CC
CC
t , t
r
ns/V
f
NOTE:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.
CC
CC
CC
CC
3
1998 Apr 20
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
–0.5 to +7.0
±I
DC input diode current
DC output diode current
V < –0.5 or V > V + 0.5V
20
50
mA
mA
IK
I
I
CC
±I
OK
V
O
< –0.5 or V > V + 0.5V
O
CC
DC output source or sink current
– standard outputs
±I
O
–0.5V < V < V + 0.5V
mA
O
CC
25
±I
±I
,
DC V or GND current for types with
– standard outputs
GND
CC
CC
mA
50
T
stg
Storage temperature range
–65 to +150
°C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
P
TOT
mW
– plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
= 1.2V
UNIT
1
MIN
0.9
1.4
2.0
TYP.
MAX
MIN
0.9
1.4
2.0
MAX
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 2.0V
HIGH level Input
voltage
V
IH
V
= 2.7 to 3.6V
= 4.5 to 5.5V
= 1.2V
0.7*V
0.7*V
CC
CC
0.3
0.6
0.8
0.3
0.6
0.8
= 2.0V
LOW level Input
voltage
V
IL
V
= 2.7 to 3.6V
= 4.5 to 5.5
0.3*V
0.3*V
CC
CC
= 1.2V; V = V or V –I = 100µA
1.2
2.0
2.7
3.0
4.5
I
IH
IL;
O
= 2.0V; V = V or V –I = 100µA
1.8
2.5
2.8
4.3
1.8
2.5
2.8
4.3
I
IH
IL;
O
HIGH level output
voltage; all outputs
= 2.7V; V = V or V –I = 100µA
V
V
V
V
V
I
IH
IL;
O
OH
= 3.0V; V = V or V –I = 100µA
I
IH
IL;
O
= 4.5V; V = V or V –I = 100µA
I
IH
IL;
O
HIGH level output
voltage;
STANDARD
V
V
= 3.0V; V = V or V –I = 6mA
2.40
3.60
2.82
4.20
2.20
3.50
CC
I
IH
IL;
O
OH
= 4.5V; V = V or V –I = 12mA
CC
I
IH
IL;
O
outputs
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V; V = V or V I
IL; O
= 100µA
= 100µA
= 100µA
= 100µA
= 100µA
0
0
0
0
0
I
IH
= 2.0V; V = V or V
I
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
I
IH
IL; O
LOW level output
voltage; all outputs
= 2.7V; V = V or V
I
V
V
I
IH
IL; O
OL
= 3.0V; V = V or V I
IL; O
I
IH
= 4.5V; V = V or V I
IL; O
I
IH
LOW level output
voltage;
STANDARD
V
CC
V
CC
V
CC
= 3.0V; V = V or V I = 6mA
IL; O
0.25
0.35
0.40
0.55
1.0
0.50
0.65
1.0
I
IH
V
OL
= 4.5V; V = V or V I = 12mA
IL; O
I
IH
outputs
Input leakage
current
I
I
= 5.5V; V = V or GND
µA
I
CC
4
1998 Apr 20
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
1
MIN
TYP.
MAX
MIN
MAX
Quiescent supply
current; SSI
I
V
V
= 5.5V; V = V or GND; I = 0
20.0
40
µA
µA
CC
CC
I
CC
O
Additional
quiescent supply
current
∆I
= 2.7V to 3.6V; V = V –0.6V
500
850
CC
CC
I
CC
NOTE:
1. All typical values are measured at T
= 25°C.
amb
AC CHARACTERISTICS
GND = 0V; t = t ≤ 2.5ns; C = 50pF; R = 1KΩ
r
f
L
L
LIMITS
–40 to +85 °C
CONDITION
(V)
–40 to +125 °C
SYMBOL
PARAMETER
WAVEFORM
UNIT
1
V
CC
MIN
TYP.
40
MAX
MIN
MAX
1.2
2.0
2.7
14
21
15
12
10
26
19
15
13
Propagation delay
nA, nB to nY
10
t
/t
Figures 1, 2
ns
PHL PLH
2
3.0 to 3.6
4.5 to 5.5
7.5
6.0
3
NOTES:
1. Unless otherwise stated, all typical values are measured at T
= 25°C
amb
2. Typical values are measured at V = 3.3 V.
CC
3. Typical values are measured at V = 5.0 V.
CC
AC WAVEFORMS
TEST CIRCUIT
V
V
V
= 1.5 V at V ≥ 2.7 V and ≤ 3.6 V;
M
CC
V
cc
= 0.5 × V at V < 2.7 V and ≥ 4.5 V;
and V are the typical output voltage drop that occur with the
M
CC
CC
OL
OH
output load.
V
V
O
l
V
I
PULSE
GENERATOR
D.U.T.
50pF
nA, nB, INPUT
GND
V
R = 1k
L
M
R
T
C
L
t
t
PLH
PHL
Test Circuit for Outputs
V
OH
DEFINITIONS
R
L
C
L
R
T
= Load resistor
nY OUTPUT
V
M
= Load capacitance includes jig and probe capacitiance
= Termination resistance should be equal to Z of pulse generators.
OUT
V
OL
SV00392
TEST
V
V
I
CC
Figure 1. Input (nA, nB) to output (nY) propagation delays.
t
t
< 2.7V
2.7–3.6V
≥ 4.5 V
V
CC
PLH/ PHL
2.7V
V
CC
SV00902
Figure 2. Load circuitry for switching times.
5
1998 Apr 20
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
6
1998 Apr 20
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
7
1998 Apr 20
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
8
1998 Apr 20
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
9
1998 Apr 20
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04402
Document order number:
Philips
Semiconductors
相关型号：
74LV02PW-T
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NOR GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Gate
NXP
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