74LV4052PW,118 [NXP]
74LV4052 - Dual 4-channel analog multiplexer/demultiplexer TSSOP 16-Pin;
| 型号： | 74LV4052PW,118 |
| 厂家： | 
NXP |
| 描述： | 74LV4052 - Dual 4-channel analog multiplexer/demultiplexer TSSOP 16-Pin 光电二极管 |
| 文件： | 总26页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 4 — 1 July 2013
Product data sheet
1. General description
The 74LV4052 is a low-voltage CMOS device and is pin and function compatible with the
74HC/HCT4052.
The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer with a common select
logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common
input/output (nZ). The common channel select logics include two digital select inputs (S0
and S1) and an active LOW enable input (E). With E LOW, one of the four switches is
selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches are in the
high impedance OFF-state, independent of S0 and S1. VCC and GND are the supply
voltage pins for the digital control inputs (S0, S1 and E). The VCC to GND ranges are 1.0 V
to 6.0 V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between VCC as a
positive limit and VEE as a negative limit. VCC - VEE may not exceed 6.0 V. For operation
as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).
2. Features and benefits
Optimized for low-voltage applications: 1.0 V to 6.0 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Low ON resistance:
145 (typical) at VCC VEE = 2.0 V
90 (typical) at VCC VEE = 3.0 V
60 (typical) at VCC VEE = 4.5 V
Logic level translation:
To enable 3 V logic to communicate with 3 V analog signals
Typical ‘break before make’ built in
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV4052N
74LV4052D
40 C to +125 C
40 C to +125 C
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
SOT109-1
plastic small outline package; 16 leads; body
width 3.9 mm
74LV4052DB
74LV4052PW
40 C to +125 C
40 C to +125 C
SSOP16
plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
SOT403-1
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
4. Functional diagram
9
&&
ꢁꢅ
ꢁꢉ
ꢁ=
ꢁꢈ
ꢁ<ꢀ
ꢁꢃ
ꢁ<ꢁ
ꢁꢊ
ꢁ<ꢈ
ꢁꢀ
6ꢀ
ꢁꢁ
ꢁ<ꢉ
/2*,&
/(9(/
&219(56,21
ꢄ
ꢁꢂ2)ꢂꢃ
'(&2'(5
6ꢁ
ꢁ
ꢈ<ꢀ
ꢅ
(
ꢊ
ꢈ<ꢁ
ꢈ
ꢈ<ꢈ
ꢃ
ꢈ<ꢉ
ꢉ
ꢈ=
ꢆ
ꢇ
9
((
*1'
DDDꢀꢁꢁꢂꢃꢄꢅ
Fig 1. Functional diagram
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
2 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
10
9
0
0
3
4 ×
1
13
G4
6
1Z
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
12
14
15
11
1
MDX
10
9
S0
S1
0
1
2
3
1
5
3
2
4
5
12
14
15
2
13
6
E
4
2Z
3
11
001aah824
001aah825
Fig 2. Logic symbol
Fig 3. IEC logic symbol
nYn
V
V
EE
CC
V
CC
V
CC
V
V
EE
CC
V
EE
nZ
from
logic
mnb043
Fig 4. Schematic diagram (one switch)
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
3 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
ꢀꢁ/9ꢁꢂꢃꢄ
ꢁꢅ
ꢁꢊ
ꢁꢃ
ꢁꢉ
ꢁꢈ
ꢁꢁ
ꢁꢀ
ꢄ
ꢁ
ꢈ
ꢉ
ꢃ
ꢊ
ꢅ
ꢇ
ꢆ
ꢈ<ꢀ
ꢈ<ꢈ
ꢈ=
9
&&
ꢁ<ꢈ
ꢁ<ꢁ
ꢁ=
ꢀꢁ/9ꢁꢂꢃꢄ
ꢁ
ꢈ
ꢉ
ꢃ
ꢊ
ꢅ
ꢇ
ꢆ
ꢁꢅ
ꢁꢊ
ꢁꢃ
ꢁꢉ
ꢁꢈ
ꢁꢁ
ꢁꢀ
ꢄ
ꢈ<ꢀ
ꢈ<ꢈ
ꢈ=
9
&&
ꢈ<ꢉ
ꢈ<ꢁ
(
ꢁ<ꢈ
ꢁ<ꢁ
ꢁ=
ꢁ<ꢀ
ꢁ<ꢉ
6ꢀ
ꢈ<ꢉ
ꢈ<ꢁ
(
ꢁ<ꢀ
ꢁ<ꢉ
6ꢀ
9
((
9
((
*1'
6ꢁ
*1'
6ꢁ
DDDꢀꢁꢁꢂꢃꢆꢁ
DDDꢀꢁꢁꢂꢃꢆꢃ
Fig 5. Pin configuration for DIP16 andSO16
Fig 6. Pin configuration for (T)SSOP16
5.2 Pin description
Table 2.
Symbol
2Y0
2Y2
2Z
Pin description
Pin
1
Description
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
enable input (active LOW)
negative supply voltage
ground (0 V)
2
3
2Y3
2Y1
E
4
5
6
VEE
GND
S1
7
8
9
select logic input
S0
10
11
12
13
14
15
16
select logic input
1Y3
1Y0
1Z
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
positive supply voltage
1Y1
1Y2
VCC
74LV4052
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
4 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
6. Functional description
Table 3.
Function table[1]
Input
Channel on
E
L
L
L
L
H
S1
L
S0
L
nY0 and nZ
nY1 and nZ
nY2 and nZ
nY3 and nZ
none
L
H
L
H
H
X
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7.0
20
20
25
Unit
V
[1]
[2]
[2]
[2]
supply voltage
0.5
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
-
-
-
mA
mA
mA
ISK
switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
source or sink current
Tstg
Ptot
storage temperature
total power dissipation
65
+150
C
[3]
Tamb = 40 C to +125 C
DIP16 package
-
-
-
750
500
400
mW
mW
mW
SO16 package
SSOP16 and TSSOP16 package
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current flows out of terminals nYn. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE
.
[2] The minimum input voltage rating may be exceeded if the input current rating is observed.
[3] For DIP16 package: above 70 C the value of Ptot derates linearly with 12 mW/K.
For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
5 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions[1]
Parameter
Conditions
Min
Typ
Max
6
Unit
V
supply voltage
input voltage
see Figure 7
1
3.3
VI
0
-
-
-
-
-
-
VCC
VCC
+125
500
200
100
V
VSW
switch voltage
ambient temperature
0
V
Tamb
in free air
40
C
t/V
input transition rise and fall rate VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
-
-
-
ns/V
ns/V
ns/V
VCC = 2.7 V to 6.0 V
[1] The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V. However, LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
001aak344
8.0
V
CC
- GND
(V)
6.0
4.0
2.0
0
operating area
0
2.0
4.0
6.0
CC
8.0
- V (V)
V
EE
Fig 7. Guaranteed operating area as a function of the supply voltages
74LV4052
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
6 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
-
-
-
0.9
-
-
V
V
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
1.4
VCC = 2.7 V to 3.6 V
VCC = 4.5 V
2.0
-
2.0
-
3.15
-
3.15
-
VCC = 6.0 V
4.20
-
4.20
-
VIL
LOW-level input voltage
input leakage current
VCC = 1.2 V
-
-
-
-
-
0.3
0.6
0.8
1.35
1.80
-
-
-
-
-
0.3
0.6
0.8
1.35
1.80
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V
VCC = 6.0 V
II
VI = VCC or GND
VCC = 3.6 V
-
-
-
-
1.0
2.0
-
-
1.0
2.0
A
A
VCC = 6.0 V
IS(OFF)
IS(ON)
ICC
OFF-state leakage current VI = VIH or VIL; see Figure 8
VCC = 3.6 V
-
-
-
-
1.0
2.0
-
-
1.0
2.0
A
A
VCC = 6.0 V
ON-state leakage current
supply current
VI = VIH or VIL; see Figure 9
VCC = 3.6 V
-
-
-
-
1.0
2.0
-
-
1.0
2.0
A
A
VCC = 6.0 V
VI = VCC or GND; IO = 0 A
VCC = 3.6 V
-
-
-
-
-
-
20
40
-
-
-
40
80
A
A
A
VCC = 6.0 V
ICC
additional supply current
per input; VI = VCC 0.6 V;
500
850
VCC = 2.7 V to 3.6 V
CI
input capacitance
switch capacitance
-
-
-
3.5
5
-
-
-
-
-
-
-
-
-
pF
pF
pF
Csw
independent pins nYn
common pins nZ
12
[1] Typical values are measured at Tamb = 25 C.
74LV4052
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
7 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9.1 Test circuits
9
9
&&
&&
6ꢀꢋWRꢋ6ꢁ
6ꢀꢋWRꢋ6ꢁ
9
,+
ꢋRUꢋ9
9 ꢋRUꢋ9
,+ ,/
,/
Q<Q
Q<Q
ꢁ
ꢈ
Q<Q
Q<Q
ꢁ
ꢈ
VZLWFK
VZLWFK
Q=
(
Q=
(
,
,
6
6
,
6
*1'ꢋ ꢋ9
*1'ꢋ ꢋ9
((
((
9
&&
*1'
9
,
9
2
9
9
,
2
DDDꢀꢁꢁꢂꢃꢆꢇ
DDDꢀꢁꢁꢂꢃꢆꢈ
VI = VCC or VEE and VO = VEE or VCC
.
VI = VCC or VEE and VO = open circuit.
Fig 8. Test circuit for measuring OFF-state leakage
current
Fig 9. Test circuit for measuring ON-state leakage
current
9.2 ON resistance
Table 7.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 10 and
Figure 11.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak)
VI = 0 V to VCC VEE
[2]
VCC = 1.2 V; ISW = 100 A
VCC = 2.0 V; ISW = 1000 A
VCC = 2.7 V; ISW = 1000 A
-
-
-
-
-
-
-
-
-
-
-
145
90
325
200
180
375
235
210
VCC = 3.0 V to 3.6 V;
80
ISW = 1000 A
V
CC = 4.5 V; ISW = 1000 A
-
-
60
55
135
125
-
-
160
145
VCC = 6.0 V; ISW = 1000 A
RON
ON resistance mismatch VI = 0 V to VCC VEE
between channels
[2]
VCC = 1.2 V; ISW = 100 A
VCC = 2.0 V; ISW = 1000 A
VCC = 2.7 V; ISW = 1000 A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
4
4
VCC = 3.0 V to 3.6 V;
ISW = 1000 A
VCC = 4.5 V; ISW = 1000 A
VCC = 6.0 V; ISW = 1000 A
-
-
3
2
-
-
-
-
-
-
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
8 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
Table 7.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 10 and
Figure 11.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min Typ[1] Max
Min
Max
RON(rail) ON resistance (rail)
VI = GND
[2]
VCC = 1.2 V; ISW = 100 A
VCC = 2.0 V; ISW = 1000 A
VCC = 2.7 V; ISW = 1000 A
VCC = 3.0 V to 3.6 V;
-
-
-
-
225
110
70
-
-
-
-
-
-
235
145
130
270
165
150
60
I
SW = 1000 A
VCC = 4.5 V; ISW = 1000 A
VCC = 6.0 V; ISW = 1000 A
VI = VCC VEE
-
-
45
40
100
85
-
-
115
100
RON(rail) ON resistance (rail)
[2]
VCC = 1.2 V; ISW = 100 A
VCC = 2.0 V; ISW = 1000 A
VCC = 2.7 V; ISW = 1000 A
-
-
-
-
250
120
75
-
-
-
-
-
-
320
195
175
370
225
205
VCC = 3.0 V to 3.6 V;
70
ISW = 1000 A
V
CC = 4.5 V; ISW = 1000 A
-
-
50
45
130
120
-
-
150
135
VCC = 6.0 V; ISW = 1000 A
[1] Typical values are measured at Tamb = 25 C.
[2] When supply voltages (VCC VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
1.2 V, only use these devices for transmitting digital signals.
74LV4052
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
9 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9.3 On resistance waveform and test circuit
9
9
6:
9
&&
6ꢀꢋWRꢋ6ꢁ
9 ꢋRUꢋ9
,+ ,/
Q<Q
Q<Q
ꢁ
ꢈ
VZLWFK
Q=
(
*1'ꢋ ꢋ9
((
9
,
*1'
,
6:
DDDꢀꢁꢁꢂꢃꢆꢉ
RON = VSW / ISW
.
Fig 10. Test circuit for measuring RON
001aak412
180
R
ON
V
CC
= 2.0 V
(Ω)
120
V
= 3.0 V
CC
V
= 4.5 V
CC
60
0
0
1.2
2.4
3.6
4.8
V (V)
I
Vi = 0 V to VCC VEE
Fig 11. Typical RON as a function of input voltage
74LV4052
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
10 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 14.
Symbol Parameter Conditions 40 C to +85 C
Min
Typ[1] Max
40 C to +125 C Unit
Min
Max
[2]
tpd
propagation delay nYn to nZ, nZ to nYn; see Figure 12
VCC = 1.2 V
-
-
-
-
-
-
25
9
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
17
13
10
9
20
15
12
10
8
VCC = 2.7 V
6
[3]
[2]
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
5
4
VCC = 6.0 V
3
7
ten
enable time
E, Sn to nYn, nZ; see Figure 13
VCC = 1.2 V
-
-
-
-
-
-
-
190
65
48
30
36
32
25
-
121
89
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
146
108
-
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
71
60
46
86
73
56
VCC = 6.0 V
[2]
tdis
disable time
E, Sn to nYn, nZ; see Figure 13
VCC = 1.2 V
-
-
-
-
-
-
-
-
125
43
33
22
26
23
18
57
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
pF
VCC = 2.0 V
80
59
-
95
71
-
VCC = 2.7 V
[3]
[3]
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V
48
41
32
-
57
49
38
-
VCC = 6.0 V
[4]
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
[1] All typical values are measured at Tamb = 25 C.
[2]
tpd is the same as tPLH and tPHL
.
ten is the same as tPZL and tPZH
.
tdis is the same as tPLZ and tPHZ
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + ((CL Csw VCC2 fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
Csw = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs.
74LV4052
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
11 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
10.1 Waveforms
V
CC
nYn or nZ
input
V
M
V
V
EE
t
t
PLH
PHL
V
O
nZ or nYn
output
V
M
EE
001aak351
Measurement points are given in Table 9.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 12. nYn, nZ to nZ, nYn propagation delays
V
CC
Sn, E input
V
M
V
V
V
SS
t
t
PLZ
PZL
V
O
90 %
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
10 %
EE
t
t
PHZ
PZH
V
O
90 %
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
10 %
switch ON
001aak352
EE
switch ON
switch OFF
Measurement points are given in Table 9.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 13. Enable and disable times
Table 9. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
2.7 V to 3.6 V
> 3.6 V
0.5VCC
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NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
V
EE
001aak353
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 14. Test circuit for measuring switching times
Table 10. Test data
Supply voltage Input
Load
CL
VEXT
VCC
VI
tr, tf
RL
tPHL, tPLH
open
tPZH, tPHZ
VEE
tPZL, tPLZ
2VCC
< 2.7 V
VCC
2.7 V
VCC
6 ns
6 ns
6 ns
50 pF
1 k
2.7 V to 3.6 V
> 3.6 V
15 pF, 50 pF 1 k
50 pF 1 k
open
VEE
2VCC
open
VEE
2VCC
74LV4052
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74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
10.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf 6.0 ns; Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic
distortion
fi = 1 kHz; CL = 50 pF; RL = 10 k; see Figure 19
VCC = 3.0 V; VI = 2.75 V (p-p)
VCC = 6.0 V; VI = 5.5 V (p-p)
fi = 10 kHz; CL = 50 pF; RL = 10 k; see Figure 19
VCC = 3.0 V; VI = 2.75 V (p-p)
VCC = 6.0 V; VI = 5.5 V (p-p)
CL = 50 pF; RL = 50 ; see Figure 15
VCC = 3.0 V
-
-
0.8
-
-
%
%
0.4
-
-
2.4
1.2
-
-
%
%
[1]
[2]
f(3dB)
3 dB frequency
response
-
-
180
200
-
-
MHz
MHz
VCC = 6.0 V
iso
isolation (OFF-state)
crosstalk voltage
fi = 1 MHz; CL = 50 pF; RL = 600 ; see Figure 17
VCC = 3.0 V
-
-
50
50
-
-
dB
dB
VCC = 6.0 V
Vct
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 600 ; see Figure 20
VCC = 3.0 V
VCC = 6.0 V
-
-
0.11
0.12
-
-
V
V
[2]
Xtalk
crosstalk
between switches; fi = 1 MHz; CL = 50 pF;
RL = 600 ; see Figure 21
VCC = 3.0 V
VCC = 6.0 V
-
-
60
60
-
-
dB
dB
[1] To obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 50 ), adjust fi voltage.
[2] To obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 600 ), adjust fi voltage.
10.2.1 Test circuits
9
9
&&
&&
ꢈ5
/
6ꢀꢋWRꢋ6ꢁ
9 ꢋRUꢋ9
,+ ,/
Q<Q
Q<Q
ꢁ
ꢈ
VZLWFK
Q=
(
ꢀꢌꢁꢋ)
*1'ꢋ ꢋ9
((
ꢈ5
/
&
/
G%
*1'
I
L
DDDꢀꢁꢁꢂꢃꢆꢊ
Fig 15. Test circuit for measuring frequency response
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Dual 4-channel analog multiplexer/demultiplexer
001aak361
5
(dB)
0
−5
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
VCC = 3.0 V; GND = 0 V; VEE = - 3.0 V; RL = 50 ; RSOURCE = 1 k.
Fig 16. Typical frequency response
9
&&
9
&&
ꢈ5
/
/
6ꢀꢋWRꢋ6ꢁ
9
,+
ꢋRUꢋ9
,/
Q<Q
Q<Q
ꢁ
ꢈ
VZLWFK
Q=
(
ꢀꢌꢁꢋ)
*1'ꢋ ꢋ9
((
ꢈ5
&
/
G%
9
&&
I
L
DDDꢀꢁꢁꢂꢃꢆꢄ
Fig 17. Test circuit for measuring isolation (OFF-state)
74LV4052
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74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
001aak360
0
(dB)
−50
−100
2
3
4
5
6
10
10
10
10
10
10
f (kHz)
VCC = 3.0 V; GND = 0 V; VEE = - 3.0 V; RL = 50 ; RSOURCE = 1 k.
Fig 18. Typical isolation (OFF-state) as function of frequency
9
&&
9
&&
ꢈ5
/
/
6ꢀꢋWRꢋ6ꢁ
9
,+
ꢋRUꢋ9
,/
Q<Q
Q<Q
ꢁ
ꢈ
VZLWFK
Q=
(
ꢁꢀꢋ)
*1'ꢋ ꢋ9
((
ꢈ5
&
/
'
*1'
I
L
DDDꢀꢁꢁꢂꢃꢆꢆ
Fig 19. Test circuit for measuring total harmonic distortion
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74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9
9
9
&&
&&
&&
ꢈ5
/
ꢈ5
/
6ꢀꢋWRꢋ6ꢁ
Q<Q
Q<Q
ꢁ
ꢈ
VZLWFK
Q=
(
*1'ꢋ ꢋ9
((
ꢈ5
/
&
/
9
2
9
*
ꢈ5
/
9
ꢋRUꢋ9
,+ ,/
DDDꢀꢁꢁꢂꢃꢆꢂ
a. Test circuit
logic
input (Sn, E)
off
on
off
V
V
ct
O
001aaj908
b. Input and output pulse definitions
VI may be connected to Sn or E.
Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch
74LV4052
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Product data sheet
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74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
9
&&
9
9
&&
ꢈ5
&&
ꢈ5
/
/
6ꢀꢋWRꢋ6ꢁ
9 ꢋRUꢋ9
,+ ,/
Q<Q
Q<Q
5
/
Q=
(
ꢀꢌꢁꢋ)
*1'ꢋ ꢋ9
((
ꢈ5
/
9
2
&
/
ꢈ5
/
G%
*1'
9
,
DDDꢀꢁꢁꢂꢃꢆꢅ
a. Switch on channel.
9
9
9
9
&&
&&
&&
&&
ꢈ5
ꢈ5
ꢈ5
/
/
/
6ꢀꢋWRꢋ6ꢁ
9 ꢋRUꢋ9
,+
,/
Q<Q
Q<Q
Q=
(
*1'ꢋ ꢋ9
((
5
/
9
,
ꢈ5
/
*1'
ꢈ5
/
&
/
9
G%
2
DDDꢀꢁꢁꢂꢃꢂꢁ
b. Switch off channel.
Fig 21. Test circuit for measuring crosstalk between switches
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Product data sheet
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74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
11. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 22. Package outline SOT38-4 (DIP16)
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74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 23. Package outline SOT109-1 (SO16)
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Dual 4-channel analog multiplexer/demultiplexer
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 24. Package outline SOT338-1 (SSOP16)
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Dual 4-channel analog multiplexer/demultiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 25. Package outline SOT403-1 (TSSOP16)
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Dual 4-channel analog multiplexer/demultiplexer
12. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 13. Revision history
Document ID
74LV4052 v.4
Modifications:
Release date
20130701
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV4052 v.3
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74LV4052 v.3
74LV4052 v.2
19980623
Product specification
-
74LV4052 v.2
19970715
Product specification
-
-
74LV4052
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14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
14.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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74LV4052
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Dual 4-channel analog multiplexer/demultiplexer
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
25 of 26
74LV4052
NXP Semiconductors
Dual 4-channel analog multiplexer/demultiplexer
16. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
7
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 8
On resistance waveform and test circuit. . . . . 10
9.1
9.2
9.3
10
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Additional dynamic parameters . . . . . . . . . . . 14
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10.1
10.2
10.2.1
11
12
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 July 2013
Document identifier: 74LV4052
相关型号：
74LV4052PWDH-T
IC DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, PLASTIC, TSSOP-16, Multiplexer or Switch
NXP
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