74LV4053A [TI]
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS; 三重2通道模拟多路复用器/多路解复用器
| 型号： | 74LV4053A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS |
| 文件： | 总22页 (文件大小：821K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢂ ꢇ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢃꢆ ꢂꢇ ꢈ
ꢋꢌ ꢍ ꢎ ꢄꢏ ꢐꢑꢒ ꢓꢈꢁꢁꢏ ꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢖ ꢗꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍ ꢎꢄ ꢏꢘ ꢏ ꢌꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
SN54LV4053A . . . J OR W PACKAGE
SN74LV4053A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
2-V to 5.5-V V
Operation
CC
Support Mixed-Mode Voltage Operation on
All Ports
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
V
CC
D
D
D
D
D
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
2-COM
1-COM
1Y1
1Y0
A
3-COM
3Y0
INH
GND
GND
Extremely Low Input Current
Latch-Up Performance Exceeds 250 mA Per
JESD 17
B
C
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN74LV4053A . . . RGY PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
1
16
These
multiplexers/demultiplexers are designed for 2-V
to 5.5-V V operation.
triple
2-channel
CMOS
analog
2Y0
3Y1
15 2-COM
2
3
4
5
6
7
14
13
12
11
10
1-COM
1Y1
1Y0
A
CC
3-COM
3Y0
The ’LV4053A devices handle both analog and
digital signals. Each channel permits signals with
amplitudes up to 5.5 V (peak) to be transmitted in
either direction.
INH
GND
B
8
9
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing
for
analog-to-digital
and
digital-to-analog conversion systems.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
SN74LV4053AN
SN74LV4053AN
LW053A
QFN − RGY
Reel of 1000
Tube of 40
SN74LV4053ARGYR
SN74LV4053AD
SOIC − D
LV4053A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV4053ADR
SN74LV4053ANSR
SN74LV4053ADBR
SN74LV4053APW
SN74LV4053APWR
SN74LV4053APWT
SN74LV4053ADGVR
SNJ54LV4053AJ
SOP − NS
74LV4053A
LW053A
−40°C to 85°C
SSOP − DB
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LW053A
TVSOP − DGV
CDIP − J
LW053A
SNJ54LV4053AJ
SNJ54LV4053AW
−55°C to 125°C
CFP − W
Tube of 150
SNJ54LV4053AW
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢗ ꢁ ꢄꢏꢀꢀ ꢔ ꢋꢓ ꢏꢌꢛ ꢍꢀ ꢏ ꢁ ꢔꢋꢏꢚ ꢜꢝ ꢞꢟ ꢠꢡꢢ ꢣꢤꢥ ꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢎꢌ ꢔ ꢚ ꢗ ꢒꢋ ꢍꢔ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢂꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢂ ꢇ ꢈ
ꢋ ꢌꢍ ꢎ ꢄ ꢏ ꢐ ꢑꢒ ꢓꢈ ꢁ ꢁꢏ ꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢖꢗ ꢄꢋꢍ ꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
FUNCTION TABLE
INPUTS
ON CHANNELS
INH
L
C
L
B
L
A
L
1Y0, 2Y0, 3Y0
1Y1, 2Y0, 3Y0
1Y0, 2Y1, 3Y0
1Y1, 2Y1, 3Y0
1Y0, 2Y0, 3Y1
1Y1, 2Y0, 3Y1
1Y0, 2Y1, 3Y1
1Y1, 2Y1, 3Y1
None
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
X
L
L
H
L
L
H
H
X
L
H
X
H
logic diagram (positive logic)
15
14
2-COM
1-COM
11
A
12
13
1Y0
1Y1
2Y0
2Y1
3Y0
10
B
2
1
5
9
C
3
4
3Y1
6
INH
3-COM
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢂ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢂꢇ ꢈ
ꢋꢌ ꢍ ꢎ ꢄꢏ ꢐꢑꢒ ꢓꢈꢁꢁꢏ ꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢖ ꢗꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏ ꢌ ꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Switch I/O voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
IO
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
I/O diode current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IOK IO
Switch through current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
T
IO
CC
CC
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LV4053A
MIN MAX
SN74LV4053A
MIN MAX
UNIT
‡
‡
V
V
Supply voltage
2
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage, control inputs
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
V
V
× 0.3
× 0.3
× 0.3
5.5
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage, control inputs
V
V
Control input voltage
Input/output voltage
0
0
0
0
V
V
I
V
V
CC
IO
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
200
100
20
200
100
20
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
−55
125
−40
85
°C
‡
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢂꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢂ ꢇ ꢈ
ꢋ ꢌꢍ ꢎ ꢄ ꢏ ꢐ ꢑꢒ ꢓꢈ ꢁ ꢁꢏ ꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢖꢗ ꢄꢋꢍ ꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
41
SN54LV4053A SN74LV4053A
TEST
CONDITIONS
PARAMETER
UNIT
V
CC
MIN
MAX
180
150
75
MIN
MAX
225
190
100
600
225
125
40
MIN
MAX
225
190
100
600
225
125
40
2.3 V
3 V
I
= 2 mA,
T
I
INH
On-state
switch resistance
V = V
V
or GND,
CC
30
r
r
Ω
on
= V
IL
4.5 V
2.3 V
3 V
23
(see Figure 1)
139
63
500
180
100
30
I
T
= 2 mA,
V = V
to GND,
to GND,
Peak on-state resistance
Ω
I
CC
on(p)
V
= V
IL
INH
4.5 V
2.3 V
3 V
35
2
Difference in
on-state resistance
between switches
I = 2 mA,
T
I CC
1.6
1.3
20
30
30
V = V
V
∆r
Ω
on
= V
IL
INH
4.5 V
15
20
20
0 to
5.5 V
I
I
Control input current
V = 5.5 V or GND
I
0.1
1
1
µA
V = V
and
= GND, or
I
CC
V
O
Off-state
switch leakage current
V = GND and
I
I
5.5 V
0.1
1
1
µA
µA
S(off)
V
V
= V
= V
,
O
INH
CC
IH
(see Figure 2)
V = V or GND,
I
CC
On-state
switch leakage current
I
I
V
= V
5.5 V
5.5 V
0.1
1
1
S(on)
INH
IH
(see Figure 3)
Supply current
V = V or GND
20
20
µA
CC
I
CC
C
Control input capacitance
2
pF
IC
IS
Common
terminal capacitance
C
8.2
pF
Switch
terminal capacitance
C
C
5.6
0.5
pF
pF
OS
F
Feedthrough capacitance
switching characteristics over recommended operating free-air temperature range,
= 2.5 V 0.2 V (unless otherwise noted)
V
CC
T = 25°C
A
SN54LV4053A SN74LV4053A
FROM
(INPUT)
TO
TEST
PARAMETER
UNIT
ns
(OUTPUT) CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
t
Propagation
delay time
C
= 15 pF
(see Figure 4)
PLH
PHL
L
COM or Yn Yn or COM
2.5
7.6
10
16
16
t
t
Enable
delay time
C
= 15 pF
(see Figure 5)
PZH
PZL
L
INH
INH
COM or Yn
COM or Yn
18
18
12
28
28
23
23
18
35
35
23
23
18
35
35
ns
t
t
Disable
delay time
C
= 15 pF
(see Figure 5)
PHZ
PLZ
L
7.7
ns
t
t
Propagation
delay time
C
= 50 pF
(see Figure 4)
PLH
PHL
L
COM or Yn Yn or COM
4.4
ns
t
t
Enable
delay time
C
= 50 pF
(see Figure 5)
PZH
PZL
L
INH
INH
COM or Yn
COM or Yn
8.8
ns
t
t
Disable
delay time
C
= 50 pF
(see Figure 5)
PHZ
PLZ
L
11.7
ns
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ꢟ
ꢜ
ꢩ
ꢜ
ꢝ
ꢧ
ꢢ
ꢜ
ꢤ
ꢥ
ꢩ
ꢥ
ꢦ
ꢞ
ꢦ
ꢟ
ꢜ
ꢡ
ꢜ
ꢟ
ꢜ
ꢞ
ꢢ
ꢩ
ꢢ
ꢠ
ꢧ
ꢩ
ꢜ
ꢲ
ꢧ
ꢥ
ꢧ
ꢦ
ꢥ
ꢠ
ꢡ
ꢜ
ꢝ
ꢜ
ꢥ
ꢩ
ꢟ
ꢪ
ꢞ
ꢨ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢩ
ꢥ
ꢠ
ꢥ
ꢣ
ꢟ
ꢞ
ꢱ
ꢟ
ꢭ
ꢧ
ꢜ
ꢟ
ꢍ
ꢩ
ꢣ
ꢥ
ꢟ
ꢥ
ꢟ
ꢜ
ꢝ
ꢩ
ꢞ
ꢱ
ꢝ
ꢜ
ꢡ
ꢢ
ꢝ
ꢱ
ꢥ
ꢡ
ꢩ
ꢞ
ꢟ
ꢦ
ꢜ
ꢞ
ꢦ
ꢥ
ꢜ
ꢝ
ꢥ
ꢩ
ꢡ
ꢟ
ꢯ
ꢡ
ꢣ
ꢜ
ꢞ
ꢥ
ꢭ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢂ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢂꢇ ꢈ
ꢋꢌ ꢍ ꢎ ꢄꢏ ꢐꢑꢒ ꢓꢈꢁꢁꢏ ꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢖ ꢗꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏ ꢌ ꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted)
V
CC
T = 25°C
A
SN54LV4053A SN74LV4053A
FROM
(INPUT)
TO
TEST
PARAMETER
UNIT
ns
(OUTPUT) CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
t
Propagation
delay time
C
= 15 pF
(see Figure 4)
PLH
PHL
L
COM or Yn Yn or COM
1.6
5.3
6.1
2.9
6.1
8.9
6
10
10
t
t
Enable
delay time
C
= 15 pF
(see Figure 5)
PZH
PZL
L
INH
INH
COM or Yn
COM or Yn
12
12
9
15
15
12
25
25
15
15
12
25
25
ns
t
t
Disable
delay time
C
= 15 pF
(see Figure 5)
PHZ
PLZ
L
ns
t
t
Propagation
delay time
C
= 50 pF
(see Figure 4)
PLH
PHL
L
COM or Yn Yn or COM
ns
t
t
Enable
delay time
C
= 50 pF
(see Figure 5)
PZH
PZL
L
INH
INH
COM or Yn
COM or Yn
20
20
ns
t
t
Disable
delay time
C
= 50 pF
(see Figure 5)
PHZ
PLZ
L
ns
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted)
V
CC
T = 25°C
A
SN54LV4053A SN74LV4053A
FROM
(INPUT)
TO
TEST
PARAMETER
UNIT
ns
(OUTPUT) CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
t
Propagation
delay time
C
= 15 pF
(see Figure 4)
PLH
PHL
L
COM or Yn Yn or COM
0.9
3.8
4.6
1.8
4.3
6.3
4
7
7
t
t
Enable delay
time
C
= 15 pF
(see Figure 5)
PZH
PZL
L
INH
INH
COM or Yn
COM or Yn
8
8
10
10
8
10
10
8
ns
t
t
Disable
delay time
C
= 15 pF
(see Figure 5)
PHZ
PLZ
L
ns
t
t
Propagation
delay time
C
= 50 pF
(see Figure 4)
PLH
PHL
L
COM or Yn Yn or COM
6
ns
t
t
Enable delay
time
C
= 50 pF
(see Figure 5)
PZH
PZL
L
INH
INH
COM or Yn
COM or Yn
14
14
18
18
18
18
ns
t
t
Disable
delay time
C
= 50 pF
(see Figure 5)
PHZ
PLZ
L
ns
ꢎ
ꢌ
ꢔ
ꢚ
ꢗ
ꢒ
ꢋ
ꢎ
ꢌ
ꢏ
ꢅ
ꢍ
ꢏ
ꢛ
ꢞ
ꢦ
ꢨ
ꢡ
ꢩ
ꢤ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢢ
ꢡ
ꢦ
ꢢ
ꢥ
ꢩ
ꢦ
ꢟ
ꢪ
ꢩ
ꢡ
ꢠ
ꢣ
ꢢ
ꢜ
ꢟ
ꢞ
ꢦ
ꢜ
ꢝ
ꢥ
ꢨ
ꢡ
ꢩ
ꢤ
ꢧ
ꢜ
ꢞ
ꢲ
ꢥ
ꢡ
ꢩ
ꢠ
ꢥ
ꢟ
ꢥ
ꢧ
ꢞ
ꢢ
ꢦ
ꢱ
ꢦ
ꢪ
ꢝ
ꢦ
ꢠ
ꢧ
ꢟ
ꢟ
ꢢ
ꢥ
ꢧ
ꢡ
ꢡ
ꢨ
ꢠ
ꢥ
ꢦ
ꢲ
ꢥ
ꢱ
ꢟ
ꢬ
ꢡ
ꢡ
ꢧ
ꢥ
ꢪ
ꢬ
ꢪ
ꢤ
ꢥ
ꢋ
ꢠ
ꢦ
ꢥ
ꢣ
ꢜ
ꢭ
ꢮ
ꢢ
ꢒ
ꢝ
ꢦ
ꢞ
ꢧ
ꢟ
ꢜ
ꢩ
ꢜ
ꢝ
ꢧ
ꢢ
ꢜ
ꢤ
ꢥ
ꢩ
ꢥ
ꢦ
ꢞ
ꢦ
ꢟ
ꢜ
ꢡ
ꢜ
ꢟ
ꢜ
ꢞ
ꢢ
ꢩ
ꢢ
ꢠ
ꢧ
ꢩ
ꢜ
ꢲ
ꢧ
ꢥ
ꢧ
ꢦ
ꢥ
ꢠ
ꢡ
ꢜ
ꢝ
ꢜ
ꢥ
ꢩ
ꢟ
ꢪ
ꢞ
ꢨ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢩ
ꢥ
ꢠ
ꢥ
ꢣ
ꢟ
ꢞ
ꢱ
ꢟ
ꢭ
ꢧ
ꢜ
ꢟ
ꢍ
ꢩ
ꢣ
ꢥ
ꢟ
ꢥ
ꢟ
ꢜ
ꢝ
ꢩ
ꢞ
ꢱ
ꢝ
ꢜ
ꢡ
ꢢ
ꢝ
ꢱ
ꢥ
ꢡ
ꢩ
ꢞ
ꢟ
ꢦ
ꢜ
ꢞ
ꢦ
ꢥ
ꢜ
ꢝ
ꢥ
ꢩ
ꢡ
ꢟ
ꢯ
ꢡ
ꢣ
ꢜ
ꢞ
ꢥ
ꢭ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢂꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢂ ꢇ ꢈ
ꢋ ꢌꢍ ꢎ ꢄ ꢏ ꢐ ꢑꢒ ꢓꢈ ꢁ ꢁꢏ ꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢖꢗ ꢄꢋꢍ ꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
analog switch characteristics
T
A
= 25°C
TYP
30
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
V
UNIT
CC
2.3 V
3 V
C
R
= 50 pF,
= 600 Ω,
= 1 MHz (sine wave)
(see Note 6 and Figure 6)
L
L
Frequency response
(switch on)
35
COM or Yn
COM or Yn
INH
Yn or COM
Yn or COM
COM or Yn
Yn or COM
MHz
f
in
4.5 V
2.3 V
3 V
50
−45
−45
−45
20
C
R
= 50 pF,
= 600 Ω,
= 1 MHz (sine wave)
(see Note 7 and Figure 7)
L
L
Crosstalk
(between any switches)
dB
mV
dB
f
in
4.5 V
2.3 V
3 V
C
R
= 50 pF,
= 600 Ω,
= 1 MHz (square wave)
(see Figure 8)
L
L
Crosstalk
(control input to signal output)
35
f
in
4.5 V
2.3 V
3 V
65
−45
−45
−45
C
R
= 50 pF,
= 600 Ω,
= 1 MHz
L
L
Feedthrough attenuation
(switch off)
COM or Yn
f
in
4.5 V
(see Note 7 and Figure 9)
C
R
= 50 pF,
= 10 kΩ,
= 1 kHz
2.3 V
3 V
0.1
0.1
0.1
V = 2 V
p-p
L
L
I
V = 2.5 V
I p-p
Sine-wave distortion
COM or Yn
Yn or COM
f
in
%
(sine wave)
4.5 V
V = 4 V
I p-p
(see Figure 10)
NOTES: 6. Adjust f voltage to obtain 0-dBm output. Increase f frequency until dB meter reads −3 dB.
in in
7. Adjust f voltage to obtain 0-dBm input.
in
operating characteristics, V
= 3.3 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
C
= 50 pF,
f = 10 MHz
5.3
pF
pd
L
PARAMETER MEASUREMENT INFORMATION
V
CC
V
INH
= V
IL
V
CC
V = V
I CC
or GND
V
O
(ON)
GND
VI – VO
W
2 10–3
ron
+
2 mA
V
V − V
I
O
Figure 1. On-State Resistance Test Circuit
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢂ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢂꢇ ꢈ
ꢋꢌ ꢍ ꢎ ꢄꢏ ꢐꢑꢒ ꢓꢈꢁꢁꢏ ꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢖ ꢗꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏ ꢌ ꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
= V
INH
I
IH
V
CC
V
O
A
V
(OFF)
GND
Condition 1: V = 0, V = V
CC
I
O
Condition 2: V = V , V = 0
I
CC
O
Figure 2. Off-State Switch Leakage-Current Test Circuit
V
V
CC
V
INH
= V
IL
CC
A
V
I
Open
(ON)
GND
V = V
I CC
or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
V
V
CC
V
INH
= V
IL
CC
Input
Output
(ON)
GND
C
50 Ω
L
Figure 4. Propagation Delay Time, Signal Input to Signal Output
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢂꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢂ ꢇ ꢈ
ꢋ ꢌꢍ ꢎ ꢄ ꢏ ꢐ ꢑꢒ ꢓꢈ ꢁ ꢁꢏ ꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢖꢗ ꢄꢋꢍ ꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
50 Ω
V
INH
TEST
S1
S2
t
/t
/t
GND
V
CC
GND
V
CC
PLZ PZL
t
V
CC
1 kΩ
V
I
V
O
PHZ PZH
S1
S2
GND
C
L
TEST CIRCUIT
50%
V
CC
V
CC
V
INH
50%
0 V
0 V
t
t
PZH
PZL
≈V
CC
V
OH
V
O
50%
50%
V
OL
≈0 V
(t
, t )
PZL PZH
V
CC
V
CC
V
INH
50%
50%
0 V
0 V
t
t
PLZ
PHZ
≈V
CC
V
OH
V
OH
− 0.3 V
V
O
V
OL
+ 0.3 V
V
OL
≈0 V
(t
, t )
PLZ PHZ
VOLTAGE WAVEFORMS
Figure 5. Switching Time (t
, t
t
, t
), Control to Signal Output
PZL PLZ, PZH PHZ
V
CC
V
INH
= GND
V
CC
f
V
O
in
(ON)
GND
0.1 µF
R
L
50 Ω
C
L
V
CC
/2
NOTE A: f is a sine wave.
in
Figure 6. Frequency Response (Switch On)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢂ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢂꢇ ꢈ
ꢋꢌ ꢍ ꢎ ꢄꢏ ꢐꢑꢒ ꢓꢈꢁꢁꢏ ꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢖ ꢗꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏ ꢌ ꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
INH
= GND
V
CC
f
V
O1
in
50 Ω
(ON)
GND
600 Ω
0.1 µF
R
C
L
L
V
CC
/2
V
CC
V
INH
= V
CC
V
CC
f
(OFF)
GND
V
O2
in
R
C
L
600 Ω
L
V
CC
/2
Figure 7. Crosstalk Between Any Two Switches
50 Ω
V
V
CC
V
INH
CC
V
O
GND
600 Ω
R
L
C
L
V
CC
/2
V
CC
/2
Figure 8. Crosstalk Between Control Input and Switch Output
V
CC
CC
V
INH
= V
CC
0.1 µF
V
f
in
V
O
(OFF)
GND
600 Ω
R
L
C
50 Ω
L
V
CC
/2
V
CC
/2
Figure 9. Feedthrough Attenuation (Switch Off)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢂꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢂ ꢇ ꢈ
ꢋ ꢌꢍ ꢎ ꢄ ꢏ ꢐ ꢑꢒ ꢓꢈ ꢁ ꢁꢏ ꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢖꢗ ꢄꢋꢍ ꢎ ꢄꢏ ꢘꢏꢌꢀ ꢙꢚꢏ ꢖꢗ ꢄꢋ ꢍꢎ ꢄꢏ ꢘꢏꢌꢀ
SCLS430K − MAY 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
INH
= GND
10 µF
10 µF
V
CC
f
in
V
O
(ON)
GND
R
L
600 Ω
C
L
V
CC
/2
Figure 10. Sine-Wave Distortion
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74LV4053AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4053ADBR
SN74LV4053ADBRE4
SN74LV4053ADE4
SN74LV4053ADG4
SN74LV4053ADGVR
SN74LV4053ADGVRE4
SN74LV4053ADR
SSOP
SSOP
SOIC
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4053ADRE4
SN74LV4053ADRG4
SN74LV4053AN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74LV4053ANE4
SN74LV4053ANSR
SN74LV4053ANSRE4
SN74LV4053APW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SO
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
RGY
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4053APWE4
SN74LV4053APWG4
SN74LV4053APWR
SN74LV4053APWRE4
SN74LV4053APWRG4
SN74LV4053APWT
SN74LV4053APWTE4
SN74LV4053APWTG4
SN74LV4053ARGYR
SN74LV4053ARGYRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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