74LV4094DB-T [NXP]
IC LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16, Shift Register;
| 型号： | 74LV4094DB-T |
| 厂家： | 
NXP |
| 描述： | IC LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 5.30 MM, PLASTIC, MO-150, SOT-338-1, SSOP-16, Shift Register 存储 |
| 文件： | 总14页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LV4094
8-stage shift-and-store bus register
Product specification
1998 Jun 23
Philips
Semiconductors
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
FEATURES
DESCRIPTION
The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT4094.
• Optimized for low voltage applications: 1.0 to 3.6 V
• Accepts TTL input levels between V = 2.7 V and V = 3.6 V
CC
CC
The 74LV4094 is an 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input (D) to the parallel buffered 3-State outputs (QP to OP ). The
• Typical V
(output ground bounce) < 0.8 V at V = 3.3 V,
OLP
= 25°C
CC
T
amb
0
7
parallel outputs may be connected directly to the common bus lines.
Data is shifted on the positive-going clock (CP) transitions. The data
in each shift register is transferred to the storage register when the
strobe input (STR) is HIGH. Data in the storage register appears at
the outputs whenever the output enable input (OE) signal is HIGH.
• Typical V
(output V undershoot) > 2 V at V = 3.3 V,
OHV
= 25°C
OH
CC
T
amb
• Output capability: standard
• I category: MSI
CC
Two serial outputs (QS and QS ) are available for cascading a
1
2
Applications:
number of 74LV4094 devices. Data is available at QS on the
1
positive-going clock edges to allow high-speed operation in
cascaded systems in which the clock rise time is fast. The same
• Serial-to-parallel data conversion
• Remote control holding register
serial information is available at QS on the next negative going
2
clock edge and is for cascading 74LV4094 devices when the clock
rise time is slow.
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; t =t ≤ 2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
C = 15 pF;
L
Propagation delay
V
CC
= 3.3 V
CP to QS
CP to QS
CP to QP
STR to QP
14
13
18
17
1
2
n
t
f
/t
ns
PHL PLH
n
Maximum clock frequency
Input capacitance
MHz
pF
95
MAX
C
C
3.5
I
V
= 3.3 V
CC
Power dissipation capacitance per gate
83
pF
PD
NO TAG
V = GND to V
I
CC
NOTE:
1.
C
is used to determine the dynamic power dissipation (P in µW)
D
PD
2
2
P
D
= C × V
× f )ȍ (C × V
× f ) where:
CC o
PD
CC
i
L
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
ȍ (C × V
× f ) = sum of the outputs.
L
CC
o
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LV4094 N
PKG. DWG. #
SOT38-4
16-Pin Plastic DIL
16-Pin Plastic SO
–40°C to +125°C
–40°C to +125°C
74LV4094 N
74LV4094 D
74LV4094 D
SOT109-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
STR
D
16
15
V
CC
1
2
3
STR
D
Strobe input
Serial input
Clock input
2
OE
QP
QP
QP
QP
3
4
5
6
CP
14
13
12
11
CP
4
5
6
7
4, 5, 6, 7, 14,
13, 12, 11
QP
0
QP to QP
Parallel outputs
0
7
QP
1
8
GND
Ground (0 V)
Serial outputs
QP
2
9, 10
15
QS , QS
1
2
7
8
10
9
QP
3
QS
QS
OE
Output enable input
2
1
16
V
Positive supply voltage
GND
CC
SV01611
2
1998 Jun 23
853-2078 19619
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
3
1
1
C2
15
EN3
CP
STR
9
QS
1
SRG8
3
10
4
QS
2
QP
0
QP
1
C1/
4
5
2
1D
2D
5
3
6
QP
QP
QP
2
3
4
2
D
6
7
7
14
14
13
13
12
11
QP
QP
QP
5
6
7
12
11
9
OE
15
SV01612
10
SV01613
FUNCTIONAL DIAGRAM
D
2
QS
QS
8-STATE SHIFT
REGISTER
2
1
10
9
CP
3
STR
8-BIT STORAGE
REGISTER
1
OE
3-STATE OUTPUTS
15
QP QP QP QP QP Q5 QP QP
0
1
2
3
4
1
6
7
4
5
6
7
14
13
12
11
SV01614
LOGIC DIAGRAM
STAGES 1 TO 6
STAGE 0
Q
FF0
CP
STAGE 7
Q
FF7
CP
’
Q
7
D
D
D
Q
D
QS
2
D
Q
CP
CP
CP
latch
D
latch
CP
Q
D
latch
CP
Q
STR
OE
QP
QP
QP
QP
QP
7
0
1
3
5
QP
QP
QP
6
SV01615
2
4
3
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
FUNCTION TABLE
INPUTS
PARALLEL OUTPUT
SERIAL OUTPUTS
QS QS
2
CP
↑
OE
L
STR
X
D
X
X
X
L
QP
Z
QP
Z
0
n
1
Q’
NC
QP
6
↓
L
X
Z
Z
NC
7
↑
H
H
H
H
L
NC
L
NC
Q’
6
Q’
6
Q’
6
NC
NC
NC
↑
H
QP
n–1
n–1
↑
H
H
H
H
QP
↓
H
NC
NC
NC
QP
7
NOTES:
↑
= LOW-to–HIGH CP transition
H
L
X
Z
= HIGH voltage level
= LOW voltage level
= don’t care
↓
Q’
= HIGH-to-LOW CP transition
th
=
the information in the 8 register stage is transferred to the
6
th
8 register stage and QS clock edge.
n
= high impedance OFF-state
NC = no change
TIMING DIAGRAM
CLOCK INPUT
CP
D
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q’0 (FF0)
OUTPUT
STR
OE
Z–state
Z–state
QP
0
INTERNAL Q’6 (FF6)
OUTPUT
QP
QS
QS
6
1
2
SERIAL OUTPUT
SERIAL OUTPUT
SV01616
4
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
NO TAG, NO TAG
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
–0.5 to +7.0
"I
DC input diode current
DC output diode current
V < –0.5 or V > V + 0.5V
20
50
mA
mA
IK
I
I
CC
"I
V
O
< –0.5 or V > V + 0.5V
OK
O
CC
DC output source or sink current
– standard outputs
"I
–0.5V < V < V + 0.5V
mA
O
O
CC
25
DC V or GND current for types with
– standard outputs
CC
"I
"I
,
mA
GND
50
CC
T
stg
Storage temperature range
–65 to +150
°C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
P
TOT
mW
– plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
1.0
0
TYP
3.3
–
MAX
UNIT
V
CC
DC supply voltage
See Note NO TAG
3.6
V
V
V
V
I
Input voltage
V
CC
V
CC
V
O
Output voltage
0
–
See DC and AC
characteristics
–40
–40
+85
+125
T
amb
Operating ambient temperature range in free air
°C
V
CC
V
CC
V
CC
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
–
–
–
–
–
–
500
200
100
Input rise and fall times except for
Schmitt-trigger inputs
t , t
r
ns/V
f
NOTE:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.
CC
CC
CC
CC
5
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, voltages are referenced to GND (ground = 0 V)
LIMITS
MAX
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
TYP
MIN
MIN
MAX
NO TAG
V
V
V
V
V
V
V
V
V
V
= 1.2 V
V
0.6
0.4
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
HIGH level Input
voltage
= 2.0 V
1.4
2.0
1.4
2.0
V
V
V
IH
= 2.7 to 3.6 V
= 1.2 V
GND
0.6
GND
0.6
LOW level Input
voltage
= 2.0 V
V
IL
= 2.7 to 3.6 V
0.8
0.8
= 1.2 V; V = V or V –I = 100µA
1.2
2.0
2.7
3.0
I
IH
IL;
O
= 2.0 V; V = V or V –I = 100µA
1.8
2.5
2.8
1.8
2.5
2.8
I
IH
IL;
O
HIGH level output
voltage; all outputs
V
OH
V
OH
V
V
V
V
= 2.7 V; V = V or V –I = 100µA
I
IH
IL;
O
= 3.0 V; V = V or V –I = 100µA
I
IH
IL;
O
HIGH level output
voltage;
STANDARD
outputs
V
CC
= 3.0 V; V = V or V –I = 6mA
2.40
2.82
2.20
I
IH
IL;
O
V
CC
V
CC
V
CC
V
CC
= 1.2 V; V = V or V I
IL; O
= 100µA
= 100µA
= 100µA
= 100µA
0
0
0
0
I
IH
= 2.0 V; V = V or V I
IL; O
0.2
0.2
0.2
0.2
0.2
0.2
I
IH
LOW level output
voltage; all outputs
V
OL
OL
= 2.7 V; V = V or V I
IL; O
I
IH
= 3.0 V; V = V or V I
IL; O
I
IH
LOW level output
voltage;
STANDARD
outputs
V
V
CC
= 3.0 V; V = V or V I = 6mA
IL; O
0.25
0.40
0.50
I
IH
Input leakage
current
I
V
= 3.6 V; V = V or GND
1.0
5
1.0
10
µA
µA
µA
µA
I
CC
CC
I
CC
3-State output
OFF-state current
V
V
= 3.6 V; V = V or V
I IH IL;
I
OZ
CC
= V or GND
O
CC
Quiescent supply
current; SSI
I
V
V
V
V
= 3.6; V = V or GND; I = 0
20.0
20.0
20.0
500
40
CC
I
CC
O
Quiescent supply
current; flip-flops
= 3.6; V = V or GND; I = 0
80
CC
CC
CC
I
CC
O
Quiescent supply
current; MSI
I
= 3.6 V; V = V or GND; I = 0
160
1000
CC
I
CC
O
µA
µA
Quiescent supply
current; LSI
= 3.6 V; V = V or GND; I = 0
I
CC
O
Additional
quiescent supply
current per input
∆I
CC
V
CC
= 2.7 V to 3.6 V; V = V – 0.6 V
500
850
I
CC
NOTE:
1. All typical values are measured at T
= 25°C.
amb
6
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
AC CHARACTERISTICS
GND = 0 V; t = t ≤ 2.5ns; C = 50pF
r
f
L
LIMITS
–40 to +85 °C
CONDITION
–40 to +125 °C
SYMBOL
PARAMETER
WAVEFORM
UNIT
ns
V
CC
1
MIN
TYP
MAX
MIN
MAX
(V)
1.2
90
31
23
2.0
58
43
34
70
51
41
Propagation delay
t
t
t
t
t
t
t
PHL/ PLH
CP to QS
2.7
1
2
3.0 to 3.6
1.2
17
80
27
20
2.0
51
38
30
61
45
36
Propagation delay
t
ns
PHL/ PLH
CP to QS
2.7
2
2
3.0 to 3.6
1.2
14
115
39
2.0
75
55
44
90
66
53
Propagation delay
t
ns
PHL/ PLH
CP to QP
2.7
29
n
2
3.0 to 3.6
1.2
22
105
36
2.0
68
50
40
82
60
48
Propagation delay
t
ns
PHL/ PLH
STR to QP
2.7
26
n
2
3.0 to 3.6
1.2
20
100
34
3-State Output
enable time
2.0
65
48
38
77
56
45
/t
ns
PZH PZL
2.7
25
OE to QP
n
2
3.0 to 3.6
1.2
19
65
24
18
3-State Output
disable time
2.0
40
32
26
49
37
30
/t
ns
PHZ PLZ
2.7
OE to QP
n
2
3.0 to 3.6
2.0
14
34
25
20
34
25
20
9
6
41
30
24
41
30
24
Clock pulse width
HIGH or LOW
2.7
t
t
ns
ns
w
2
3.0 to 3.6
2.0
5
9
6
Strobe pulse width;
HIGH
2.7
w
2
3.0 to 3.6
1.2
5
25
9
2.0
22
16
13
26
19
15
Set-up time
D to CP
t
ns
ns
su
su
2.7
6
2
3.0 to 3.6
1.2
5
50
17
13
2.0
43
31
51
38
Set-up time
CP to STR
t
2.7
10
3.0 to 3.6
25
30
NO TAG
7
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
CONDITION
–40 to +85 °C
–40 to +125 °C
SYMBOL
PARAMETER
WAVEFORM
UNIT
V
CC
1
MIN
TYP
MAX
MIN
MAX
(V)
1.2
2.0
2.7
–10
–4
5
5
5
5
Hold time
D to CP
T
h
ns
–3
–2
NO TAG
3.0 to 3.6
5
5
NOTES:
1. Unless otherwise stated, all typical values are measured at T
= 25°C
amb
2. Typical values are measured at V = 3.3 V.
CC
8
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
AC CHARACTERISTICS (Continued)
GND = 0 V; t = t ≤ 2.5ns; C = 50pF
r
f
L
CONDITION
–40 to +85 °C
–40 to +125 °C
SYMBOL
PARAMETER
WAVEFORM
UNIT
V
(V)
CC
1
MIN
TYP
MAX
MIN
MAX
1.2
–25
–9
2.0
5
5
5
5
Hold time
D to STR
T
h
ns
2.7
–6
2
3.0 to 3.6
2.0
5
–5
5
14
19
24
52
70
12
16
20
Maximum clock pulse
frequency
2.7
f
MHz
max
2
3.0 to 3.6
87
NOTES:
1. Unless otherwise stated, all typical values are measured at T
= 25°C
amb
2. Typical values are measured at V = 3.3 V.
CC
AC WAVEFORMS
V
V
V
V
V
V
V
= 1.5 V at V ≥ 2.7 V
M
CC
= 0.5 × V at V < 2.7 V.
M
CC
CC
and V are the typical output voltage drop that occur with the output load.
OL
OH
= V + 0.3 V at V ≥ 2.7 V
X
X
Y
Y
OL
CC
= V + 0.1 × V at V < 2.7 ς
OL
CC
CC
= V ± 0.3 V at V ≥ 2.7 V
OH
CC
= V ± 0.1 × V at V < 2.7V
OH
CC
CC
V
CC
1/f
max
V
CC
V
M
CP INPUT
GND
CP INPUT
GND
V
M
t
su
t
h
t
W
t
PHL
V
t
CC
PLH
V
OH
STR INPUT
GND
V
M
V
QP , QS OUTPUT
M
n
1
t
W
V
OL
t
t
PHL
PLH
t
t
PLH
PHL
V
OH
V
OH
QP OUTPUT
n
QS OUTPUT
2
V
M
V
M
V
OL
V
OL
SV01620
SV01619
Figure 2. Strobe (STR) to output (QP ) propagation delays and
the strobe pulse width and the clock set-up and hold times for
strobe input.
n
Figure 1. Clock (CP) to output (QP , QS , QS )
n
1
2
propagation delays, the clock pulse width
and the maximum clock frequency.
9
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
V
CC
V
CC
OE INPUT
GND
V
M
CP INPUT
GND
V
M
t
t
PZL
PLZ
t
t
su
su
V
CC
t
h
t
h
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
V
CC
M
V
V
X
V
OL
D INPUT
GND
V
M
t
PZH
t
PHZ
V
OH
V
OH
V
Y
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
QP , QS , QS OUTPUT
n
1
2
M
V
M
GND
V
OL
outputs
disabled
outputs
enabled
outputs
enabled
SV01618
The shaded areas indicate when the input is permitted to change for predictable
output performance.
SV01617
Figure 3. 3-State enable and disable times for input OE.
Figure 4. Data set-up and hold times for the data input (D).
TEST CIRCUIT
t
W
V
I
90%
S
1
90%
V
cc
V
Open
GND
S1
V
V
M
M
NEGATIVE
PULSE
10%
10%
90%
0V
(t )
R
R
= 1k
L
L
V
V
O
t
t
(t )
t
TLH
l
THL
TLH
f
r
PULSE
GENERATOR
D.U.T.
(t )
r
t
(t )
THL f
V
= 1k
R
T
I
90%
M
C = 50pF
L
POSITIVE
PULSE
V
V
M
10%
10%
t
W
0V
Test Circuit for Outputs
V
M
= 1.5V
Input Pulse Definition
DEFINITIONS
SWITCH POSITION
R = Load resistor
L
TEST
S
1
V
CC
V
I
V
S1
C = Load capacitance includes jig and probe capacitance
L
t
t
Open
< 2.7V
2.7–3.6V
≥ 4.5 V
V
2 < V
2 < V
2 < V
PLH/ PHL
CC
CC
CC
CC
R = Termination resistance should be equal to Z
T
of
OUT
t
t
V
S1
2.7V
PLZ/ PZL
pulse generators.
t
/t
GND
V
CC
PHZ PZH
SY00044
Figure 5. Load circuitry for switching times.
10
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
11
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
12
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
NOTES
13
1998 Jun 23
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 08-98
9397-750-04662
Document order number:
Philips
Semiconductors
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