74LVC10 [NXP]
Triple 3-input NAND gate; 三路3输入与非门
| 型号： | 74LVC10 |
| 厂家： | 
NXP |
| 描述： | Triple 3-input NAND gate |
| 文件： | 总8页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC10
Triple 3-input NAND gate
Product specification
1997 Apr 28
Replaces data sheet of 1996 Feb
IC24 Data Handbook
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10
FEATURES
DESCRIPTION
The 74LVC10 is a high performance, low power, low voltage, Si gate
CMOS device and superior to most advanced CMOS compatible
TTL families.
• Wide supply voltage range of 1.2 V to 3.6 V
• In accordance with JEDEC standard no. 8-1A.
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Output capability: standard
The 74LVC10 provides the 3-input NAND function.
• I category: SSI
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; t = t v2.5 ns
amb
r f
SYMBOL
/t
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
nA, nB, nC to nY
C = 50 pF;
L
CC
t
3.9
ns
PHL PLH
V
= 3.3 V
C
Input capacitance
5.0
26
pF
pF
I
1
C
Power dissipation capacitance per gate
V = GND to V
I CC
PD
NOTE:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C × V
× f )ȍ (C × V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
ȍ (C × V
× f ) = sum of the outputs.
L
CC
o
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LVC10 D
DWG NUMBER
SOT108-1
14-Pin Plastic SO
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC10 D
74LVC10 DB
74LVC10 PW
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
74LVC10 DB
SOT337-1
74LVC10PW DH
SOT402-1
PIN CONFIGURATION
LOGIC SYMBOL
V
1
2
1A
1B
1A
1B
1
2
3
4
5
6
7
14
CC
1Y 12
13 1C
13 1C
2A
12 1Y
11 3C
10 3B
3
4
5
2A
2B
2C
2B
2Y
3Y
6
8
2C
2Y
9
8
3A
3Y
9
3A
10 3B
11 3C
GND
SV00416
SV00417
PIN DESCRIPTION
PIN
SYMBOL
NUMBER
NAME AND FUNCTION
Data inputs
1, 3, 9
2, 4, 10
7
1A – 3A
1B – 3B
GND
Data inputs
Ground (0 V)
Data outputs
12, 6, 8
13, 5, 11
14
1Y – 3Y
1C – 3C
Data inputs
V
CC
Positive supply voltage
2
1997 Apr 28
853-1973 17997
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10
LOGIC SYMBOL (IEEE/IEC)
FUNCTION TABLE
INPUTS
OUTPUTS
nY
1
&
2
12
13
nA
nB
nC
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
3
4
5
&
6
9
10
11
&
H
8
H
H
H
H
L
L
H
H
L
H
L
H
H
H
L
SV00418
H
LOGIC DIAGRAM (ONE GATE)
NOTES:
H = HIGH voltage level
L = LOW voltage level
A
B
C
Y
SV00419
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
2.7
1.2
0
MAX
V
V
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
3.6
3.6
5.5
V
V
CC
CC
V
I
V
V
DC input voltage range for I/Os
0
V
V
I/O
CC
CC
V
DC output voltage range
0
V
V
O
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +6.5
–50
UNIT
V
V
CC
I
IK
DC input diode current
DC input voltage
V t 0
mA
V
I
V
I
Note 2
–0.5 to +5.5
V
DC input voltage range for I/Os
DC output diode current
DC output voltage
–0.5 to V +0.5
V
I/O
OK
CC
I
V
uV or V t 0
"50
mA
V
O
CC
O
V
Note 2
= 0 to V
–0.5 to V +0.5
OUT
OUT
CC
I
DC output source or sink current
V
O
"50
"100
mA
mA
°C
CC
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–60 to +150
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
P
TOT
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3
1997 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V
V
CC
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
IL
= 2.7 to 3.6V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
I
IH
IL
O
CC
CC
CC
CC
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*1.0
V
CC
I
IH
IL
O
V
OH
HIGH level output voltage
LOW level output voltage
V
= 3.0V; V = V or V I
= –12mA
I = –24mA
I
IH
IL; O
= 3.0V; V = V or V
IL; O
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
I
IH
IL
O
= 3.0V; V = V or V ; I = 100µA
V
OL
V
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
I
Input leakage current
= 3.6V; V = 5.5V or GND Not for I/O pins
"0.1
"0.1
0.1
µA
µA
µA
µA
I
I
I
/I
Input current for common I/O pins
3-State output OFF-state current
Quiescent supply current
= 3.6V; V = V or GND
"15
"10
20
IHZ ILZ
I
CC
I
= 3.6V; V = V or V ; V = V or GND
I IH IL O CC
OZ
CC
I
= 3.6V; V = V or GND; I = 0
0.1
I
CC
O
Additional quiescent supply current per
input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
5
500
µA
I
CC
O
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC CHARACTERISTICS
GND = 0 V; t = t v 2.5 ns; C = 50 pF
r
f
L
LIMITS
V
V
CC
= 3.3V ±0.3V
= 2.7V
V
CC
= 1.2V
SYMBOL
PARAMETER
WAVEFORM
UNIT
CC
1
MIN
–
TYP
MAX
6.4
MIN
MAX
7.5
TYP
t
t
/
Propagation delay
nA, nB, nC to nY
PHL
Figures 1, 2
3.9
–
–
ns
PLH
NOTE:
1. These typical values are at V = 3.3V and T
= 25°C.
amb
CC
AC WAVEFORMS
TEST CIRCUIT
V
V
V
= 1.5 V at V w 2.7 V
M
CC
S
1
= 0.5 S V at V < 2.7 V
M
CC
CC
2 < V
Open
CC
V
CC
and V are the typical output voltage drop that occur with the
OL
OH
GND
output load.
500Ω
500Ω
V
V
O
I
PULSE
GENERATOR
D.U.T.
V
I
nA, nB, nC
INPUT
GND
50pF
C
V
L
R
T
M
t
t
PLH
PHL
V
Test
/t
S
1
OH
V
V
nY OUTPUT
V
V
M
CC
I
t
Open
PLH PHL
t 2.7V
2.7V – 3.6V
V
t
/t
2 < V
CC
CC
PLZ PZL
OL
2.7V
t
/t
GND
PHZ PZH
SV00420
SY00003
Figure 1. Input (nA, nB, nC) to output (nY)
propagation delays.
Figure 2. Load circuitry for switching times.
4
1997 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
5
1997 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
6
1997 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
7
1997 Apr 28
Philips Semiconductors
Product specification
Triple 3-input NAND gate
74LVC10
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
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