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74LVC169BQ,115 [NXP]

74LVC169 - Presettable synchronous 4-bit up/down binary counter QFN 16-Pin;
74LVC169BQ,115
型号： 74LVC169BQ,115
厂家： NXP    NXP
描述：

74LVC169 - Presettable synchronous 4-bit up/down binary counter QFN 16-Pin

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74LVC169  
Presettable synchronous 4-bit up/down binary counter  
Rev. 6 — 29 November 2012  
Product data sheet  
1. General description  
The 74LVC169 is a synchronous presettable 4-bit binary counter which features an  
internal look-ahead carry circuitry for cascading in high-speed counting applications.  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that  
the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by  
the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation  
eliminates the output counting spikes that are normally associated with asynchronous  
(ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the  
LOW-to-HIGH transition of the clock.  
The counter is fully programmable; that is, the outputs may be preset to any number  
between 0 and its maximum count. Presetting is synchronous with the clock and takes  
place regardless of the levels of the count enable inputs. A LOW level on the parallel  
enable (pin PE) input disables the counter and causes the data at the Dn input to be  
loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of  
the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the  
counter counts up, when LOW, it counts down.  
The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous  
applications without additional gating. Instrumental in accomplishing this function are two  
count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both  
count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed  
forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a  
LOW-level output pulse with a duration approximately equal to a HIGH level portion of  
pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded  
stages.  
The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing  
the control of data input signals in either state of the clock. The only requirement is that  
the various inputs attain the desired state at least a set-up time before the next  
LOW-to-HIGH transition of the clock and remain valid for the recommended hold time  
thereafter.  
The parallel load operation takes precedence over the other operations, as indicated in  
the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters  
the flip-flops on the next LOW-to-HIGH transition of the clock.  
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be  
HIGH. The pin U/D input determines the direction of the counting. The terminal count  
output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW,  
when a counter reaches 15 in the count up mode. The pin TC output state is not a function  
of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by  
decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For  
this reason the use of pin TC as a clock signal is not recommended; see the following  
logic equations:  
count enable = CEP CET PE  
count up: TC = Q3 Q2 Q1 Q0 CET U D  
count down: TC = Q3 Q2 Q1 Q0 CET U D  
2. Features and benefits  
5 V tolerant inputs for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Up/down counting  
Two count enable inputs for n-bit cascading  
Built-in look-ahead carry capability  
Presettable for programmable operation  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
2 of 24  
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
3. Ordering information  
Table 1.  
Ordering information  
Type number Temperature range Package  
Name  
Description  
Version  
74LVC169D  
40 C to +125 C  
SO16  
plastic small outline package; 16 leads;  
body width 3.9 mm  
SOT109-1  
74LVC169DB 40 C to +125 C  
74LVC169PW 40 C to +125 C  
74LVC169BQ 40 C to +125 C  
SSOP16  
TSSOP16  
plastic shrink small outline package; 16 leads;  
body width 5.3 mm  
SOT338-1  
SOT403-1  
plastic thin shrink small outline package; 16 leads;  
body width 4.4 mm  
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1  
quad flat package; no leads; 16 terminals;  
body 2.5 3.5 0.85 mm  
4. Functional diagram  
CTR4  
M1 [LOAD]  
9
M2 [COUNT]  
M3 [UP]  
3
4
5
6
1
M4 [DOWN]  
D0  
D1  
D2  
D3  
15  
10  
7
3, 5 CT=15  
4, 5 CT=0  
G5  
G6  
9
1
PE  
U/D  
CP  
2, 3, 5, 6+/C7  
2, 3, 5, 6−  
2
15  
2
TC  
7
CEP  
CET  
Q0  
14  
13  
12  
11  
3
4
5
6
1,7D  
[1]  
[2]  
[4]  
[8]  
10  
Q1 Q2  
Q3  
11  
14  
13  
12  
001aaa645  
001aaa646  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
3 of 24  
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
D
Q
Q
3
D0  
14  
13  
12  
11  
Q0  
Q1  
Q2  
Q3  
CP  
D
Q
Q
4
D1  
CP  
D
Q
Q
5
D2  
CP  
D
Q
Q
6
D3  
CP  
9
PE  
7
10  
CEP  
CET  
2
CP  
1
U/D  
15  
TC  
001aaa649  
Fig 3. Logic diagram  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
4 of 24  
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
5. Pinning information  
5.1 Pinning  
74LVC169  
terminal 1  
index area  
74LVC169  
2
3
4
5
6
7
15  
14  
13  
12  
11  
10  
CP  
D0  
TC  
Q0  
Q1  
Q2  
Q3  
CET  
U/D  
CP  
1
2
3
4
5
6
7
8
16 V  
CC  
D1  
15 TC  
14 Q0  
13 Q1  
12 Q2  
11 Q3  
10 CET  
D0  
D2  
D1  
D3  
(1)  
GND  
D2  
CEP  
D3  
CEP  
GND  
001aaa682  
9
PE  
Transparent top view  
001aaa644  
(1) This is not a supply pin. The substrate is attached to this  
pad using conductive die attach material. There is no  
electrical or mechanical requirement to solder this pad.  
However, if it is soldered, the solder land should remain  
floating or be connected to GND.  
Fig 4. Pin configuration for SO16 and (T)SSOP16  
Fig 5. Pin configuration for DHVQFN16  
5.2 Pin description  
Table 2.  
Symbol  
U/D  
Pin description  
Pin  
Description  
1
up/down control input  
CP  
2
clock input (LOW-to-HIGH, edge-triggered)  
data input  
D0 to D3  
CEP  
3, 4, 5, 6  
7
count enable input (active LOW)  
ground (0 V)  
GND  
PE  
8
9
parallel enable input (active LOW)  
count enable carry input (active LOW)  
flip-flop output  
CET  
10  
Q0 to Q3  
TC  
14, 13, 12, 11  
15  
16  
terminal count output (active LOW)  
supply voltage  
VCC  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
5 of 24  
 
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
6. Functional description  
Table 3.  
Function table[1]  
Operating mode  
Input  
Output  
CP  
U/D  
X
CEP  
CET  
PE  
I
Dn  
I
Qn  
TC  
*
Parallel load (Dn to Qn)  
X
X
I
X
X
I
L
X
l
h
H
*
Count up (increment)  
Count down (decrement)  
Hold (do nothing)  
h
h
h
h
h
X
X
X
X
count up  
count down  
qn  
*
I
I
I
*
X
h
X
X
X
*
X
qn  
H
[1] H = HIGH voltage level steady state  
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition  
L = LOW voltage level steady state  
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition  
qn = Lower case letters indicate state of referenced output prior to the LOW-to-HIGH clock transition  
X = don’t care  
= LOW-to-HIGH clock transition  
* = The TC is LOW when CET is LOW and the counter is at terminal count  
Terminal count up is (HHHH) and terminal count down is (LLLL)  
0
1
2
3
4
5
6
7
8
15  
14  
13  
12  
11  
10  
9
count down  
count up  
001aaa647  
Fig 6. State diagram  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
6 of 24  
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
PE  
D0  
D1  
D2  
D3  
CP  
U/D  
CEP and CET  
Q0  
Q1  
Q2  
Q3  
TC  
13  
14  
15  
0
1
2
2
2
1
0
15  
14  
13  
load  
count up  
inhibit  
count down  
001aaa648  
The following sequence is illustrated:  
- Load (preset) to thirteen.  
- Count up to fourteen, fifteen (maximum), zero, one and two.  
- Inhibit.  
- Count down to one, zero (minimum), fifteen, fourteen and thirteen.  
Fig 7. Typical timing sequence  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
7 of 24  
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
7. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
0.5  
50  
0.5  
-
Max  
+6.5  
-
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
[1]  
[2]  
VI  
+5.5  
50  
VCC + 0.5  
50  
100  
-
IOK  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
mA  
V
VO  
0.5  
-
IO  
output current  
mA  
mA  
mA  
C  
ICC  
supply current  
-
IGND  
Tstg  
Ptot  
ground current  
100  
65  
-
storage temperature  
total power dissipation  
+150  
500  
[3]  
Tamb = 40 C to +125 C  
mW  
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.  
[2] The output voltage ratings may be exceeded if the output current ratings are observed.  
[3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.  
For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.  
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.  
8. Recommended operating conditions  
Table 5.  
Symbol  
VCC  
Recommended operating conditions  
Parameter  
Conditions  
Min  
1.65  
1.2  
0
Typ  
Max  
3.6  
-
Unit  
V
supply voltage  
-
-
-
-
-
-
-
functional  
V
VI  
input voltage  
5.5  
VCC  
+125  
20  
V
VO  
output voltage  
0
V
Tamb  
t/V  
ambient temperature  
input transition rise and fall rate  
in free air  
40  
0
C  
ns/V  
ns/V  
VCC = 1.65 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
0
10  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
8 of 24  
 
 
 
 
 
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
9. Static characteristics  
Table 6.  
Static characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C  
Unit  
Min  
Typ[1]  
Max  
Min  
Max  
VIH  
HIGH-level  
input voltage  
VCC = 1.2 V  
1.08  
-
-
-
-
-
-
-
-
-
1.08  
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 1.2 V  
0.65 VCC  
-
0.65 VCC  
-
1.7  
-
1.7  
-
2.0  
-
0.12  
2.0  
-
0.12  
VIL  
LOW-level  
input voltage  
-
-
-
-
-
-
-
-
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VI = VIH or VIL  
0.35 VCC  
0.7  
0.35 VCC  
0.7  
0.8  
0.8  
VOH  
HIGH-level  
output  
voltage  
IO = 100 A;  
VCC = 1.65 V to 3.6 V  
VCC 0.2  
-
-
VCC 0.3  
-
V
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 18 mA; VCC = 3.0 V  
IO = 24 mA; VCC = 3.0 V  
VI = VIH or VIL  
1.2  
1.8  
2.2  
2.4  
2.2  
-
-
-
-
-
-
-
-
-
-
1.05  
1.65  
2.05  
2.25  
2.0  
-
-
-
-
-
V
V
V
V
V
VOL  
LOW-level  
output  
voltage  
IO = 100 A;  
VCC = 1.65 V to 3.6 V  
-
-
0.2  
-
0.3  
V
IO = 4 mA; VCC = 1.65 V  
IO = 8 mA; VCC = 2.3 V  
-
-
-
-
-
-
0.45  
0.6  
-
-
-
-
-
0.65  
0.8  
V
-
V
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
VCC = 3.6 V; VI = 5.5 V or GND  
-
-
0.4  
0.6  
V
0.55  
5  
0.8  
V
II  
input  
0.1  
20  
A  
leakage  
current  
ICC  
supply  
current  
VCC = 3.6 V; VI = VCC or GND;  
IO = 0 A  
-
-
0.1  
5
10  
-
-
40  
A  
A  
ICC  
additional  
supply  
per input pin; VCC = 2.7 V to 3.6 V;  
VI = VCC 0.6 V; IO = 0 A  
500  
5000  
current  
CI  
input  
VCC = 0 V to 3.6 V;  
-
5.0  
-
-
-
pF  
capacitance VI = GND to VCC  
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
9 of 24  
 
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
10. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
[2]  
[2]  
[2]  
[2]  
tpd  
propagation delay  
CP to Qn; see Figure 8  
VCC = 1.2 V  
-
17  
7.1  
4.1  
3.9  
3.7  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.5  
2.4  
1.5  
1.5  
13.1  
7.4  
7.2  
6.6  
1.5  
2.4  
1.5  
1.5  
15.1  
8.6  
9.0  
VCC = 3.0 V to 3.6 V  
CP to TC; see Figure 8  
VCC = 1.2 V  
10.0  
-
21  
8.5  
4.9  
4.7  
4.4  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
2.0  
3.0  
1.5  
1.5  
14.9  
8.4  
8.8  
7.5  
2.0  
3.0  
1.5  
1.5  
17.2  
9.7  
11.0  
9.5  
VCC = 3.0 V to 3.6 V  
CET to TC; see Figure 9  
VCC = 1.2 V  
-
19  
6.6  
3.8  
4.0  
3.4  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
1.5  
2.2  
1.5  
1.5  
12.3  
7.0  
7.2  
6.2  
1.5  
2.2  
1.5  
1.5  
14.2  
8.1  
9.0  
8.0  
V
CC = 2.3 V to 2.7 V  
VCC = 2.7 V  
VCC = 3.0 V to 3.6 V  
U/D to TC; see Figure 10  
VCC = 1.2 V  
-
21  
7.3  
4.2  
4.4  
3.8  
-
-
-
ns  
ns  
ns  
ns  
ns  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
1.7  
1.5  
1.5  
13.7  
7.7  
8.2  
6.9  
1.0  
1.7  
1.5  
1.5  
15.8  
8.9  
10.5  
9.0  
VCC = 3.0 V to 3.6 V  
CP HIGH or LOW; see Figure 8  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
tW  
pulse width  
6.0  
5.0  
5.0  
4.0  
-
-
-
-
-
-
6.0  
5.0  
5.0  
4.0  
-
-
-
-
ns  
ns  
ns  
ns  
-
VCC = 3.0 V to 3.6 V  
1.2  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
10 of 24  
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
Table 7.  
Dynamic characteristics …continued  
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
tsu  
set-up time  
Dn to CP; see Figure 11  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
5.5  
4.5  
3.0  
2.5  
-
-
-
-
-
-
5.5  
4.5  
3.0  
2.5  
-
-
-
-
ns  
ns  
ns  
ns  
-
VCC = 3.0 V to 3.6 V  
PE to CP; see Figure 11  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
4.5  
4.0  
3.5  
3.0  
-
-
-
-
-
-
4.5  
4.0  
3.5  
3.0  
-
-
-
-
ns  
ns  
ns  
ns  
-
VCC = 3.0 V to 3.6 V  
U/D to CP; see Figure 12  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.2  
9.0  
7.0  
6.5  
5.5  
-
-
-
-
-
-
9.0  
7.0  
6.5  
5.5  
-
-
-
-
ns  
ns  
ns  
ns  
-
VCC = 3.0 V to 3.6 V  
CEP, CET to CP; see Figure 12  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
2.8  
9.0  
6.0  
5.5  
4.5  
-
-
-
-
-
-
9.0  
6.0  
5.5  
4.5  
-
-
-
-
ns  
ns  
ns  
ns  
-
VCC = 3.0 V to 3.6 V  
2.1  
th  
hold time  
Dn, PE, CEP, CET, U/D to CP;  
see Figure 11 and 12  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
1.0  
1.0  
0.0  
0.5  
-
-
-
-
-
-
1.0  
1.0  
0.0  
0.5  
-
-
-
-
ns  
ns  
ns  
ns  
-
VCC = 3.0 V to 3.6 V  
see Figure 8  
0.0  
fmax  
maximum  
frequency  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V  
100  
125  
150  
150  
-
-
-
80  
100  
120  
120  
-
-
MHz  
MHz  
MHz  
MHz  
ns  
-
-
-
-
-
-
200  
-
VCC = 3.0 V to 3.6 V  
VCC = 3.0 V to 3.6 V  
-
-
[3]  
tsk(o)  
output skew time  
1.0  
1.5  
74LVC169  
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Product data sheet  
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NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
Table 7.  
Dynamic characteristics …continued  
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.  
Symbol Parameter  
Conditions  
40 C to +85 C  
40 C to +125 C Unit  
Min  
Typ[1]  
Max  
Min  
Max  
[4]  
CPD  
power dissipation  
capacitance  
per input pin; VI = GND to VCC  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
-
-
-
12.7  
16.4  
19.7  
-
-
-
-
-
-
-
-
-
pF  
pF  
pF  
VCC = 3.0 V to 3.6 V  
[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.  
[2] tpd is the same as tPLH and tPHL  
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.  
[4] PD is used to determine the dynamic power dissipation (PD in W).  
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:  
fi = input frequency in MHz; fo = output frequency in MHz  
CL = output load capacitance in pF  
VCC = supply voltage in Volt  
N = number of inputs switching  
(CL VCC2 fo) = sum of outputs  
11. Waveforms  
1/f  
max  
V
I
CP input  
V
M
GND  
t
W
t
t
PLH  
PHL  
V
OH  
V
Qn, TC output  
M
V
OL  
001aaa651  
Measurement points are given in Table 8.  
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.  
Fig 8. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency  
74LVC169  
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Product data sheet  
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74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
V
I
V
CET  
M
GND  
t
t
PLH  
PHL  
V
V
OH  
I
V
TC  
M
V
OL  
001aaa652  
Measurement points are given in Table 8.  
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.  
Fig 9. Input (CET) to output (TC) propagation delays  
V
I
V
U/D  
TC  
M
GND  
t
t
PLH  
PHL  
V
V
OH  
I
V
M
V
OL  
001aaa653  
Measurement points are given in Table 8.  
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.  
Fig 10. The up/down control input (U/D) to output (TC) propagation delays  
74LVC169  
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Product data sheet  
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13 of 24  
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
V
I
V
PE input  
M
t
GND  
t
su  
su  
t
t
h
h
V
I
V
CP input  
M
GND  
t
t
su  
su  
t
t
h
h
V
I
V
Dn input  
M
GND  
001aaa654  
The shaded areas indicate when the input is permitted to change for predictable output performance.  
Measurement points are given in Table 8.  
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.  
Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE)  
V
I
V
CEP, CET, U/D input  
M
GND  
t
t
h
h
t
t
su  
su  
V
I
V
CP input  
M
GND  
001aaa655  
The shaded areas indicate when the input is permitted to change for predictable output performance.  
Measurement points are given in Table 8.  
Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load.  
Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input (U/D)  
Table 8.  
Measurement points  
Supply voltage  
VCC  
Input  
VI  
Output  
VM  
VM  
1.2 V  
VCC  
VCC  
VCC  
2.7 V  
2.7 V  
0.5 VCC  
0.5 VCC  
0.5 VCC  
1.5 V  
0.5 VCC  
0.5 VCC  
0.5 VCC  
1.5 V  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
3.0 V to 3.6 V  
1.5 V  
1.5 V  
74LVC169  
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Product data sheet  
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14 of 24  
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
EXT  
R
V
CC  
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
001aae331  
Test data is given in Table 9.  
Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig 13. Test circuit for measuring switching times  
Table 9.  
Test data  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
S1 position  
tPLH, tPHL  
open  
tr, tf  
RL  
1.2 V  
VCC  
VCC  
VCC  
2.7 V  
2.7 V  
2 ns  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
30 pF  
50 pF  
50 pF  
1 k[1]  
1 k[1]  
500   
500   
500   
1.65 V to 1.95 V  
2.3 V to 2.7 V  
2.7 V  
open  
open  
open  
3.0 V to 3.6 V  
open  
[1] The circuit performs better when RL = 1000 k.  
74LVC169  
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Product data sheet  
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74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
12. Application information  
CP  
U/D  
PE  
D0 D1 D2 D3  
D0 D1 D2 D3  
PE  
D0 D1 D2 D3  
PE  
D0 D1 D2 D3  
PE  
PE  
U/D  
CP  
U/D  
CP  
U/D  
CP  
U/D  
CP  
TC  
CEP  
CET  
TC  
CEP  
CET  
TC  
CEP  
CET  
TC  
CEP  
CET  
Q0 Q1 Q2 Q3  
Q0 Q1 Q2 Q3  
Q0 Q1 Q2 Q3  
Q0 Q1 Q2 Q3  
least significant  
4-bit counter  
most significant  
4-bit counter  
001aaa650  
Fig 14. Synchronous multistage counting scheme  
74LVC169  
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Product data sheet  
Rev. 6 — 29 November 2012  
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74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
13. Package outline  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
v
c
y
H
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.39  
0.014 0.0075 0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT109-1  
076E07  
MS-012  
Fig 15. Package outline SOT109-1 (SO16)  
74LVC169  
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Product data sheet  
Rev. 6 — 29 November 2012  
17 of 24  
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm  
SOT338-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
8
1
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
6.4  
6.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
1.00  
0.55  
mm  
2
0.25  
0.65  
1.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT338-1  
MO-150  
Fig 16. Package outline SOT338-1 (SSOP16)  
74LVC169  
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Product data sheet  
Rev. 6 — 29 November 2012  
18 of 24  
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm  
SOT403-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
(A )  
3
A
2
A
A
1
pin 1 index  
θ
L
p
L
1
8
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
5.1  
4.9  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.40  
0.06  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT403-1  
MO-153  
Fig 17. Package outline SOT403-1 (TSSOP16)  
74LVC169  
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Product data sheet  
Rev. 6 — 29 November 2012  
19 of 24  
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;  
16 terminals; body 2.5 x 3.5 x 0.85 mm  
SOT763-1  
B
A
D
A
A
1
E
c
detail X  
terminal 1  
index area  
C
terminal 1  
index area  
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16  
15  
10  
D
h
X
0
2.5  
scale  
5 mm  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.  
0.05 0.30  
0.00 0.18  
3.6  
3.4  
2.15  
1.85  
2.6  
2.4  
1.15  
0.85  
0.5  
0.3  
mm  
0.05  
0.1  
1
0.2  
0.5  
2.5  
0.1  
0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-10-17  
03-01-27  
SOT763-1  
- - -  
MO-241  
- - -  
Fig 18. Package outline SOT763-1 (DHVQFN16)  
74LVC169  
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Product data sheet  
Rev. 6 — 29 November 2012  
20 of 24  
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
14. Abbreviations  
Table 10. Abbreviations  
Acronym  
CDM  
DUT  
Description  
Charged Device Model  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
HBM  
MM  
TTL  
Transistor-Transistor Logic  
15. Revision history  
Table 11. Revision history  
Document ID  
Release date  
20121129  
Data sheet status  
Change notice  
Supersedes  
74LVC169 v.6  
Product data sheet  
-
74LVC169 v.5  
Modifications:  
• Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage  
ranges.  
74LVC169 v.5  
74LVC169 v.4  
74LVC169 v.3  
74LVC169 v.2  
74LVC169 v.1  
20090608  
20041014  
20040512  
19980520  
19960823  
Product data sheet  
Product specification  
Product specification  
Product specification  
Product specification  
-
-
-
-
-
74LVC169 v.4  
74LVC169 v.3  
74LVC169 v.2  
74LVC169 v.1  
-
74LVC169  
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Product data sheet  
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21 of 24  
 
 
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NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
16. Legal information  
16.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use — NXP Semiconductors products are not designed,  
16.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
16.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
22 of 24  
 
 
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
16.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
17. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
74LVC169  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2012. All rights reserved.  
Product data sheet  
Rev. 6 — 29 November 2012  
23 of 24  
 
 
74LVC169  
NXP Semiconductors  
Presettable synchronous 4-bit up/down binary counter  
18. Contents  
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
6
Functional description . . . . . . . . . . . . . . . . . . . 6  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Recommended operating conditions. . . . . . . . 8  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9  
Dynamic characteristics . . . . . . . . . . . . . . . . . 10  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Application information. . . . . . . . . . . . . . . . . . 16  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21  
7
8
9
10  
11  
12  
13  
14  
15  
16  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
16.1  
16.2  
16.3  
16.4  
17  
18  
Contact information. . . . . . . . . . . . . . . . . . . . . 23  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2012.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 29 November 2012  
Document identifier: 74LVC169  
 

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