74LVC1G58GW-Q100 [NXP]
IC SPECIALTY LOGIC CIRCUIT, Logic IC:Other;
| 型号： | 74LVC1G58GW-Q100 |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY LOGIC CIRCUIT, Logic IC:Other 光电二极管 逻辑集成电路 |
| 文件： | 总17页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G58-Q100
Low-power configurable multiple function gate
Rev. 1 — 10 June 2014
Product data sheet
1. General description
The 74LVC1G58-Q100 provides configurable multiple functions. The output state is
determined by eight patterns of 3-bit input. The user can choose the logic functions AND,
OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
plastic surface-mounted package; 6 leads
Version
74LVC1G58GW-Q100 40 C to +125 C
74LVC1G58GV-Q100 40 C to +125 C
SC-88
SOT363
TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G58GW-Q100
74LVC1G58GV-Q100
YK
V58
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
A
4
Y
1
B
6
C
001aab687
Fig 1. Logic symbol
6. Pinning information
6.1 Pinning
ꢀꢁ/9&ꢂ*ꢃꢄꢅ4ꢂꢆꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
%
*1'
$
&
9
<
&&
DDDꢀꢁꢂꢃꢄꢅꢁ
Fig 2. Pin configuration SOT363 and SOT457
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
2 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
1
Description
data input
B
GND
A
2
ground (0 V)
data input
3
Y
4
data output
supply voltage
data input
VCC
C
5
6
7. Functional description
Table 4.
Function table[1]
Inputs
Output
C
L
B
L
A
L
Y
L
L
L
H
L
H
L
L
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
L
H
H
H
L
[1] H = HIGH voltage level; L = LOW voltage level
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input NAND
see Figure 3
see Figure 6
see Figure 4 and 5
see Figure 4 and 5
see Figure 6
see Figure 3
see Figure 7
see Figure 8
see Figure 9
2-input NAND with both inputs inverted
2-input AND with inverted input
2-input NOR with inverted input
2-input OR
2-input OR with both inputs inverted
2-input XOR
Buffer
Inverter
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
3 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
V
CC
V
CC
B
Y
C
B
C
Y
Y
B
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
B
Y
C
B
C
001aab689
001aab688
Fig 3. 2-input NAND gate or 2-input OR with both
inputs inverted
Fig 4. 2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
V
CC
V
CC
A
C
A
C
Y
Y
Y
Y
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
C
Y
A
C
A
A
C
A
001aab690
001aab691
Fig 5. 2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
Fig 6. 2-input OR gate or 2-input NAND gate with
both inputs inverted
V
CC
V
CC
B
1
2
3
6
5
4
C
Y
1
2
3
6
5
4
B
C
A
Y
Y
A
Y
001aab692
001aab693
Fig 7. 2-input XOR gate
Fig 8. Buffer
V
CC
B
1
2
3
6
5
4
B
Y
Y
001aab694
Fig 9. Inverter
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
4 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
50
+6.5
+6.5
50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1][2]
[1][2]
VO
0.5
0.5
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
100
65
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
1.65
0
Typ
Max
5.5
Unit
supply voltage
input voltage
output voltage
-
-
-
-
-
V
VI
5.5
V
VO
Active mode
0
VCC
5.5
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
40
+125
C
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
5 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = 40 C to +85 C
VOL
LOW-level output voltage VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
0.45
0.3
0.4
0.55
0.55
VOH
HIGH-level output voltage VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
VCC 0.1 -
-
V
1.2
1.9
2.2
2.3
3.8
-
-
-
V
IO = 8 mA; VCC = 2.3 V
-
-
V
IO = 12 mA; VCC = 2.7 V
-
-
V
IO = 24 mA; VCC = 3.0 V
-
-
V
IO = 32 mA; VCC = 4.5 V
-
-
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
0.1
0.1
0.1
5
10
10
A
A
A
IOFF
ICC
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
supply current
VI = 5.5 V or GND;
-
VCC = 1.65 V to 5.5 V; IO = 0 A
ICC
additional supply current VI = VCC 0.6 V; IO = 0 A;
-
-
5
500
-
A
VCC = 2.3 V to 5.5 V
CI
input capacitance
2.5
pF
Tamb = 40 C to +125 C
VOL LOW-level output voltage VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.7
0.45
0.6
0.8
0.8
V
V
V
V
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VOH
HIGH-level output voltage VI = VT+ or VT
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
VCC 0.1 -
-
V
0.95
1.7
1.9
2.0
3.4
-
-
-
-
-
-
-
-
V
IO = 8 mA; VCC = 2.3 V
-
V
IO = 12 mA; VCC = 2.7 V
-
V
IO = 24 mA; VCC = 3.0 V
-
V
IO = 32 mA; VCC = 4.5 V
-
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
100
A
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
6 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V
ICC
Conditions
Min
Typ[1]
Max
200
200
Unit
A
-
-
-
-
supply current
VI = 5.5 V or GND;
A
VCC = 1.65 V to 5.5 V; IO = 0 A
ICC
additional supply current VI = VCC 0.6 V; IO = 0 A;
CC = 2.3 V to 5.5 V
-
-
5000
A
V
[1] Typical values are measured at maximum VCC and Tamb = 25 C.
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
tpd
propagation delay
A, B, C to Y; see Figure 10
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
0.5
0.5
0.5
0.5
-
6.0
3.5
4.2
3.8
3.0
20
14.4
8.3
8.5
6.3
5.1
-
1.0
0.5
0.5
0.5
0.5
-
18.0
10.4
10.6
7.9
6.4
-
ns
ns
ns
ns
ns
pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 3.3 V; VI = GND to VCC
[3]
CPD
power dissipation
capacitance
[1] Typical values are measured at nominal VCC and at Tamb = 25 C.
[2] pd is the same as tPLH and tPHL
t
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
7 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
12. Waveforms
V
I
A, B, C input
GND
V
V
M
M
t
t
PLH
PHL
V
OH
V
V
V
M
Y output
M
V
OL
t
t
PLH
PHL
V
OH
Y output
V
M
M
V
OL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Input A, B, C to output Y propagation delay times
Table 10. Measurement points
Supply voltage
VCC
Input
Output
VM
VM
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 VCC
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
1.5 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
1.5 V
0.5 VCC
0.5 VCC
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
8 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 11. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 k
500
500
500
500
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
open
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
9 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
13. Transfer characteristics
Table 12. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
Min Max
Typ[1]
40 C to +125 C Unit
Min Max
VT+
VT
VH
positive-going
threshold voltage Figure 14 and Figure 15
see Figure 12, Figure 13,
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.70
1.11
1.50
2.16
2.61
1.02
1.20
1.60
2.00
2.74
3.33
0.67
1.20
V
V
V
V
V
1.42
1.79
2.52
2.99
1.08
1.47
2.13
2.58
1.60
2.00
2.74
3.33
negative-going
threshold voltage Figure 14 and Figure 15
see Figure 12, Figure 13,
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.30
0.58
0.80
1.21
1.45
0.53
0.77
1.04
1.55
1.86
0.72
1.00
1.30
1.90
2.29
0.30
0.58
0.80
1.21
1.45
0.75
1.03
1.33
1.93
2.32
V
V
V
V
V
hysteresis voltage (VT+ VT);
see Figure 12, Figure 13,
Figure 14 and Figure 15
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
0.30
0.40
0.50
0.71
0.71
0.48
0.64
0.75
0.97
1.13
0.62
0.80
1.00
1.20
1.40
0.23
0.34
0.44
0.65
0.65
0.62
0.80
1.00
1.20
1.40
V
V
V
V
V
[1] Typical values are measured at Tamb = 25 C.
14. Waveforms transfer characteristics
V
T+
V
O
V
I
V
H
V
T−
V
O
V
I
mna208
V
H
V
V
T+
T−
mna207
VT+ and VT limits are at 70 % and 20 %.
Fig 12. Transfer characteristics
Fig 13. Definition of VT+, VT and VH
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
10 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
V
T+
V
I
V
O
V
H
V
T−
V
O
V
I
V
H
mnb155
V
V
T+
T−
001aab684
VT+ and VT limits are at 70 % and 20 %.
Fig 14. Transfer characteristics
Fig 15. Definition of VT+, VT and VH
001aab594
16
I
CC
(mA)
12
8
4
0
0
1
2
3
V (V)
I
Fig 16. Typical 74LVC1G58-Q100 transfer characteristics; VCC = 3.0 V
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
11 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
15. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 17. Package outline SOT363 (SC-88)
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
12 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
Plastic surface-mounted package (TSOP6); 6 leads
SOT457
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
c
1
2
3
L
p
e
b
p
w
M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-11-07
06-03-16
SOT457
SC-74
Fig 18. Package outline SOT457 (TSOP6)
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
13 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
16. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 14. Revision history
Document ID
Release date
20140610
Data sheet status
Change notice
Supersedes
74LVC1G58_Q100 v.1
Product data sheet
-
-
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
14 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
18.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
15 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
16 of 17
74LVC1G58-Q100
NXP Semiconductors
Low-power configurable multiple function gate
20. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 3
Logic configurations . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Transfer characteristics . . . . . . . . . . . . . . . . . 10
Waveforms transfer characteristics. . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
9
10
11
12
13
14
15
16
17
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 June 2014
Document identifier: 74LVC1G58_Q100
相关型号：
©2020 ICPDF网 联系我们和版权申明