74LVC1G66GF [NXP]
Bilateral switch; 双向开关
| 型号： | 74LVC1G66GF |
| 厂家： | 
NXP |
| 描述： | Bilateral switch |
| 文件： | 总22页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G66
Bilateral switch
Rev. 06 — 27 August 2007
Product data sheet
1. General description
The 74LVC1G66 is a low-power, low-voltage Si-gate CMOS device.
The 74LVC1G66 provides one single pole, single-throw analog switch function. It has two
input/output terminals (Yand Z) and an active HIGH enable input pin (E). When E is LOW,
the analog switch is turned off.
Schmitt-trigger action at the enable input makes the circuit tolerant of slower input rise and
fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ Very low ON resistance:
◆ 7.5 Ω (typical) at VCC = 2.7 V
◆ 6.5 Ω (typical) at VCC = 3.3 V
◆ 6 Ω (typical) at VCC = 5 V
■ Switch current capability of 32 mA
■ High noise immunity
■ CMOS low power consumption
■ TTL interface compatibility at 3.3 V
■ Latch-up performance meets requirements of JESD78 Class I
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Enable input accepts voltages up to 5.5 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC1G66
NXP Semiconductors
Bilateral switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G66GW −40 °C to +125 °C
TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G66GV
−40 °C to +125 °C
SC-74A plastic surface-mounted package; 5 leads
SOT753
SOT886
74LVC1G66GM −40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads;
6 terminals; body 1 × 1.45 × 0.5 mm
74LVC1G66GF
−40 °C to +125 °C
XSON6
plastic extremely thin small outline package; no leads;
SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2.
Marking
Type number
74LVC1G66GW
74LVC1G66GV
74LVC1G66GM
74LVC1G66GF
Marking code
VL
V66
VL
VL
5. Functional diagram
1
E
Y
1
X1
2
1
4
#
Z
mna076
001aag487
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Z
Y
E
V
CC
mna658
Fig 3. Logic diagram
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
2 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
6. Pinning information
6.1 Pinning
74LVC1G66
74LVC1G66
Y
Z
1
2
3
6
5
4
V
CC
74LVC1G66
1
2
3
5
4
Y
Z
V
E
Y
Z
1
2
3
6
5
4
V
CC
CC
n.c.
E
n.c.
E
GND
GND
GND
001aag498
001aag499
001aad654
Transparent top view
Transparent top view
Fig 4. Pin configuration SOT353-1
and SOT753
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT353-1/SOT753 SOT886/SOT891
Description
Y
1
2
3
4
-
1
2
3
4
5
6
independent input or output
independent output or input
ground (0 V)
Z
GND
E
enable input (active HIGH)
not connected
n.c.
VCC
5
supply voltage
7. Functional description
Table 4.
Function table[1]
Input E
Switch
L
OFF-state
ON-state
H
[1] H = HIGH voltage level;
L = LOW voltage level
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
3 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−50
-
Max
+6.5
+6.5
-
Unit
V
supply voltage
[1]
[2]
input voltage
V
IIK
input clamping current
switch clamping current
switch voltage
VI < −0.5 V or VI > VCC + 0.5 V
VI < −0.5 V or VI > VCC + 0.5 V
enable and disable mode
mA
mA
V
ISK
±50
VCC + 0.5
±50
100
-
VSW
ISW
−0.5
-
switch current
VSW > −0.5 V or VSW < VCC + 0.5 V
mA
mA
mA
°C
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−100
−65
-
storage temperature
total power dissipation
+150
250
[3]
Tamb = −40 ° C to +125 °C
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
supply voltage
input voltage
1.65
-
-
-
-
-
-
VI
0
5.5
V
[1]
VSW
switch voltage
ambient temperature
0
VCC
+125
20
V
Tamb
−40
°C
[2]
[2]
∆t/∆V
input transition rise and
fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
ns/V
ns/V
10
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Y. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
4 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65VCC
-
-
0.65VCC
-
V
V
V
V
V
V
V
V
1.7
-
-
1.7
-
2.0
-
-
-
2.0
-
-
0.7VCC
-
0.7VCC
VIL
LOW-level
input voltage
-
-
-
-
-
-
0.35VCC
0.7
-
-
-
-
-
0.35VCC
0.7
-
-
-
0.8
0.8
0.3VCC
±5
0.3VCC
[2]
[2]
II
input leakage pin E; VI = 5.5 V or GND;
current
±0.1
±100 µA
VCC = 0 V to 5.5 V
IS(OFF)
OFF-state
leakage
current
VI = VIH or VIL; VCC = 5.5 V;
see Figure 7
-
-
-
-
±0.1
±0.1
0.1
5
±5
±5
-
-
-
-
±200 µA
[2]
[2]
[2]
IS(ON)
ON-state
leakage
current
VI = VIH or VIL; VCC = 5.5 V;
see Figure 8
±200 µA
ICC
supply
current
VI = 5.5 V or GND;
10
200
µA
V
V
SW = GND or VCC; IO = 0 A;
CC = 1.65 V to 5.5 V
∆ICC
additional
supply
current
pin E; VI = VCC − 0.6 V;
500
5000 µA
V
V
SW = GND or VCC; IO = 0 A;
CC = 5.5 V
CI
input
capacitance
-
-
-
2.0
6.5
11
-
-
-
-
-
-
-
-
-
pF
pF
pF
CS(OFF) OFF-state
capacitance
CS(ON)
ON-state
capacitance
[1] All typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC = 3.3 V.
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
5 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
10.1 Test circuits
V
V
CC
CC
E
Y
E
Z
V
V
IH
IL
Z
Y
I
I
I
S
S
S
GND
GND
V
V
V
V
O
I
O
I
001aag488
001aag489
VI = VCC or GND and VO = GND or VCC
.
VI = VCC or GND and VO = open circuit.
Fig 7. Test circuit for measuring OFF-state leakage
current
Fig 8. Test circuit for measuring ON-state leakage
current
10.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak) VI = GND to VCC; see Figure 9
ISW = 4 mA;
-
34.0 130
-
195
Ω
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = GND; see Figure 9
-
-
-
-
12.0
10.4
7.8
30
25
20
15
-
-
-
-
45
38
30
23
Ω
Ω
Ω
Ω
6.2
RON(rail)
ON resistance (rail)
ISW = 4 mA;
-
8.2
18
-
27
Ω
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
VI = VCC; see Figure 9
-
-
-
-
7.1
6.9
6.5
5.8
16
14
12
10
-
-
-
-
24
21
18
15
Ω
Ω
Ω
Ω
ISW = 4 mA;
-
10.4
30
-
45
Ω
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
7.6
7.0
6.1
4.9
20
18
15
10
-
-
-
-
30
27
23
15
Ω
Ω
Ω
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
6 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 8.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
[2]
RON(flat)
ON resistance
(flatness)
VI = GND to VCC
ISW = 4 mA;
-
26.0
-
-
-
Ω
VCC = 1.65 V to 1.95 V
ISW = 8 mA; VCC = 2.3 V to 2.7 V
ISW = 12 mA; VCC = 2.7 V
-
-
-
-
5.0
3.5
2.0
1.5
-
-
-
-
-
-
-
-
-
-
-
-
Ω
Ω
Ω
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] Typical values are measured at Tamb = 25 °C and nominal VCC
.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
10.3 ON resistance test circuit and graphs
mna673
40
R
ON
(Ω)
30
V
SW
(1)
20
10
0
V
CC
E
Y
(2)
(3)
V
IH
Z
(4)
(5)
4
GND
V
I
I
SW
0
1
2
3
5
V (V)
I
001aag490
RON = VSW/ISW
.
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 9. Test circuit for measuring ON resistance
Fig 10. Typical ON resistance as a function of input
voltage; Tamb = 25 °C
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
7 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
001aaa712
001aaa708
55
15
R
ON
R
ON
(Ω)
(Ω)
45
13
35
25
15
5
11
9
(4)
(3)
(2)
(1)
(1)
(2)
(3)
(4)
7
5
0
0.4
0.8
1.2
1.6
2.0
0
0.5
1.0
1.5
2.0
2.5
V (V)
I
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 11. ON resistance as a function of input voltage;
CC = 1.8 V
Fig 12. ON resistance as a function of input voltage;
VCC = 2.5 V
V
001aaa709
001aaa710
13
10
R
(Ω)
ON
R
ON
(Ω)
11
8
6
4
(1)
(1)
(2)
9
7
5
(2)
(3)
(3)
(4)
(4)
0
0.5
1.0
1.5
2.0
2.5 3.0
V (V)
I
0
1
2
3
4
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 13. ON resistance as a function of input voltage;
CC = 2.7 V
Fig 14. ON resistance as a function of input voltage;
VCC = 3.3 V
V
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
8 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
001aaa711
7
6
5
4
3
R
ON
(Ω)
(1)
(2)
(3)
(4)
0
1
2
3
4
5
V (V)
I
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2][3]
tpd
propagation delay Y to Z or Z to Y;
see Figure 16
VCC = 1.65 V to 1.95 V
-
-
-
-
-
0.8
0.4
0.4
0.3
0.2
2.0
1.2
1.0
0.8
0.6
-
-
-
-
-
3.0
2.0
1.5
1.5
1.0
ns
ns
ns
ns
ns
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
E to Y or Z; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[4]
ten
enable time
1.0
1.0
1.0
1.0
1.0
5.3
3.0
2.6
2.5
1.9
12
6.5
6.0
5.0
4.2
1.0
1.0
1.0
1.0
1.0
15.5
8.5
8.0
6.5
5.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
9 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[5]
tdis
disable time
E to Y or Z; see Figure 17
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
1.0
1.0
4.2
2.4
3.6
3.4
2.5
10
6.9
7.5
6.5
5.0
1.0
1.0
1.0
1.0
1.0
13
9.0
9.5
8.5
6.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[6]
CPD
power dissipation CL = 50 pF; fi = 10 MHz;
capacitance
VI = GND to VCC
VCC = 2.5 V
-
-
-
9.8
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 3.3 V
12.0
17.3
VCC = 5.0 V
[1] Typical values are measured at Tamb = 25 °C and nominal VCC
.
[2] tpd is the same as tPLH and tPHL
[3] propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL
[5] tdis is the same as tPLZ and tPHZ
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ{(CL + CS(ON))× VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ{(CL + CS(ON)) × VCC2 × fo} = sum of the outputs.
11.1 Waveforms and test circuit
V
I
V
Y or Z input
M
GND
t
t
PLH
PHL
V
OH
V
M
Z or Y output
V
OL
mna667
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Input (Y or Z) to output (Z or Y) propagation delays
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
10 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
V
I
E
V
M
GND
t
t
PZL
PLZ
V
CC
output
Y or Z
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
Y or Z
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
switch
enabled
switch
enabled
switch
disabled
mna668
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5VCC
0.5VCC
1.5 V
1.5 V
0.5VCC
0.5VCC
0.5VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
V
V
V
V
V
OH − 0.15 V
OH − 0.15 V
OH − 0.3 V
OH − 0.3 V
OH − 0.3 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5VCC
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
11 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 11.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 18. Load circuit for switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
2VCC
2VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
GND
GND
GND
GND
GND
500 Ω
500 Ω
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
4.5 V to 5.5 V
open
6 V
open
2VCC
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic distortion
RL = 10 kΩ; CL = 50 pF; fi = 1 kHz;
see Figure 19
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
0.032
0.008
0.006
0.001
-
-
-
-
%
%
%
%
RL = 10 kΩ; CL = 50 pF; fi = 10 kHz;
see Figure 19
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
0.068
0.009
0.008
0.006
-
-
-
-
%
%
%
%
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
12 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f(−3dB)
−3 dB frequency response RL = 600 Ω; CL = 50 pF;
see Figure 20
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
135
145
150
155
-
-
-
-
MHz
MHz
MHz
MHz
RL = 50 Ω; CL = 5 pF; see Figure 20
VCC = 1.65 V
VCC = 2.3 V
-
-
-
-
> 500
> 500
> 500
> 500
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 3.0 V
VCC = 4.5 V
RL = 50 Ω; CL = 10 pF; see Figure 20
VCC = 1.65 V
-
-
-
-
200
350
410
440
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
αiso
isolation (OFF-state)
RL = 600 Ω; CL = 50 pF; fi = 1 MHz;
see Figure 21
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
−46
−46
−46
−46
-
-
-
-
dB
dB
dB
dB
RL = 50 Ω; CL = 5 pF; fi = 1 MHz;
see Figure 21
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
−37
−37
−37
−37
-
-
-
-
dB
dB
dB
dB
Vct
crosstalk voltage
between digital input and switch;
RL = 600 Ω; CL = 50 pF; fi = 1 MHz;
tr = tf = 2 ns; see Figure 22
VCC = 1.65 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
-
-
-
-
69
-
-
-
-
mV
mV
mV
mV
87
156
302
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
13 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Qinj
charge injection
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω;
fi = 1 MHz; RL = 1 MΩ; see Figure 23
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 5.5 V
-
-
-
-
-
3.3
4.1
5.0
6.4
7.5
-
-
-
-
-
pC
pC
pC
pC
pC
11.3 Test circuits
V
0.5V
CC
CC
E
V
R
L
IH
10 pF
Y/Z
Z/Y
V
O
f
600 Ω
C
L
D
i
001aag492
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
VCC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 19. Test circuit for measuring total harmonic distortion
V
0.5V
CC
CC
E
V
R
L
IH
0.1 pF
Y/Z
Z/Y
V
O
f
50 Ω
C
L
dB
i
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
14 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
0.5V
V
0.5V
CC
CC
CC
E
R
L
V
R
L
IL
0.1 pF
Y/Z
Z/Y
V
O
f
50 Ω
C
L
dB
i
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
V
CC
E
Y/Z
Z/Y
V
O
logic
input
G
R
L
C
L
50 Ω
600 Ω
0.5V
0.5V
001aag494
CC
CC
Fig 22. Test circuit for measuring crosstalk between digital input and switch
V
CC
E
R
gen
Y/Z
Z/Y
V
O
R
1 MΩ
C
L
0.1 nF
G
logic
input
L
V
gen
001aag495
logic
input (E)
off
on
off
V
O
∆V
O
mna675
Qinj = ∆VO × CL.
∆VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
15 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
12. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 24. Package outline SOT353-1 (TSSOP5)
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
16 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig 25. Package outline SOT753 (SC-74A)
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
17 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 26. Package outline SOT886 (XSON6)
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
18 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
(1)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 27. Package outline SOT891 (XSON6)
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
19 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
13. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
TTL
Description
Complementary Metal Oxide Semiconductor
Transistor-Transistor Logic
Human Body Model
HBM
ESD
ElectroStatic Discharge
Machine Model
MM
DUT
Device Under Test
14. Revision history
Table 14. Revision history
Document ID
74LVC1G66_6
Modifications:
Release date
20070827
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC1G66_5
• Section 10 “Static characteristics”:
Changed: Conditions for OFF-state and ON-state leakage current.
20070807 Product data sheet
74LVC1G66_5
Modifications:
-
74LVC1G66_4
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name when appropriate.
• Added type number 74LVC1G66GM (XSON6/SOT886 package)
• Added type number 74LVC1G66GF (XSON6/SOT891 package)
• Section 2 “Features”:
Added: Wide supply voltage range from 1.65 V to 5.5 V
Changed: JESD78 Class II to JESD78 Class I
Added: Enable input accepts voltages up to 5.5 V
• Section 8 “Limiting values”:
Added: Limiting values of switch parameters.
Added: Derating factors of the applicable packages
• Section 9 “Recommended operating conditions”:
Added: Recommended operation conditions of switch parameters.
• Section 10 “Static characteristics”:
Changed: Maximum values of ON resistance (peak) parameters and graphics.
Changed: Conditions for input leakage and supply current.
• Section 11 “Dynamic characteristics”:
Changed: Typical values of the charge injection.
74LVC1G66_4
74LVC1G66_3
74LVC1G66_2
74LVC1G66_1
20040413
20021115
20020529
20011030
Product specification
Product specification
Product specification
Product specification
-
-
-
-
74LVC1G66_3
74LVC1G66_2
74LVC1G66_1
-
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
20 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
15.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC1G66_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 27 August 2007
21 of 22
74LVC1G66
NXP Semiconductors
Bilateral switch
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
10
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 7
10.1
10.2
10.3
11
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms and test circuit . . . . . . . . . . . . . . . 10
Additional dynamic characteristics . . . . . . . . . 12
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.1
11.2
11.3
12
13
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 August 2007
Document identifier: 74LVC1G66_6
相关型号：
74LVC1G66GN
LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, BCC6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, XSON-6
NXP
74LVC1G66GS
LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, BCC6, 1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, XSON-6
NXP
©2020 ICPDF网 联系我们和版权申明