74LVCH16373ADG [NXP]
IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48, Bus Driver/Transceiver;
| 型号： | 74LVCH16373ADG |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48, Bus Driver/Transceiver 锁存器 |
| 文件： | 总10页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVC16373A/74LVCH16373A
16-bit D-type transparent latch with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
1998 Mar 17
Supersedes data of 1997 Aug 22
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
FEATURES
PIN CONFIGURATION
• 5 volt tolerant inputs/outputs for interfacing with 5V logic
48 1LE
1OE
1Q0
1Q1
1
2
3
• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
47
46
45
44
1D0
1D1
GND
1D2
GND
1Q2
4
5
TM
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for minimum
43 1D3
1Q3
6
7
8
9
noise and ground bounce
42
41
40
39
V
CC
V
CC
• Direct interface with TTL levels
1Q4
1Q5
1D4
1D5
GND
• All data inputs have bus hold (74LVCH167373A only)
• High impedance when V = 0
CC
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. One latch enable (LE) input and one output
enable (OE) are provided for each octal. Inputs can be driven from
either 3.3V or 5V devices. In 3-State operation, outputs can handle
5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
33 2D2
32 2D3
The 74LVC(H)16373A consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
31
30
V
CC
V
18
CC
2D4
2D5
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
29
28 GND
27 2D6
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
26
25
2D7
2LE
SW00066
The 74LVCH16373A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t ≤ 2.5ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
Dn to Qn
LE to Qn
C = 50pF
L
3.0
3.4
t
/t
ns
PHL PLH
V
CC
= 3.3V
C
C
Input capacitance
5.0
26
pF
pF
I
Power dissipation capacitance per latch
V
CC
= 3.3V
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW):
PD
D
2
2
P
= C × V
× f + S (C × V
× f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
S (C × V
× f ) = sum of outputs.
L
CC
o
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
VC16373A DL
DWG NUMBER
SOT370-1
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC16373A DL
74LVC16373A DGG
74LVCH16373A DL
74LVCH16373A DGG
VC16373A DGG
VCH16373A DL
VCH16373A DGG
SOT362-1
SOT370-1
SOT362-1
2
1998 Mar 17
853-2027 19112
Philips Semiconductors
Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
PIN DESCRIPTION
LOGIC SYMBOL
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
24
Output enable input
(active LOW)
1
1OE
1Q0 to 1Q7
GND
1OE
2OE
2, 3, 5, 6, 8, 9,
11, 12
47
2
1D0
1Q0
Data inputs/outputs
46
44
1D1
1D2
1Q1
1Q2
3
5
4, 10, 15, 21,
28, 34, 39, 45
Ground (0V)
43
41
1D3
1D4
1Q3
1Q4
6
8
7, 18, 31, 42
V
Positive supply voltage
Data inputs/outputs
CC
13, 14, 16, 17,
19, 20, 22, 23
40
38
37
1D5
1D6
1D7
1Q5
1Q6
1Q7
9
2Q0 to 2Q7
2OE
11
12
Output enable input
(active LOW)
24
25
36
35
2D0
2D1
2Q0
2Q1
13
14
Latch enable input (active
HIGH)
2LE
33
32
2D2
2D3
2Q2
2Q3
16
17
36, 35, 33, 32,
30, 29, 27, 26
2D0 to 2D7
1D0 to 1D7
1LE
Data inputs
Data inputs
30
29
2D4
2D5
2Q4
2Q5
19
20
47, 46, 44, 43,
41, 40, 38, 37
27
26
2D6
2D7
2Q6
2Q7
22
23
Latch enable input (active
HIGH)
48
1LE
48
2LE
25
SW00067
LOGIC DIAGRAM
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH
1
LATCH
9
LE LE
LE LE
1LE
2LE
1OE
2OE
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
SW00068
FUNCTION TABLE (per section of eight bits)
INPUTS
OUTPUTS
Q0 to Q7
INTERNAL
LATCHES
OPERATING MODES
OE
LE
Dn
enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
L
L
L
L
l
h
L
H
L
H
latch and read register
H
H
L
L
l
h
L
H
Z
Z
latch register and disable outputs
H
= HIGH voltage level
h
L
l
= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
= LOW voltage level
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X
= don’t care
Z
= high impedance OFF-state
3
1998 Mar 17
Philips Semiconductors
Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
LOGIC SYMBOL (IEEE/IEC)
BUS HOLD CIRCUIT
V
CC
1
1EN
C3
1OE
48
25
24
1LE
2OE
2EN
C4
2LE
47
46
2
3
5
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
3D
1
Data Input
To internal circuit
44
43
41
6
8
9
40
38
11
12
37
SW00044
36
35
13
4D
2
14
16
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
33
32
17
19
30
29
20
22
23
27
26
SW00069
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
2.7
1.2
0
MAX
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
3.6
V
CC
V
3.6
V
I
5.5
V
V
DC input voltage range; output HIGH or LOW state
DC output voltage range; output 3-State
Operating free-air temperature range
0
V
CC
V
O
0
5.5
T
amb
–40
+85
°C
V
CC
V
CC
= 1.2 to 2.7V
= 2.7 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
4
1998 Mar 17
Philips Semiconductors
Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +6.5
–50
UNIT
V
V
CC
I
IK
DC input diode current
V t 0
mA
V
I
V
I
DC input voltage
Note 2
–0.5 to +6.5
"50
I
DC output diode current
V
O
uV or V t 0
mA
OK
CC
O
DC output voltage; output HIGH or LOW state
DC output voltage; output 3-State
DC output source or sink current
Note 2
Note 2
–0.5 to V +0.5
CC
V
V
O
–0.5 to 6.5
"50
I
O
V
O
= 0 to V
CC
mA
mA
°C
I
, I
DC V or GND current
"100
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
– plastic mini-pack (SO)
P
TOT
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
– plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
V
V
V
= 1.2V
V
CC
CC
CC
CC
CC
V
HIGH level Input voltage
LOW level Input voltage
V
IH
= 2.7 to 3.6V
= 1.2V
2.0
GND
0.8
V
V
V
IL
= 2.7 to 3.6V
V
= 2.7V; V = V or V ; I = –12mA
V
V
V
V
*0.5
CC
CC
CC
CC
CC
CC
I
IH
IL
O
CC
CC
CC
CC
V
V
V
V
V
V
V
V
V
V
= 3.0V; V = V or V ; I = –100µA
*0.2
*0.6
*0.8
V
CC
I
IH
IL
O
V
OH
HIGH level output voltage
LOW level output voltage
= 3.0V; V = V or V I
= –18mA
I = –24mA
V
V
I
IH
IL; O
= 3.0V; V = V or V
IL; O
I
IH
= 2.7V; V = V or V ; I = 12mA
0.40
0.20
0.55
"5
I
IH
IL
O
= 3.0V; V = V or V ; I = 100µA
V
OL
I
IH
IL
O
O
= 3.0V; V = V or V
I
= 24mA
CC
CC
I
IH
IL;
6
I
Input leakage current
= 3.6V; V = 5.5V or GND
µA
µA
µA
µA
"0.1
I
I
I
3-State output OFF-state current
Power off leakage supply
Quiescent supply current
= 3.6V; V = V or V ; V = 5.5V or GND
0.1
"5
OZ
CC
CC
CC
I
IH
IL
O
I
off
= 0.0V; V or V = 5.5V
I O
"10
20
I
= 3.6V; V = V or GND; I = 0
0.1
5
CC
I
CC
O
Additional quiescent supply
current per input pin
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V; I = 0
500
µA
I
CC
O
5
1998 Mar 17
Philips Semiconductors
Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
75
TYP
MAX
2, 3, 4
I
Bus hold LOW sustaining current
Bus hold HIGH sustaining current
Bus hold LOW overdrive current
Bus hold HIGH overdrive current
V
CC
V
CC
V
CC
V
CC
= 3.0V; V = 0.8V
µA
µA
µA
µA
BHL
I
2, 3, 4
I
= 3.0V; V = 2.0V
–75
500
–500
BHH
I
2, 3, 5
I
= 3.6V
BHLO
BHHO
2, 3, 5
I
= 3.6V
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. Valid for data inputs of bus hold parts (LVCH16-A) only.
3. For data inputs only, control inputs do not have a bus hold circuit.
4. The specified sustaining current at the data input holds the input below the specified V level.
I
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
6. For bus hold parts, the bus hold circuit is switched off when V exceeds V allowing 5.5V on the input terminal.
i
CC
AC CHARACTERISTICS
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
V
CC
= 1.2V
UNIT
1
MIN
TYP
MAX
MIN
MAX
TYP
t
t
Propagation delay
Dn to Qn
PHL
PLH
1, 5
2, 5
4, 5
4, 5
1.5
1.5
1.5
1.5
3.0
4.7
4.8
5.5
5.4
1.5
5.7
5.8
6.5
6.4
12
14
18
11
ns
ns
ns
ns
t
t
Propagation delay
LE to Qn
PHL
PLH
3.4
3.5
3.9
1.5
1.5
1.5
t
3-State output enable time
OE to Qn
PZH
t
PZL
t
3-State output disable time
OE to Qn
PHZ
t
PLZ
t
LE pulse width HIGH
Set-up time Dn to LE
Hold time Dn to LE
2
3
3
3
2.0
–0.1
0.1
–
–
–
3
–
–
–
–
–
–
ns
ns
ns
W
t
su
1.7
1.2
1.7
1.2
t
h
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
AC WAVEFORMS
V
V
V
V
= 1.5V at V w 2.7V; V = 0.5 V at V t 2.7V.
M
CC M CC CC
and V are the typical output voltage drop that occur with the output load.
OL
OH
= V + 0.3V at V w 2.7V; V = V + 0.1 V at V t2.7V
X
Y
OL
CC
X
OL
CC
CC
= V –0.3V at V w2.7V; V = V – 0.1 V at V t2.7V
OH
CC
Y
OH
CC
CC
V
I
V
I
LE INPUT
GND
Dn INPUT
GND
V
V
V
t
V
V
M
t
M
t
M
M
M
t
w
t
PHL
PLH
PHL
PLH
V
OH
V
OH
V
V
Qn OUTPUT
M
M
Qn OUTPUT
V
M
V
OL
V
SW00071
OL
SW00070
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Qn) propagation delays
Waveform 1. Input (Dn) to output (Qn) propagation delays
6
1998 Mar 17
Philips Semiconductors
Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
AC WAVEFORMS (Continued)
TEST CIRCUIT
V
= 1.5V at V w 2.7V; V = 0.5 V at V t 2.7V.
M
CC M CC CC
S
1
V
OL
and V are the typical output voltage drop that occur with the
OH
V
CC
2<V
CC
output load.
Open
GND
V
X
V
Y
= V + 0.3V at V w 2.7V; V = V + 0.1 V at V t2.7V
OL CC X OL CC CC
= V –0.3V at V w2.7V; V = V – 0.1 V at V t2.7V
OH
CC
Y
OH
CC
CC
R =500 Ω
L
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
V
I
Dn
INPUT
R =500 Ω
L
R
C
V
T
M
L
GND
th
th
Test Circuit for 3-State Outputs
SWITCH POSITION
t
t
SU
SU
V
I
LE
INPUT
V
M
V
V
IN
TEST
SWITCH
Open
CC
GND
t 2.7V
2.7 – 3.6V 2.7V
V
CC
t
/t
PLH PHL
NOTE: The shaded areas indicate when the input is permitted to change
t
/t
2<V
CC
PLZ PZL
for predictable output performance.
t
/t
GND
PHZ PZH
SW00073
DEFINITIONS
R = Load resistor
Waveform 3. Data set-up and hold times for the Dn input to the
LE input
L
C = Load capacitance includes jig and probe capacitance
L
V
I
R = Termination resistance should be equal to Z
T
OUT
of pulse generators.
V
OE INPUT
GND
V
M
M
SW00047
Waveform 5. Load circuitry for switching times
t
t
PZL
PLZ
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
OUTPUT
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
SW00072
Waveform 4. 3-State enable and disable times
7
1998 Mar 17
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
74LVC16373A/
74LVCH16373A
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
8
1998 Mar 17
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
74LVC16373A/
74LVCH16373A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
9
1998 Mar 17
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 5 Volt Tolerant
inputs/outputs (3-State)
74LVC16373A/
74LVCH16373A
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04533
Document order number:
Philips
Semiconductors
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74LVCH16373ADGG-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
NEXPERIA
74LVCH16373ADGG-T
IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, SOT-362-1, TSSOP2-48, Bus Driver/Transceiver
NXP
74LVCH16373ADGG:11
74LVC(H)16373A - 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state TSSOP 48-Pin
NXP
74LVCH16373ADGG:51
74LVC(H)16373A - 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state TSSOP 48-Pin
NXP
74LVCH16373ADGV
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction
NEXPERIA
74LVCH16373ADGV-Q100
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
NEXPERIA
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