74LVCH32374AEC,551 [NXP]
74LVCH32374A - 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin;
| 型号： | 74LVCH32374AEC,551 |
| 厂家： | 
NXP |
| 描述： | 74LVCH32374A - 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin 驱动 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVCH32374A
32-bit edge-triggered D-type
flip-flop with 5 V tolerant
inputs/outputs; 3-state
Product specification
2004 May 24
Supersedes data of 1999 Nov 24
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
FEATURES
advanced CMOS compatible TTL families.
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
The inputs can be driven from either 3.3 V or 5 V devices.
In 3-state operation, the outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 V or 5 V environment.
• MULTIBYTE flow-trough standard pin-out architecture
The 74LVCH32374A is a 32-bit edge-triggered flip-flop
featuring separate D-type inputs for each flip-flop and
3-state outputs for bus oriented applications. The
74LVCH32374A consists of 4 sections of 8 edge-triggered
flip-flops. A clock (pin nCP) input and an output enable
input (pin nOE) are provided per 8-bit section.
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bushold
• Complies with JEDEC standard JESD8-B/JESD36
• ESD protection:
The flip-flops will store the state of their individual D-inputs
that meet the set-up and hold time requirements on the
LOW-to-HIGH nCP transition.
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C
When pin nOE is LOW, the contents of the flip-flops are
available at the outputs. When pin nOE is HIGH, the
outputs go to the high-impedance OFF-state. Operation of
pin nOE does not affect the state of the flip-flops.
• Packaged in plastic fine-pitch ball grid array package.
The 74LVCH32374A bushold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
DESCRIPTION
The 74LVCH32374A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
fmax
propagation delay nCP to nQn
CL = 50 pF; VCC = 3.3 V
3.4
3.5
3.9
150
5.0
ns
ns
ns
3-state output enable time nOE to nQn CL = 50 pF; VCC = 3.3 V
3-state output disable time nOE to nQn CL = 50 pF; VCC = 3.3 V
maximum clock frequency
input capacitance
CL = 50 pF; VCC = 3.3 V
MHz
pF
CI
CPD
power dissipation per flip-flop
VCC = 3.3 V; notes 1 and 2
outputs enabled
19
12
pF
pF
outputs disabled
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2004 May 24
2
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
BALLS
PACKAGE MATERIAL
LFBGA96 plastic
CODE
74LVCH32374AEC
−40 °C to +85 °C
96
SOT536-1
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nQn
INTERNAL
FLIP-FLOP
OPERATING MODE
nOE
nCP
nDn
Load and read register
L
L
↑
↑
↑
↑
l
L
H
L
L
H
Z
Z
h
l
Load register and disable
outputs
H
H
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.
PINNING
BALL
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
SYMBOL
1D5
DESCRIPTION
BALL
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
SYMBOL
1Q1
1Q0
1OE
1CP
1D0
DESCRIPTION
flip-flop output
data input
1Q7
1Q6
GND
GND
1D6
flip-flop output
flip-flop output
ground (0 V)
ground (0 V)
data input
flip-flop output
output enable input (active LOW)
clock input
data input
1D1
data input
1D7
data input
1Q3
1Q2
GND
GND
1D2
flip-flop output
flip-flop output
ground (0 V)
ground (0 V)
data input
2Q1
2Q0
GND
GND
2D0
flip-flop output
flip-flop output
ground (0 V)
ground (0 V)
data input
1D3
data input
2D1
data input
1Q5
1Q4
VCC
flip-flop output
flip-flop output
supply voltage
supply voltage
data input
2Q3
2Q2
VCC
flip-flop output
flip-flop output
supply voltage
supply voltage
data input
F2
F3
VCC
F4
VCC
1D4
F5
2D2
2004 May 24
3
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
BALL
SYMBOL
DESCRIPTION
data input
BALL
SYMBOL
DESCRIPTION
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
J1
2D3
2Q5
2Q4
GND
GND
2D4
2D5
2Q6
2Q7
2OE
2CP
2D7
2D6
3Q1
3Q0
3OE
3CP
3D0
3D1
3Q3
3Q2
GND
GND
3D2
3D3
3Q5
3Q4
VCC
VCC
3D4
3D5
M1
M2
M3
M4
M5
M6
N1
N2
N3
N4
N5
N6
P1
P2
P3
P4
P5
P6
R1
R2
R3
R4
R5
R6
T1
T2
T3
T4
T5
T6
3Q7
3Q6
GND
GND
3D6
3D7
4Q1
4Q0
GND
GND
4D0
4D1
4Q3
4Q2
VCC
flip-flop output
flip-flop output
flip-flop output
ground (0 V)
ground (0 V)
data input
flip-flop output
ground (0 V)
ground (0 V)
data input
data input
data input
flip-flop output
flip-flop output
ground (0 V)
ground (0 V)
data input
flip-flop output
flip-flop output
output enable input (active LOW)
clock input
data input
data input
data input
flip-flop output
flip-flop output
supply voltage
supply voltage
data input
flip-flop output
flip-flop output
output enable input (active LOW)
clock input
J2
J3
VCC
J4
4D2
4D3
4Q5
4Q4
GND
GND
4D4
4D5
4Q6
4Q7
4OE
4CP
4D7
4D6
J5
data input
data input
J6
data input
flip-flop output
flip-flop output
ground (0 V)
ground (0 V)
data input
K1
K2
K3
K4
K5
K6
L1
L2
L3
L4
L5
L6
flip-flop output
flip-flop output
ground (0 V)
ground (0 V)
data input
data input
data input
data input
flip-flop output
flip-flop output
supply voltage
supply voltage
data input
clock input
output enable input (active LOW)
clock input
data input
data input
data input
2004 May 24
4
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
32374A
T
P
M
K
H
F
R
N
L
J
G
E
C
A
D
B
ball A1
index area
1 2 3 4 5 6
001aab000
Fig.1 Ball configuration.
1D0
2D0
1Q0
2Q0
D
Q
D
Q
CP
CP
FF 1
FF 9
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
3D0
4D0
3Q0
4Q0
D
Q
D
Q
CP
CP
FF 17
FF 25
3CP
3OE
4CP
4OE
to 7 other channels
to 7 other channels
coa012
Fig.2 Logic symbol.
5
2004 May 24
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
V
handbook, halfpage
CC
data
input
to internal circuit
MNA473
Fig.3 Bushold circuit.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
2.7
MAX.
3.6
UNIT
VCC
for maximum speed performance
for low voltage applications
V
1.2
0
3.6
5.5
VCC
5.5
+85
20
V
VI
input voltage
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
V
0
V
Tamb
tr, tf
ambient temperature
in free air
−40
0
°C
input rise and fall times
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V);
note 1.
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0 V
note 2
−
−50
mA
V
VI
−0.5
−
+6.5
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0 V
output HIGH or LOW state; note 2
output 3-state; note 2
VO = 0 V to VCC
±50
mA
V
−0.5
−0.5
−
VCC + 0.5
+6.5
V
IO
output source or sink current
±50
mA
mA
°C
mW
ICC, IGND VCC or GND current
note 1
−
±200
+150
1000
Tstg
Ptot
storage temperature
power dissipation
−65
−
Tamb = −40 °C to +85 °C; note 3
Notes
1. All supply and ground pins connected externally to one voltage source.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
2004 May 24
6
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C; note 1
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
1.2
VCC
−
−
−
−
−
V
V
V
V
2.7 to 3.6 2.0
−
1.2
−
−
GND
0.8
2.7 to 3.6
VOH
VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −18 mA
IO = −24 mA
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
2.7 to 3.6
2.7
VCC − 0.2
VCC − 0.5
VCC − 0.6
VCC − 0.8
VCC
−
−
−
−
−
V
V
V
V
3.0
−
3.0
−
VOL
LOW-level output voltage
input leakage current
2.7 to 3.6
2.7
−
−
−
−
GND
−
0.20
0.40
0.55
±5
V
V
IO = 24 mA
3.0
−
V
ILI
VI = 5.5 V or GND; 3.6
note 2
±0.1
µA
IOZ
3-state output OFF-state current VI = VIH or VIL;
3.6
−
±0.1
±5
µA
VO = 5.5 V or GND;
note 2
Ioff
power-off leakage supply current VI or VO = 5.5 V
0.0
3.6
−
−
±0.1
±10
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0 A
0.1
40
∆ICC
IBHL
IBHH
additional quiescent supply
current per input pin
VI = VCC − 0.6 V;
IO = 0 A
2.7 to 3.6
3.0
−
5
−
−
500
−
µA
µA
µA
bushold LOW sustaining current VI = 0.8 V;
notes 3 and 4
75
bushold HIGH sustaining current VI = 2.0 V;
notes 3 and 4
3.0
−75
−
IBHLO
IBHHO
bushold LOW overdrive current
notes 3 and 5
3.6
3.6
500
−
−
−
−
µA
µA
bushold HIGH overdrive current notes 3 and 5
−500
Notes
1. All typical values are measured at Tamb = 25 °C.
2. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
3. For data inputs only, control inputs do not have a bushold circuit.
4. The specified sustaining current at the data inputs holds the input below the specified VI level.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2004 May 24
7
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 °C to +85 °C; note1
tPHL/tPLH propagation delay
nCP to nQn
see Figs. 4 and 7 1.2
2.7
−
14
−
ns
1.5
1.5
−
−
6.0
5.4
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
3.0 to 3.6
3.4(2)
tPZH/tPZL
3-state output enable time see Figs. 6 and 7 1.2
20
nOE to nQn
2.7
1.5
1.0
−
−
6.0
5.2
−
3.0 to 3.6
3.5(2)
tPHZ/tPLZ
3-state output disable time see Figs. 6 and 7 1.2
12
nOE to nQn
2.7
1.5
1.5
−
−
5.1
4.9
−
3.0 to 3.6
1.2
3.9(2)
tW
tsu
th
nCP pulse width HIGH
set-up time nDn to nCP
hold time nDn to nCP
skew
see Fig.4
see Fig.5
see Fig.5
−
2.7
3.0
3.0
−
−
−
3.0 to 3.6
1.2
1.5(2)
−
−
−
2.7
1.9
1.9
−
−
−
3.0 to 3.6
1.2
0.3(2)
−
−
−
2.7
1.1
1.5
−
−
−
3.0 to 3.6
3.0 to 3.6
2.7
−0.3(2)
−
tsk(0)
fmax
−
1.0
−
maximum clock pulse
frequency
see Fig.4
80
100
−
3.0 to 3.6
150(2)
−
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V.
2004 May 24
8
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
AC WAVEFORMS
1/f
max
V
I
nCP input
V
t
V
M
M
GND
t
W
t
PHL
PLH
V
OH
V
M
nQn output
001aaa256
V
OL
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock frequency.
V
I
V
M
nCP input
GND
t
t
su
su
t
t
h
h
V
I
V
M
nDn input
GND
V
OH
V
M
nQn output
V
OL
001aaa257
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Set-up and hold times for inputs (nDn) to inputs (nCP).
9
2004 May 24
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA478
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 V at VCC < 2.7 V.
VX = VOL + 0.1 V at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 3-state output enable and disable times.
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
L
R
L
R
T
mna616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
CL
RL
1.2 V
2.7 V
VCC
50 pF
50 pF
50 pF
500 Ω(1) open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
2.7 V
2.7 V
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
10
2004 May 24
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
PACKAGE OUTLINE
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2
e
y
y
v
M
M
C
C
A B
C
1
e
w
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2
e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
2004 May 24
11
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop
with 5 V tolerant inputs/outputs; 3-state
74LVCH32374A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 May 24
12
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/02/pp13
Date of release: 2004 May 24
Document order number: 9397 750 13228
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