933372770653 [NXP]
IC 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDSO14, PLASTIC, SOT-108-1, SO-14, Counter;
| 型号： | 933372770653 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDSO14, PLASTIC, SOT-108-1, SO-14, Counter 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总5页 (文件大小：41K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4024B
MSI
7-stage binary counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4024B
MSI
7-stage binary counter
DESCRIPTION
The HEF4024B is a 7-stage binary ripple counter with a
clock input (CP), and overriding asynchronous master
reset input (MR) and seven fully buffered parallel outputs
(O0 to O6). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of CP. Each
counter stage is a static toggle flip-flop.
Fig.1 Functional diagram.
PINNING
CP
clock input (HIGH to LOW triggered)
master reset input
MR
O0 to O6
buffered parallel outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4024B are:
• Frequency dividers
• Time delay circuits
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
HEF4024BP(N):
HEF4024BD(F):
HEF4024BT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
January 1995
2
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4024B
MSI
7-stage binary counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
VDD
V
TYPICAL
EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → O0
HIGH to LOW
5
100
40
25
105
45
30
60
25
20
50
20
15
120
45
30
60
30
20
60
30
20
30
15
10
40
20
15
10
5
200
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
73 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
33 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
23 ns + (0,55 ns/pF) CL
9 ns + (0,23 ns/pF) CL
7 ns + (0,16 ns/pF) CL
93 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
tPLH
tPHL
tPLH
tPHL
tTHL
tTLH
50
210
85
LOW to HIGH
10
15
5
60
On → On + 1
120
50
HIGH to LOW
10
15
5
40
100
40
LOW to HIGH
10
15
5
30
MR → On
240
90
HIGH to LOW
10
15
5
60
Output transition times
HIGH to LOW
120
60
10
15
5
40
120
60
LOW to HIGH
10
15
5
40
Minimum clock
60
pulse width; HIGH
10
15
5
tWCPH
tWMRH
tRMR
30
20
80
35
25
20
15
15
5
Minimum MR
pulse width; HIGH
10
15
5
Recovery time
for MR
10
15
5
5
Maximum clock
pulse frequency
10
25
35
10
15
fmax
13
18
January 1995
4
Philips Semiconductors
Product specification
HEF4024B
MSI
7-stage binary counter
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
500 fi + ∑ (foCL) × VDD
where
2
10
15
2100 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
2
5200 fi + ∑ (foCL) × VDD
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths
and recovery time for MR.
January 1995
5
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