933794820602 [NXP]
IC F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, 0.300 INCH, PLASTIC, SOT-38-4, DIP-16, Counter;
| 型号： | 933794820602 |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, 0.300 INCH, PLASTIC, SOT-38-4, DIP-16, Counter 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F193
Up/down binary counter with separate
up/down clocks
Product specification
IC15 Data Handbook
1995 Jul 17
Philips
Semiconductors
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
Multistage counters will not be fully synchronous since there is a
two-gate delay time difference added for each stage that is added.
FEATURES
• Synchronous reversible 4-bit counting
The counter may be preset by the asynchronous parallel load
capability of the circuit. Information present on the parallel Data
inputs (D0 - D3) is loaded into the counter and appears on the
outputs regardless of the conditions of the clock inputs when the
Parallel Load (PL) input is Low. A High level on the Master Reset
(MR) input will disable the parallel load gates, override both clock
inputs, and set all Q outputs Low. If one of the clock inputs is Low
during and after a reset or load operation, the next Low-to-High
transition of the clock will be interpreted as a legitimate signal and
will be counted.
• Asynchronous parallel load capability
• Asynchronous reset (clear)
• Cascadable without external logic
DESCRIPTION
The 74F193 is a 4-bit synchronous up/down counter in the binary
mode. Separate up/down clocks, CP and CP respectively,
U
D
simplify operation. The outputs change state synchronously with the
Low-to-High transition of either clock input. If the CP clock is
U
pulsed while CP is held High, the device will count up. If CP clock
TYPICAL
D
D
SUPPLY CURRENT
(TOTAL)
is pulsed while CP is held High, the device will count down. The
TYPE
TYPICAL f
MAX
U
device can be cleared at any time by the asynchronous reset pin. It
may also be loaded in parallel by activating the asynchronous
parallel load pin.
74F193
125MHz
32mA
Inside the device are four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous reset,
asynchronous preset, load, and synchronous count up and count
down functions.
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
V
DESCRIPTION
PKG DWG #
CC
T
amb
= 0°C to +70°C
Each flip-flop contains JK feedback from slave to master, such that a
16-pin plastic DIP
16-pin plastic SO
N74F193N
SOT38-4
Low-to-High transition on the CP input will decrease the count by
D
N74F193D
SOT109-1
one, while a similar transition on the CP input will advance the
U
count by one.
PIN CONFIGURATION
One clock should be held High while counting with the other,
because the circuit will either count by twos or not at all, depending
on the state of the first JK flip-flop, which cannot toggle as long as
either clock input is Low. Applications requiring reversible operation
must make the reversing decision while the activating clock is High
to avoid erroneous counts.
D1
Q1
Q0
1
2
3
4
5
16
V
CC
15 D0
14 MR
The Terminal Count Up (TC ) and Terminal Count Down (TC )
U
D
13
12
CP
TC
TC
D
U
D
U
outputs are normally High. When the circuit has reached the
CP
maximum count state of 15, the next High-to-Low transition of CP
U
will cause TC to go Low. TC will stay Low until CP goes High
again, duplicating the count up clock, although delayed by two gate
U
U
U
Q2
Q3
6
7
8
11 PL
10 D2
delays. Likewise, the TC output will go Low when the circuit is in
D
the zero state and the CP goes Low. The TC outputs can be used
GND
9
D3
D
as the clock input signals to the next higher order circuit in a
multistage counter, since they duplicate the clock waveforms.
SF00745
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
D0 - D3
DESCRIPTION
Data inputs
1.0/1.0
1.0/3.0
1.0/3.0
1.0/1.0
1.0/1.0
50/33
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
CP
CP
PL
Count up clock input (active rising edge)
Count down clock input (active rising edge)
Asynchronous parallel load control input (active Low)
Asynchronous master reset input
U
D
MR
Q0 - Q3
Flip-flop outputs
TC
Terminal count up (carry) output (active Low)
Terminal count down (borrow) output (active Low)
50/33
U
TC
50/33
D
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
2
853-0353 15459
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
11
5
15
1
10
9
C3
2+
G1
CTR DIV 16
12
13
1CT=15
2CT=0
D0 D1 D2 D3
4
1–
11
PL
CP
CP
12
13
TC
G2
R
U
D
5
U
D
14
4
TC
15
3
14
MR
3D
[1]
[2]
[4]
[8]
Q0 Q1 Q2 Q3
1
2
6
10
7
9
3
2
6
7
V
= Pin 16
CC
GND = Pin 8
SF00746
SF00747
STATE DIAGRAM
0
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
COUNT UP
COUNT DOWN
.
.
.
.
.
.
.
TC = Q0 Q1 Q2 Q3 CP
U
U
.
TC = Q0 Q1 Q2 Q3 CP
D
D
Logic Equations for Terminal Count
SF00748
3
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
LOGIC DIAGRAM
D0
D1
D2
10
D3
15
1
9
11
PL
12
TC
TC
U
13
D
5
CP
U
D
4
CP
J
K
J
J
K
K
CP
CP
CP
J
CP
R
S
R
S
R
S
R
S
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
14
MR
3
2
6
7
V
= Pin 16
CC
Q0
Q1
Q1
Q1
GND = Pin 8
SF00749
FUNCTION TABLE
INPUTS
CP D0
OUTPUTS
OPERATING
MODE
MR
PL
CP
D1
D2
D3
Q0
Q1
Q2
Q3
TC
TC
D
U
D
U
H
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
H
Reset (clear)
L
L
L
L
L
L
L
L
X
X
L
L
H
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
H
L
L
H
H
H
Parallel load
H
H
1
L
L
H
H
↑
H
X
X
X
X
X
X
X
X
Count up
Count down
NOTES:
TC =CP at terminal count up (HHHH)
H
H
Count up
2
H
↑
H
H
Count down
H
L
X
↑
= High voltage level
= Low voltage level
= Don’t care
U
U
TC =CP at terminal count down (LLLL)
D
D
= Low-to-High clock transition
4
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
V
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5.0
CC
V
IN
I
IN
mA
V
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
–0.5 to +V
40
OUT
OUT
CC
I
mA
°
T
amb
0 to +70
C
°
T
stg
–65 to +150
C
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
CC
V
IH
V
IL
Supply voltage
5.0
5.5
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
IK
High-level output current
Low-level output current
Operating free-air temperature range
OH
OL
20
°
T
amb
0
+70
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
NO TAG
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
TYP
NO TAG
MIN
2.5
MAX
"10%V
V
V
V
V
V
CC
V
= MIN, V = MAX,
IL
CC
V
High-level output voltage
OH
I
= MAX, V = MIN
OH
IH
"5%V
2.7
3.4
0.35
0.35
–0.73
CC
"10%V
"5%V
0.50
0.50
–1.2
CC
V
CC
= MIN, V = MAX,
IL
V
V
Low-level output voltage
Input clamp voltage
OL
I
OL
= MAX, V = MIN
IH
CC
V
CC
V
CC
V
CC
= MIN, I = I
I IK
IK
Input current at maximum
input voltage
I
I
= MAX, V = 7.0V
100
µA
I
I
I
High-level input current
= MAX, V = 2.7V
20
–1.8
–0.6
–150
50
µA
mA
mA
mA
mA
IH
I
CP , CP
IL
U
D
Low-level input
current
V
CC
= MAX, V = 0.5V
I
Others
NO TAG
I
I
Short-circuit output current
V
V
= MAX
= MAX
–60
OS
CC
4
Supply current (total)
32
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Measure I with parallel load and Master reset inputs grounded, all other inputs at 4.5V and all outputs open.
CC
5
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
amb
CC
amb
CC
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Propagation delay
Waveform 1
Waveform 2
100
125
90
MHz
MAX
t
t
2.5
3.0
5.5
5.0
8.5
8.0
2.5
3.0
9.0
9.0
ns
ns
PLH
PHL
CP or CP to TC or TC
U
D
U
D
t
t
Propagation delay
CP or CP to Qn
2.5
5.0
5.5
8.5
8.5
12.0
2.5
5.0
9.0
13.0
ns
ns
PLH
PHL
Waveform 1
Waveform 4
Waveform 3
Waveform 5
Waveform 5
Waveform 5
Waveform 3
Waveform 4
U
D
t
t
Propagation delay
D to Qn
n
2.0
6.0
4.0
9.5
7.0
13.5
1.5
6.0
8.0
15.0
ns
ns
PLH
PHL
t
t
Propagation delay
PL to Qn
4.5
5.5
6.5
8.5
10.0
12.0
4.0
5.0
11.0
13.0
ns
ns
PLH
PHL
Propagation delay
MR to Qn
t
t
t
5.0
6.0
5.0
7.5
8.5
7.5
11.0
12.0
11.0
5.0
5.5
5.0
12.0
13.0
12.0
ns
ns
ns
PHL
PLH
PHL
Propagation delay
MR to TC
U
Propagation delay
MR to TC
D
t
t
Propagation delay
PL to TC or TC
6.0
6.0
9.5
9.0
13.5
12.0
6.0
6.0
15.0
13.0
ns
ns
PLH
PHL
U
D
t
t
Propagation delay
Dn to TC or TC
5.5
4.5
9.0
8.5
13.0
12.5
5.0
4.5
14.0
13.5
ns
ns
PLH
PHL
U
D
AC SETUP REQUIREMENTS
LIMITS
T
V
= +25°C
= +5.0V
T
V
= 0°C to +70°C
= +5.0V ± 10%
CC
amb
CC
amb
SYMBOL PARAMETER
TEST CONDITIONS
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
Dn to PL
4.5
4.5
5.0
5.0
ns
ns
s
Waveform 6
Waveform 6
Waveform 3
Waveform 1
Waveform 1
Waveform 5
Waveform 3
Waveform 5
t (H)
Hold time, High or Low
Dn to PL
2.0
2.0
2.0
2.0
ns
ns
h
t (L)
h
PL Pulse width
Low
t (L)
w
6.0
6.0
ns
t (H)
CP or CP Pulse width
3.5
5.0
3.5
5.0
ns
ns
w
U
D
t (L)
w
High or Low
CP or CP Pulse width
U
D
t (L)
w
10.0
6.0
6.0
4.0
10.0
6.0
6.0
4.0
ns
ns
ns
ns
Low (Change of direction)
MR Pulse width
High
t (H)
w
Recovery time,
t
rec
rec
PL to CP or CP
U
D
Recovery time
t
MR to CP or CP
U
D
6
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
AC WAVEFORMS
For all waveforms Vm = 1.5V
1/f
MAX
CP , CP
U D
t (L)
W
V
V
M
M
CP , CP
U
V
V
M
D
M
t (H)
W
t
t
PLH
PHL
t
t
PLH
PHL
TC , TC
U
D
V
V
M
M
Qn
V
V
M
M
SF00753
SF00750
Waveform 2. Propagation Delay, Clock to Terminal Count
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width and Maximum Clock Frequency
Dn
V
V
M
M
t (L)
W
t
t
PLH
PHL
PL
V
V
V
V
M
M
M
M
Qn TC , TC
V
V
V
V
,
U
D
M
M
M
M
t
rec
t
t
PHL
PLH
t
t
PHL
PLH
CP , CP
U
V
D
M
Qn TC , TC
,
U
D
SF00754
Waveform 4. Propagation Delay, Data to Flip-Flop Outputs,
Terminal Count Up and Down Outputs
TC , TC , Qn
V
V
M
U
D
M
SF00751
Waveform 3. Parallel Pulse Width,
Parallel Load to Output Delays, and Parallel Load
to Clock Recovery Time
Dn
V
V
M
M
t (H)
S
t (L)
S
t (H)
h
t (L)
h
V
V
M
M
MR
PL
V
M
t (H)
W
t
rec
The shaded areas indicate when the input is permitted
to change for predictable output performance.
SF00755
CP , CP
U
D
V
M
Waveform 6. Data Setup and Hold Times
t
PLH
V
V
M
M
TC
U
t
PHL
Qn, TC
D
SF00752
Waveform 5. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
7
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
Timing Diagram (Typical clear, load, and count sequence)
1
MR
PL
CLEAR
LOAD
D0
D1
D2
D3
DATA
2
CP
COUNT UP
U
2
CP
COUNT DOWN
D
Q0
Q1
Q2
Q3
OUTPUTS
TC
U
D
TC
0
13
14 15
0
1
2
1
0
15 14 13
SEQUENCE
COUNT UP
COUNT DOWN
CLEAR PRESET
NOTES:
1. Clear overrides load, data, and count inputs.
2. When counting up, count-down input must be High; when counting down, count-up input must be High.
SF00756
Binary Counter
TEST CIRCUIT AND WAVEFORMS
t
AMP (V)
90%
V
w
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
t )
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00006
8
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
9
1995 Juk 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
10
1995 Juk 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
NOTES
11
1995 Juk 17
Philips Semiconductors
Product specification
Up/down binary counter with separate up/down clocks
74F193
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05094
Document order number:
Philips
Semiconductors
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NXP
933794980602
IC F/FAST SERIES, 8-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP20, 0.300 INCH, PLASTIC, SOT-146-1, DIP-20, Arithmetic Circuit
NXP
933795000602
IC F/FAST SERIES, OTHER DECODER/DRIVER, CONFIGURABLE OUTPUT, PDIP20, PLASTIC, SOT-146-1. DIP-20, Decoder/Driver
NXP
933795010602
IC F/FAST SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24, Bus Driver/Transceiver
NXP
933795020602
IC F/FAST SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, SOT-222-1, DIP-24, Bus Driver/Transceiver
NXP
933795210602
IC F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, 0.300 INCH, PLASTIC, SOT-38-4, DIP-16, Counter
NXP
933795280602
IC F/FAST SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, DIP-24, Bus Driver/Transceiver
NXP
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