934055779127 [NXP]
73A, 150V, 0.02ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247, PLASTIC, TO-247, 3 PIN;型号: | 934055779127 |
厂家: | NXP |
描述: | 73A, 150V, 0.02ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247, PLASTIC, TO-247, 3 PIN 局域网 开关 脉冲 晶体管 |
文件: | 总7页 (文件大小:94K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PSMN020-150W
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
VDSS = 150 V
ID = 73 A
• Low thermal resistance
g
RDS(ON) ≤ 20 mΩ
s
GENERAL DESCRIPTION
PINNING
SOT429 (TO247)
SiliconMAXproductsusethelatest
Philips Trench technology to
achieve the lowest possible
on-state resistance in each
package at each voltage rating.
PIN
DESCRIPTION
1
2
gate
drain
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
3
source
drain
2
tab
1
3
The PSMN020-150W is supplied in
the SOT429 (TO247) conventional
leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
150
150
± 20
73
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
51
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
290
300
175
- 55
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS Non-repetitive avalanche
CONDITIONS
MIN.
MAX.
UNIT
Unclamped inductive load, IAS = 73 A;
tp = 100 µs; Tj prior to avalanche = 25˚C;
-
707
mJ
energy
VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to
fig:15
IAS
Non-repetitive avalanche
current
-
73
A
November 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PSMN020-150W
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb Thermal resistance junction
CONDITIONS
TYP.
MAX.
UNIT
-
0.5
K/W
to mounting base
Thermal resistance junction in free air
to ambient
Rth j-a
45
-
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
150
-
-
-
-
V
V
voltage
Tj = -55˚C
134
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
2.0
1.0
3.0
-
-
12
-
2
0.05
-
4.0
-
6
20
56
100
10
500
V
V
V
mΩ
mΩ
nA
µA
µA
Tj = 175˚C
Tj = -55˚C
-
-
-
-
-
-
RDS(ON)
Drain-source on-state
resistance
Gate source leakage current VGS = ±10 V; VDS = 0 V
Zero gate voltage drain
current
VGS = 10 V; ID = 25 A
Tj = 175˚C
IGSS
IDSS
VDS = 150 V; VGS = 0 V;
Tj = 175˚C
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 73 A; VDD = 120 V; VGS = 10 V
-
-
-
227
46
91
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 75 V; RD = 2.7 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
-
-
-
34
79
233
101
-
-
-
-
ns
ns
ns
ns
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
-
-
3.5
4.5
7.5
-
-
-
nH
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
9537
854
380
-
-
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
-
-
73
A
ISM
VSD
Pulsed source current (body
diode)
Diode forward voltage
-
-
290
A
IF = 25 A; VGS = 0 V
IF = 75 A; VGS = 0 V
-
-
0.85
1.1
1.2
-
V
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
127
1.0
-
-
ns
µC
November 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PSMN020-150W
Transient thermal impedance, Zth j-mb (K/W)
Normalised Power Derating, PD (%)
100
1
0.1
D = 0.5
90
80
70
60
50
40
30
20
10
0
0.2
0.1
0.05
0.02
P
D = tp/T
D
0.01
tp
single pulse
T
0.001
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
0
25
50
75
100
125
150
175
Pulse width, tp (s)
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A)
Tj = 25 C VGS = 10V
80
70
60
50
40
30
20
10
0
Normalised Current Derating, ID (%)
8 V
6 V
100
90
80
70
60
50
40
30
20
10
0
5.2 V
5 V
4.8 V
4.6 V
4.4 V
4.2 V
0
25
50
75
100
125
150
175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Mounting Base temperature, Tmb (C)
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
ID% = 100 ID/ID 25 ˚C = f(Tmb); VGS ≥ 10 V
Peak Pulsed Drain Current, IDM (A)
1000
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
4.2 V
4.6 V
4.4V
4.8 V
Tj = 25 C
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
RDS(on) = VDS/ ID
tp = 10 us
100 us
5V
100
10
1
5.2V
1 ms
D.C.
10 ms
6 V
100 ms
VGS = 10V
8 V
1
10
100
1000
0
10
20
30
40
50
60
70
80
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
November 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PSMN020-150W
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
100
4.5
4
VDS > ID X RDS(ON)
90
maximum
typical
80
70
60
3.5
3
2.5
2
50
40
30
20
10
0
175 C
minimum
1.5
1
Tj = 25 C
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Drain current, ID (A)
100
90
80
70
60
50
40
30
20
10
0
1.0E-01
Tj = 25 C
175 C
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
minimum
typical
maximum
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
10
20
30
40
50
60
70
80
90
100
Gate-source voltage, VGS (V)
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
Capacitances, Ciss, Coss, Crss (pF)
100000
10000
1000
Ciss
Coss
Crss
100
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
0.1
1
10
100
1000
Junction temperature, Tj (C)
Drain-Source Voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
November 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PSMN020-150W
Maximum Avalanche Current, IAS (A)
100
10
1
Gate-source voltage, VGS (V)
15
ID = 73A
14
13
12
11
10
9
25 C
Tj = 25 C
VDD = 30 V
Tj prior to avalanche = 150 C
8
7
6
5
VDD = 120 V
4
3
2
1
0
0.1
0
25
50
75
100 125 150 175 200 225 250
Gate charge, QG (nC)
0.001
0.01
0.1
Avalanche time, tAV (ms)
1
10
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Source-Drain Diode Current, IF (A)
100
VGS = 0 V
90
80
70
175 C
60
50
Tj = 25 C
40
30
20
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Source-Drain Voltage, VSDS (V)
1
1.1 1.2
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
November 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PSMN020-150W
MECHANICAL DATA
Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247
SOT429
α
E
P
A
A
1
β
q
S
R
D
Y
(1)
L
1
Q
b
2
L
1
2
3
c
b
1
w
M
b
e
e
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
β
A
A
b
b
b
2
c
D
E
e
L
L
1
P
Q
q
R
S
w
Y
α
UNIT
mm
1
1
1.9
1.7
1.2
0.9
3.7
3.3
2.6
2.4
7.5
7.1
15.7
15.3
6°
4°
17°
13°
5.3
4.7
2.2
1.8
3.2
2.8
0.9
0.6
21
20
16
15
16
15
4.0
3.6
3.5
3.3
5.45
5.3
0.4
Note
1. Tinning of terminals are uncontrolled within zone L
.
1
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
98-04-07
99-08-04
SOT429
TO-247
Fig.16. SOT429; pin 2 connected to mounting base
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT429 envelope.
3. Epoxy meets UL94 V0 at 1/8".
November 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PSMN020-150W
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 1999
7
Rev 1.000
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