935248340518 [NXP]
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 7.50 MM, PLASTIC, MS-013, SOT-136-1, SO-28;
| 型号： | 935248340518 |
| 厂家： | 
NXP |
| 描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28, 7.50 MM, PLASTIC, MS-013, SOT-136-1, SO-28 光电二极管 外围集成电路 |
| 文件： | 总22页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8004T
IC card interface
Product specification
2004 May 10
Supersedes data of 1999 Dec 30
Philips Semiconductors
Product specification
IC card interface
TDA8004T
FEATURES
• Non-inverted control of RST via pin RSTIN
• ISO 7816, GSM11.11 and EMV (payment systems)
compatibility
• 3 or 5 V supply for the IC (GND and VDD
)
• Step-up converter for VCC generation (separately
powered with a 5 V ±10% supply, VDDP and PGND)
• Supply supervisor for spikes killing during power-on and
power-off
• 3 specific protected half duplex bidirectional buffered
I/O lines (C4, C7 and C8)
• One multiplexed status signal OFF.
• VCC regulation 5 V ±5% on 2 × 100 nF or 1 × 100 nF
and 1 × 220 nF multilayer ceramic capacitors with low
ESR, ICC < 65 mA at 4.5 V < VDDP < 6.5 V, current
spikes of 40 nAs up to 20 MHz, with controlled rise and
fall times, filtered overload detection approximately
90 mA)
APPLICATIONS
• IC card readers for banking
• Electronic payment
• Identification
• Thermal and short-circuit protections on all card
• Pay TV.
contacts
• Automatic activation and deactivation sequences
(initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating or supply
drop-out)
GENERAL DESCRIPTION
The TDA8004T is a complete low cost analog interface for
asynchronous smart cards. It can be placed between the
card and the microcontroller with very few external
components to perform all supply protection and control
functions.
• Enhanced ESD protection on card side (>6 kV)
• 26 MHz integrated crystal oscillator
• Clock generation for the card up to 20 MHz (divided by
1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
plastic small outline package; 28 leads; body width 7.5 mm
VERSION
TDA8004T
SO28
SOT136-1
2004 May 10
2
Philips Semiconductors
Product specification
IC card interface
TDA8004T
QUICK REFERENCE DATA
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
VDD
VDDP
IDD
supply voltage
2.7
−
5
−
6.5
6.5
1.2
V
step-up supply voltage
supply current
4.5
V
inactive mode; VDD = 3.3 V;
fXTAL = 10 MHz
−
mA
active mode; VDD = 3.3 V;
fXTAL = 10 MHz; no load
−
−
−
−
−
−
1.5
0.1
18
mA
mA
mA
IDDP
step-up supply current
inactive mode; VDDP = 5 V;
fXTAL = 10 MHz
active mode; VDDP = 5 V;
fXTAL = 10 MHz; no load
Card supply
VCC
card supply voltage including
ripple
DC ICC < 65 mA
4.75
4.65
−
−
−
−
5.25
5.25
350
V
AC current spikes of 40 nAs
from 20 kHz to 200 MHz
V
Vi(ripple)(p-p) ripple voltage on VCC
(peak-to-peak value)
mV
ICC
card supply current
VCC from 0 to 5 V
−
−
65
mA
General
fCLK
card clock frequency
0
−
20
MHz
µs
tde
deactivation cycle duration
60
−
80
−
100
0.56
+85
Ptot
continuous total power dissipation Tamb = −25 to +85 °C
W
Tamb
ambient temperature
−25
−
°C
2004 May 10
3
Philips Semiconductors
Product specification
IC card interface
TDA8004T
BLOCK DIAGRAM
V
V
DD
100 nF
DDP
100 nF
100 nF
S1
S2
5
6
7
21
PGND
VUP
4
8
SUPPLY
STEP-UP CONVERTER
INTERNAL
REFERENCE
V
ref
INTERNAL OSCILLATOR
2.5 MHz
100 nF
VOLTAGE SENSE
ALARM
EN1 CLKUP
EN2
PV
23
20
19
V
V
17
CC
CC
OFF
RSTIN
CC
GENERATOR
100
nF
100
nF
14 CGND
16
CMDVCC
EN5
EN4
RST
BUFFER
3
RST
RFU1
SEQUENCER
1
2
CLKDIV1
CLKDIV2
15
CLOCK
BUFFER
CLK
HORSEQ
CLOCK
CIRCUITRY
10
9
PRES
PRES
CLK
EN3
THERMAL
PROTECTION
24
25
XTAL1
XTAL2
OSCILLATOR
27
28
I/O
13
12
11
AUX1UC
AUX2UC
AUX1
AUX2
I/O
TRANSCEIVER
TDA8004T
I/O
TRANSCEIVER
26
I/O
I/OUC
TRANSCEIVER
18
22
MGM175
n.c.
GND
All capacitors are mandatory.
Fig.1 Block diagram.
4
2004 May 10
Philips Semiconductors
Product specification
IC card interface
TDA8004T
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
CLKDIV1
CLKDIV2
RFU1
1
2
3
4
5
I
I
I
control with CLKDIV2 for choosing CLK frequency
control with CLKDIV1 for choosing CLK frequency
reserved for future use (to be connected to VDD or microcontroller I/O; active HIGH)
PGND
S2
supply power ground for step-up converter
I/O
capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ
must be connected between pins S1 and S2)
VDDP
S1
6
7
supply power supply voltage for step-up converter
I/O
capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ
must be connected between pins S1 and S2)
VUP
8
9
I/O
output of step-up converter (a 100 nF capacitor with ESR < 100 mΩ must be
connected to PGND)
PRES
PRES
I
I
card presence contact input (active LOW); if PRES or PRES is true, then the card is
considered as present
10
card presence contact input (active HIGH); if PRES or PRES is true, then the card is
considered as present
I/O
11
12
13
14
15
16
17
I/O
I/O
I/O
data line to and from card (C7) (internal 10 kΩ pull-up resistor connected to VCC)
AUX2
AUX1
CGND
CLK
auxiliary line to and from card (C8) (internal 10 kΩ pull-up resistor connected to VCC
auxiliary line to and from card (C4) (internal 10 kΩ pull-up resistor connected to VCC
)
)
supply ground for card signals
O
O
O
clock to card (C3)
card reset (C2)
RST
VCC
Supply for card (C1); decouple to CGND with 2 × 100 nF or 1 × 100 nF and 1 × 220 nF
capacitors with ESR < 100 mΩ (with 220 nF, the noise margin on VCC will be higher).
n.c.
18
19
20
21
22
23
−
I
not connected
CMDVCC
RSTIN
VDD
start activation sequence input from microcontroller (active LOW)
card reset input from microcontroller (active HIGH)
I
supply supply voltage
supply ground
GND
OFF
O
NMOS interrupt to microcontroller (active LOW) with 20 kΩ internal pull-up resistor
connected to VDD (refer section “Fault detection”)
XTAL1
XTAL2
I/OUC
24
25
26
27
I
crystal connection or input for external clock
O
crystal connection (leave open if an external clock source is used)
microcontroller data I/O line (internal 10 kΩ pull-up resistor connected to VDD
I/O
I/O
)
AUX1UC
auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to
VDD
auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to
VDD
)
AUX2UC
28
I/O
)
2004 May 10
5
Philips Semiconductors
Product specification
IC card interface
TDA8004T
FUNCTIONAL DESCRIPTION
Throughout this document, it is assumed that the reader is
familiar with ISO 7816 norm terminology.
Power supply
The supply pins for the IC are VDD and GND. VDD should
be in the range from 2.7 to 6.5 V. All interface signals with
the system controller are referenced to VDD; so, be sure
the supply voltage of the system controller is also VDD. All
card contacts remain inactive during powering up or
powering down. The sequencer is not activated until VDD
reaches Vth2 + Vhys(th2) (see Fig.3). When VDD falls below
Vth2, an automatic deactivation of the contacts is
performed.
handbook, halfpage
CLKDIV1
CLKDIV2
RFU1
AUX2UC
AUX1UC
I/OUC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
3
For generating a 5 V ±5% VCC supply to the card, an
integrated voltage doubler is incorporated. This step-up
converter should be separately supplied by VDDP and
PGND (from 4.5 to 6.5 V). Due to large transient currents,
the 2 × 100 nF capacitors of the step-up converter should
have an ESR less than 100 mΩ and be located as near as
possible to the IC.
PGND
S2
XTAL2
4
XTAL1
5
V
6
OFF
DDP
S1
GND
7
TDA8004T
V
VUP
8
DD
The supply voltages VDD and VDDP may be applied to
the IC in any time sequence.
RSTIN
9
PRES
PRES
10
11
CMDVCC
n.c.
If a voltage between 7 and 9 V is available within the
application, this voltage may be tied to pin VUP, thus
blocking the step-up converter. In this case, VDDP must be
tied to VDD and the capacitor between pins S1 and S2 may
be omitted.
I/O
V
AUX2 12
AUX1
CC
RST
13
CGND 14
15 CLK
Voltage supervisor
MGM174
This block surveys the VDD supply. A defined reset pulse
of approximately 10 ms (tW) is used internally for
maintaining the IC in the inactive mode during powering up
or powering down of VDD (see Fig.3).
As long as VDD is less than Vth2 + Vhys(th2), the IC will
remain inactive whatever the levels on the command lines.
This also lasts for the duration of tW after VDD has reached
a level higher than Vth2 + Vhys(th2)
.
The system controller should not try to start an activation
during this time.
Fig.2 Pin configuration.
When VDD falls below Vth2, a deactivation sequence of the
contacts is performed.
2004 May 10
6
Philips Semiconductors
Product specification
IC card interface
TDA8004T
V
V
+ V
hys(th2)
th2
th2
V
DD
t
t
W
W
ALARM
(internal signal)
MGM176
Fig.3 ALARM as a function of VDD (tW = 10 ms).
Clock circuitry
In the other cases, it is guaranteed between 45% and 55%
of the period.
The clock signal (CLK) to the card is either derived from a
clock signal input on pin XTAL1 or from a crystal up to
26 MHz connected between pins XTAL1 and XTAL2.
The crystal oscillator runs as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
XTAL1 is permanent, then the clock pulse will be applied
to the card according to the timing diagram of the
activation sequence (see Fig.5).
The frequency may be chosen at
fXTAL, 1⁄2fXTAL, 1⁄4fXTAL or 1⁄8fXTAL via pins CLKDIV1 and
CLKDIV2.
If the signal applied to XTAL1 is controlled by the system
controller, then the clock pulse will be applied to the card
when the system controller will send it (after completion of
the activation sequence).
The frequency change is synchronous, which means that
during transition, no pulse is shorter than 45% of the
smallest period and that the first and last clock pulse
around the change has the correct width.
In the case of fXTAL, the duty factors are dependent on the
signal at XTAL1.
Table 1 Clock circuitry definition
CLKDIV1
CLKDIV2
CLK
1⁄8fXTAL
1⁄4fXTAL
1⁄2fXTAL
fXTAL
In order to reach a 45% to 55% duty factor on pin CLK the
input signal on XTAL1 should have a duty factor of
48% to 52% and transition times of less than 5% of the
input signal period.
0
0
1
1
0
1
1
0
If a crystal is used with fXTAL, the duty factor on pin CLK
may be 45% to 55% depending on the layout and on the
crystal characteristics and frequency.
2004 May 10
7
Philips Semiconductors
Product specification
IC card interface
TDA8004T
I/O circuitry
Inactive state
The three data lines I/O, AUX1 and AUX2 are identical.
After power-on reset, the circuit enters the inactive state. A
minimum number of circuits are active while waiting for the
microcontroller to start a session.
The Idle state is realized by both lines (I/O and I/OUC)
being pulled HIGH via a 10 kΩ resistor (I/O to VCC and
I/OUC to VDD).
• All card contacts are inactive (approximately 200 Ω to
GND)
I/O is referenced to VCC and I/OUC to VDD, thus allowing
• I/OUC, AUX1UC and AUX2UC are high impedance
operation with VCC ≠ VDD
.
(10 kΩ pull-up resistor connected to VDD
• Voltage generators are stopped
• XTAL oscillator is running
)
The first side on which a falling edge occurs becomes the
master. An anti-latch circuit disables the detection of falling
edges on the other line, which becomes a slave.
• Voltage supervisor is active.
After a time delay td(edge) (approximately 200 ns), the
N transistor on the slave side is turned on, thus
transmitting the logic 0 present on the master side.
Activation sequence
After power-on and after the internal pulse width delay, the
system controller may check the presence of the card with
the signal OFF (OFF = HIGH while CMDVCC is HIGH
means that the card is present; OFF = LOW while
CMDVCC is HIGH means that no card is present).
When the master side returns to logic 1, the P transistor on
the slave side is turned on during the time delay td(edge) and
then both sides return to their Idle states.
This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA up to an
output voltage of 0.9VCC on a 80 pF load. At the end of the
active pull-up pulse, the output voltage only depends on
the internal pull-up resistor and on the load current (see
Fig.4).
If the card is in the reader (which is the case if PRES or
PRES is true), the system controller may start a card
session by pulling CMDVCC LOW.
The following sequence then occurs (see Fig.5):
• CMDVCC is pulled LOW (t0)
The maximum frequency on these lines is 1 MHz.
• The voltage doubler is started (t1 ~ t0)
• VCC rises from 0 to 5 V with a controlled slope
(t2 = t1 + 1⁄23T) (I/O, AUX1 and AUX2 follow VCC with a
slight delay)
FCE270
6
12
handbook, halfpage
V
o
(V)
I
o
(mA)
• I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T)
• CLK is applied to the C3 contact (t4)
• RST is enabled (t5 = t1 + 7T).
(1)
(2)
4
8
In the timing informations above and below, T is 64 times
the period of the internal oscillator, about 25 µs.
The clock may be applied to the card in the following way:
2
4
0
• Set RSTIN HIGH before setting CMDVCC LOW and
reset it LOW between t3 and t5; CLK will start at this
moment. RST will remain LOW until t5, where RST is
enabled to be the copy of RSTIN. After t5, RSTIN has no
further action on CLK. This is to allow a precise count of
CLK pulses before toggling RST.
0
0
20
40
60
t (ns)
(1) Current.
(2) Voltage.
If this feature is not needed, then CMDVCC may be set
LOW with RSTIN LOW. In this case, CLK will start at t3 and
after t5, RSTIN may be set HIGH in order to get the Answer
To Request (ATR) from the card.
Fig.4 I/O, AUX1, and AUX2 output voltage and
current as a function of time during a
LOW-to-HIGH transition.
2004 May 10
8
Philips Semiconductors
Product specification
IC card interface
TDA8004T
t
OSC_INT/64
act
(T
≈ 25 µs)
CMDVCC
VUP
t
1
t
V
2
CC
ATR
I/O
CLK
t
5
high - Z
t
t
4
3
RSTIN
RST
t
0
MGM177
Fig.5 Activation sequence.
Active state
With all these layout precautions, noise should be at an
acceptable level and jitter on C3 should be less than
100 ps. Refer to Application Note AN97036 for specimen
layouts
When the activation sequence is completed, the
TDA8004T will be in the active state. Data is exchanged
between the card and the microcontroller via the I/O lines.
The TDA8004T is designed for cards without VPP (this is
the voltage required to program or erase the internal
non-volatile memory).
Deactivation sequence
When a session is completed, the microcontroller sets the
CMDVCC line to the HIGH state. The circuit then executes
an automatic deactivation sequence by counting the
sequencer back and ends in the inactive state (see Fig.6):
Depending on the layout and on the application test
conditions (for example with an additional 1 pF cross
capacitance between C2/C3 and C2/C7) it is possible
that C2 is polluted with high frequency noise from C3. In
this case, it will be necessary to connect a 220 pF
capacitance between C2 and CGND.
• RST goes LOW → (t11 = t10)
• CLK is stopped LOW → (t12 = t11 + 1⁄2T)
• I/O, AUX1 and AUX2 are output into high-impedance
state → (t13 = t11 + T); 10 kΩ pull-up resistor connected
to VCC
• VCC falls to zero → (t14 = t11 + 1⁄23T); the deactivation
sequence is completed when VCC reaches its inactive
state
It is recommended to:
1. Keep track C3 as far as possible from other tracks
2. Have straight connection between CGND and C5 (the
2 capacitors on C1 should be connected to this ground
track)
• VUP falls to zero → (t15 = t11 + 5T) and all card contacts
become low-impedance to GND; I/OUC, AUX1UC and
AUX2UC remain pulled up to VDD via a 10 kΩ resistor.
3. Avoid ground loops between CGND, PGND and GND
4. Decouple VDDP and VDD separately; if the 2 supplies
are the same in the application, then they should be
connected in star on the main track.
2004 May 10
9
Philips Semiconductors
Product specification
IC card interface
TDA8004T
t
de
OSC_INT/64
(T ≈ 25 µs)
t
10
CMDVCC
VUP
t
15
t
14
V
CC
t
13
I/O
high - Z
t
12
CLK
RST
t
11
MGE739
Fig.6 Deactivation sequence.
Fault detection
When the system controller sets CMDVCC back to
HIGH, it may sense OFF again in order to distinguish
between a hardware problem or a card extraction. If a
supply voltage drop on VDD is detected whilst the card
is activated, then an emergency deactivation will be
performed, but OFF remains HIGH.
The following fault conditions are monitored by the circuit:
• Short-circuit or high current on VCC
• Removing card during transaction
• VDD dropping
Depending on the type of card presence switch within the
connector (normally closed or normally open) and on the
mechanical characteristics of the switch, a bouncing may
occur on presence signals at card insertion or withdrawal.
• Overheating.
There are two different cases (see Fig.7):
1. CMDVCC HIGH: (outside a card session) then, OFF is
LOW if the card is not in the reader and HIGH if the
card is in the reader. A supply voltage drop on VDD is
detected by the supply supervisor, generates an
internal power-on reset pulse, but don’t act upon OFF.
The card is not powered-up, so no short-circuit or
overheating is detected.
There is no debounce feature in the device, so the
software has to take it into account; however, the detection
of card take off during active phase, which initiates an
automatic deactivation sequence is done on the first
true/false transition on PRES or PRES and is memorized
until the system controller sets CMDVCC HIGH.
2. CMDVCC LOW: (within a card session) then, OFF falls
LOW if the card is extracted, or if a short-circuit has
occurred on VCC, or if the temperature on the IC has
become too high. As soon as the fault is detected, an
emergency deactivation is automatically performed
(see Fig.8).
So, the software may take some time waiting for presence
switches to be stabilized without causing any delay on the
necessary fast and normalized deactivation sequence.
2004 May 10
10
Philips Semiconductors
Product specification
IC card interface
TDA8004T
PRES
OFF
CMDVCC
V
CC
Deactivation caused by
cards withdrawal
Deactivation caused by
short circuit
FCE271
Fig.7 Behaviour of OFF, CMDVCC, PRES and VCC
.
t
de
OSC_INT/64
(T
≈
25 µs)
t
OFF
10
PRES
t
14
V
CC
t
13
I/O
CLK
RST
high - Z
t
12
t
11
MGE740
Fig.8 Emergency deactivation sequence.
VCC regulator
VCC buffer is able to deliver up to 65 mA continuously. It has an internal overload detection at approximately 90 mA.
This detection is internally filtered, allowing spurious current pulses up to 200 mA to be drawn by the card without causing
a deactivation (the average current value must stay below 65 mA).
For VCC accuracy reasons, a 100 nF capacitor with ESR < 100 mΩ should be tied to CGND near pin 17 and a 100 nF
(or better 220 nF) with same ESR should be tied to CGND near C1 contact.
2004 May 10
11
Philips Semiconductors
Product specification
IC card interface
TDA8004T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
VDD, VDDP supply voltage
−0.3
−0.3
+7
+7
V
V
Vn1
voltage on pins: XTAL1, XTAL2, RFU1, RSTIN,
AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2,
CMDVCC and OFF
Vn2
voltage on card contact pins PRES, PRES, I/O, RST,
AUX1, AUX2 and CLK
−0.3
+7
9
V
V
Vn3
Tstg
Ptot
Tj
voltage on pin VUP, S1 and S2
IC storage temperature
−
−55
−
+125 °C
continuous total power dissipation
junction temperature
Tamb = −25 to +85 °C
0.56
150
+6
W
−
°C
kV
Ves1
electrostatic voltage on pins: I/O, RST, VCC, AUX1,
CLK, AUX2, PRES and PRES
−6
Ves2
electrostatic voltage on all other pins
−2
+2
kV
Notes
1. All card contacts are protected against any short with any other card contact.
HANDLING
Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM; 1500 Ω; 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
70
UNIT
K/W
Rth(j-a)
thermal resistance from junction to ambient
2004 May 10
12
Philips Semiconductors
Product specification
IC card interface
TDA8004T
CHARACTERISTICS
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the
temperature range; fXTAL = 10 MHz; unless otherwise specified; all currents flowing into the IC are positive. When a
parameter is specified as a function of VDD or VCC, it means their actual value at the moment of measurement.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Temperature
Tamb
ambient temperature
−25
−
+85
°C
Supplies
VDD
supply voltage
2.7
4.5
−
6.5
6.5
V
V
VDDP
supply voltage for the voltage
doubler
5
Vo(VUP)
Vi(VUP)
output voltage on pin VUP from
step-up converter
−
5.5
−
V
V
input voltage to be applied on VUP
in order to block the step-up
converter
7
−
9
IDD
supply current
inactive mode
−
−
−
−
1.2
1.5
mA
mA
active mode; fCLK = fXTAL
CL = 30 pF
;
;
IDDP
supply current for the step-up
converter
inactive mode
−
−
0.1
mA
active mode; fCLK = fXTAL
CL = 30 pF
ICC = 0
−
−
−
−
−
−
18
mA
mA
V
ICC = 65 mA
−
150
2.4
150
20
Vth2
threshold voltage on VDD (falling)
hysteresis on Vth2
2.2
50
6
Vhys(th2)
tW
mV
ms
width of the internal ALARM pulse
Card supply voltage (VCC); note 1
VCC output voltage including ripple
inactive mode
−0.1
−0.1
4.75
−
−
−
+0.1
+0.4
5.25
V
V
V
inactive mode; ICC = 1 mA
active mode;
ICC < 65 mA DC
active mode; single current 4.65
pulse of −100 mA; 2 µs
−
−
5.25
5.25
V
V
active mode; current pulses 4.65
of 40 nAs with
ICC < 200 mA; t < 400 ns;
Vi(ripple)(p-p) peak-to-peak ripple voltage on VCC from 20 kHz to 200 MHz
−
−
−
−
350
65
mV
ICC
output current
from 0 to 5 V;
−
mA
VCC short-circuit to ground
−
120
mA
SR
slew rate
up
0.09
0.09
0.18 0.27
0.21 0.27
V/µs
V/µs
down
2004 May 10
13
Philips Semiconductors
Product specification
IC card interface
TDA8004T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Crystal connections (XTAL1 and XTAL2)
Cext
external capacitance on
XTAL1 and XTAL2
depending on specification
of crystal or resonator used
−
−
15
26
pF
fi(XTAL)
crystal input frequency
2
−
−
−
MHz
VIH(XTAL)
VIL(XTAL)
HIGH-level input voltage on XTAL1
LOW-level input voltage on XTAL1
0.8VDD
VDD + 0.2 V
−0.3
0.2VDD
V
Data lines (I/O, I/OUC, AUX1, AUX2, AUXUC1 and AUXUC2)
GENERAL
td(edge)
delay between falling edge on pins
I/OUC and I/O (or I/O and I/OUC)
and width of active pull-up pulse
−
200
−
ns
fI/O(max)
Ci
maximum frequency on data lines
input capacitance on data lines
−
−
−
−
1
MHz
pF
10
DATA LINES; I/O, AUX1 AND AUX2 (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VCC
)
VOH
HIGH-level output voltage on data
lines
no DC load
IOH = −40 µA
I = 1 mA
0.9VCC
0.75VCC
−
−
−
−
VCC + 0.1 V
VCC + 0.1 V
VOL
LOW-level output voltage on data
lines
300
mV
VIH
HIGH-level input voltage on data
lines
1.8
−
−
VCC + 0.3 V
VIL
LOW-level input voltage on data
lines
−0.3
+0.8
V
Vinactive
voltage on data lines outside a
session
no load
−
−
−
−
0.1
0.3
−
V
II/O = 1 mA
−
V
Iedge
ILIH
current from data lines when active VOH = 0.9VCC; Co = 80 pF
pull-up active
−1
mA
input leakage current HIGH on data VIH = VCC
lines
−
−
9
−
10
µA
µA
kΩ
IIL
LOW-level input current on data
lines
VIL = 0 V
−
600
13
Rpu(int)
tr, tf
internal pull-up resistance between
data lines and VCC
11
input transition times on data lines
from VIL(max) to VIH(min)
−
−
−
−
1
µs
µs
output transition times on data lines Co = 80 pF, no DC load;
0.1
10% to 90% of VCC (see
Fig.9)
DATA LINES; I/OUC, AUX1UC AND AUX2UC (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VDD
)
VOH
HIGH-level output voltage on data
lines
no DC load
IOH = −40 µA
IOL = 1 mA
0.9VDD
0.75VDD
−
−
−
−
VDD + 0.2 V
VDD + 0.2
VOL
LOW-level output voltage on data
lines
300
mV
2004 May 10
14
Philips Semiconductors
Product specification
IC card interface
TDA8004T
SYMBOL
VIH
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HIGH-level input voltage on data
lines
0.7VDD
−
VDD + 0.3 V
VIL
ILIH
LOW-level input voltage on data
lines
0
−
−
0.3VDD
10
V
input leakage current HIGH on data VIH = VDD
lines
−
µA
IIL
LOW-level input on data lines
VIL = 0 V
−
−
600
13
µA
kΩ
Rpu(int)
internal pull-up resistance between
data lines and VDD
9
11
tr, tf
input transition times on data lines
from VIL(max) to VIH(min)
−
−
−
−
1
µs
µs
output transition times on data lines Co = 30 pF; 10% to 90%
of VDD (see Fig.9)
0.1
Internal oscillator
fosc(int)
frequency of internal oscillator
2.2
−
3.2
MHz
Reset output to the card (RST)
Vo(inactive)
output voltage in inactive mode
no load
0
−
−
−
−
−
−
0.1
0.3
2
V
Io = 1 mA
0
V
td(RSTIN-RST) delay between pins RSTIN and RST RST enabled
−
µs
V
VOL
VOH
tr, tf
LOW-level output voltage
HIGH-level output voltage
rise and fall times
IOL = 200 µA
IOH = −200 µA
Co = 250 pF
0
0.3
VCC
0.1
0.9VCC
V
−
µs
Clock output to the card (CLK)
Vo(inactive)
output voltage in inactive mode
no load
0
−
−
−
−
−
−
−
0.1
0.3
0.3
VCC
8
V
Io = 1 mA
0
V
VOL
VOH
tr, tf
δ
LOW-level output voltage
HIGH-level output voltage
rise and fall times
IOL = 200 µA
IOH = −200 µA
CL = 35 pF; note 2
CL = 35 pF; note 2
CL = 35 pF
0
V
0.9VCC
−
V
ns
%
V/ns
duty factor (except for fXTAL
slew rate (rise and fall)
)
45
55
−
SR
0.2
Logic inputs (CLKDIV1, CLKDIV2, PRES, PRES, CMDVCC, RSTIN and RFU1); note 3
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
input leakage current LOW
input leakage current HIGH
−
−
−
−
−
0.3VDD
V
0.7VDD
−
5
5
V
ILIL
ILIH
0 < VIL < VDD
0 < VIH < VDD
−
−
µA
µA
OFF output (OFF is an open drain with an internal 20 kΩ pull-up resistor to VDD
)
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = 2 mA
−
−
−
0.4
V
V
IOH = −15 µA
0.75VDD
−
Protections
Tsd
shut-down temperature
shut-down current at VCC
−
−
135
−
°C
ICC(sd)
−
110
mA
2004 May 10
15
Philips Semiconductors
Product specification
IC card interface
TDA8004T
SYMBOL
Timing
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tact
tde
t3
activation sequence duration
deactivation sequence duration
see Fig.5
see Fig.6
−
180 220
µs
µs
µs
60
−
80
100
130
start of the window for sending CLK see Fig.5
to the card
−
t5
end of the window for sending CLK see Fig.5
to the card
140
−
−
µs
Notes
1. To meet these specifications VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR
with values of either 100 nF or one 100 nF and one 220 nF.
t1
2. The transition times and duty factor definitions are shown in Fig.9; δ =
-------------------
(t1 + t2)
3. PRES and CMDVCC are active LOW; RSTIN and PRES are active HIGH; for CLKDIV1 and CLKDIV2 see Table 1;
RFU1 must be tied HIGH.
t
t
f
r
V
or V
DD
CC
90%
90%
(V
0
+ V )/2
OH
OL
10%
10%
t
t
2
1
MGM178
Fig.9 Definition of output transition times.
APPLICATION INFORMATION
VDD for the TDA8004T must be the same as for the microcontroller and CLKDIV1, CLKDIV2, RSTIN, PRES, PRES,
AUX1UC, AUX2UC, I/OUC, RFU1, CMDVCC and OFF should be referenced to VDD and XTAL1 also when driven by an
external clock.
For optimum layout be sure that there is enough ground area around the TDA8004T and the connector. Place the
TDA8004T very near to the connector, ideally under the connector, and decouple VDD and VDDP properly.
Refer to AN97036 for further application information for proper implementation of the TDA8004T.
2004 May 10
16
Philips Semiconductors
Product specification
IC card interface
TDA8004T
V
for the TDA8004 must be the same as controller
DD
supply voltage, CLKDIV1, CLKDIV2, RSTIN, PRES,
PRES, AUXUC, I/OUC, AUX2UC, RFU1, CMDVCC,
OFF should be referenced to V , and also XTAL1
if driven by external clock.
More application information on
application report AN97036
DD
CLKDIV1
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
28
27
26
25
24
23
1
2
3
4
5
6
10 µF
100 nF
CLKDIV2
RFU1
+5 V
+3.3 V
GNDP
S2
3.3 V POWERED
MICROCONTROLLER
33 pF
V
DDP
100 nF
S1
VUP
GND
7
22
21
20
19
18
17
16
15
TDA8004T
V
100 nF
DD
8
+3.3 V
RSTIN
CMDVCC
n.c.
PRES
PRES
I/O
100 nF
9
10
11
12
13
14
These capacitors
must be placed
near the IC and
have LOW ESR
(Less than 1 cm)
+3.3 V
V
AUX2
AUX1
CGND
CC
RST
CLK
100 k
+3.3 V
One 100nF
with LOW ESR
near pin 17,
100 nF
Straight and short
connextions between
CGND, C5 and capacitors
GND. (No loop)
CARD READ
(Normally closed type)
One 100nF or 220nF
with LOW ESR
220 nF
near C1 contact
(less than 1cm)
C5
C6
C1
C2
C7
C8
C3
C4
C3 should be routed
far from C2, C7, C4 and C8
and, better, surrounded
with ground tracks.
K1
K2
MGM179
Fig.10 Application diagram.
17
2004 May 10
Philips Semiconductors
Product specification
IC card interface
TDA8004T
PACKAGE OUTLINE
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
H
v
M
A
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.71
0.014 0.009 0.69
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT136-1
075E06
MS-013
2004 May 10
18
Philips Semiconductors
Product specification
IC card interface
TDA8004T
SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
Introduction to soldering surface mount packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all BGA, HTSSON-T and SSOP-T packages
Manual soldering
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
volume ≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 May 10
19
Philips Semiconductors
Product specification
IC card interface
TDA8004T
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
PLCC(5), SO, SOJ
not suitable(4)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not recommended(7)
suitable
not suitable
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 May 10
20
Philips Semiconductors
Product specification
IC card interface
TDA8004T
DATA SHEET STATUS
DATA SHEET
LEVEL
PRODUCT
STATUS(2)(3)
DEFINITION
STATUS(1)
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 May 10
21
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R63/03/pp22
Date of release: 2004 May 10
Document order number: 9397 750 13141
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