935249730112 [NXP]
IC 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOT-109, SO-16, Counter;
| 型号： | 935249730112 |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, PLASTIC, SOT-109, SO-16, Counter 光电二极管 |
| 文件： | 总5页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4040B
MSI
12-stage binary counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
DESCRIPTION
The HEF4040B is a 12-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O0 to O11).
The counter advances on the HIGH to LOW transition of
CP. A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of CP. Each counter stage is a
static toggle flip-flop. Schmitt-trigger action in the clock
input makes the circuit highly tolerant to slower clock rise
and fall times.
Fig.1 Functional diagram.
PINNING
CP
clock input (HIGH to LOW edge-triggered)
master reset input (active HIGH)
parallel outputs
MR
O0 to O11
APPLICATION INFORMATION
Some examples of applications for the HEF4040B are:
• Frequency dividing circuits
• Time delay circuits
Fig.2 Pinning diagram.
• Control counters
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
HEF4040BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4040BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4040BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
January 1995
2
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
Fig.3 Logic diagram.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Propagation delays
CP → O0
HIGH to LOW
5
105
45
35
85
40
30
35
15
10
35
15
10
90
40
30
60
30
20
60
30
20
210 ns
78 ns
34 ns
27 ns
58 ns
29 ns
22 ns
note 1
note 1
note 1
note 1
note 1
note 1
63 ns
29 ns
22 ns
10 ns
9 ns
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
10
15
5
tPHL
tPLH
tPHL
tPLH
tPHL
tTHL
tTLH
90 ns
70 ns
170 ns
80 ns
60 ns
70 ns
30 ns
20 ns
70 ns
30 ns
20 ns
180 ns
80 ns
60 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
LOW to HIGH
10
15
5
On → On + 1
HIGH to LOW
10
15
5
LOW to HIGH
10
15
5
MR → On
+
+
+
+
+
+
+
+
+
HIGH to LOW
10
15
5
Output transition times
HIGH to LOW
10
15
5
6 ns
10 ns
9 ns
LOW to HIGH
January 1995
10
15
6 ns
3
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Minimum clock
5
10
15
5
50
30
20
40
30
20
40
30
20
10
15
25
25
15
10
20
15
10
20
15
10
20
30
50
ns
pulse width; HIGH
tWCPH
tWMRH
tRMR
ns
ns
Minimum MR
ns
pulse width; HIGH
10
15
5
ns
ns
see also waveforms
Fig.4
Recovery time
for MR
ns
10
15
5
ns
ns
Maximum clock
pulse frequency
MHz
MHz
MHz
10
15
fmax
Note
1. For other loads than 50 pF at the nth output, use the slope given.
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
400 fi + ∑ (foCL) × VDD
where
2
10
15
2 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
2
5 200 fi + ∑ (foCL) × VDD
V
DD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4040B
MSI
12-stage binary counter
Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths.
January 1995
5
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