935249800518 [NXP]
IC SPECIALTY MEMORY CIRCUIT, PDSO40, 10.16 MM, PLASTIC, SO-40, Memory IC:Other;
| 型号： | 935249800518 |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY MEMORY CIRCUIT, PDSO40, 10.16 MM, PLASTIC, SO-40, Memory IC:Other 光电二极管 内存集成电路 |
| 文件： | 总30页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA4955TJ
2.9-Mbit field memory
1999 Apr 29
Product specification
Supersedes data of 1997 Sep 25
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
PALplus, PIP and 3D comb filter. The maximum storage
depth is 245772 words × 12 bits. A FIFO operation with
full word continuous read and write could be used as a
data delay, for example. A FIFO operation with
FEATURES
• 2949264-bit field memory
• 245772 × 12-bit organization
• 3.3 V power supply
asynchronous read and write could be used as a data rate
multiplier. Here the data is written once, then read as many
times as required without being overwritten by new data.
In addition to the FIFO operations, a random block access
mode is accessible during the pointer reset operation.
When this mode is enabled, reading and/or writing may
begin at, or proceed from, the start address of any of the
6144 blocks. Each block is 40 words in length. Two or
more SAA4955TJs can be cascaded to provide greater
storage depth or a longer delay, without the need for
additional circuitry.
• Inputs fully TTL compatible when using an extra 5 V
power supply
• High speed read and write operations
• FIFO operations:
– full word continuous read and write
– independent read and write pointers (asynchronous
read and write access)
– resettable read and write pointers
• Optional random access by block function (40 words per
block) enabled during pointer reset operation
The SAA4955TJ contains separate 12-bit wide serial ports
for reading and writing. The ports are controlled and
clocked separately, so asynchronous read and write
operations are supported. Independent read and write
clock rates are possible. Addressing is controlled by read
and write address pointers. Before a controlled write
operation can begin, the write pointer must be set to zero
or to the beginning of a valid address block. Likewise, the
read pointer must be set to zero or to the beginning of a
valid address block before a controlled read operation can
begin.
• Quasi static (internal self-refresh and clocking pauses of
infinite length)
• Write mask function
• Cascade operation possible
• 16 Mbit CMOS DRAM process technology
• 40-pin SOJ Package.
GENERAL DESCRIPTION
The SAA4955TJ is a 2949264-bit field memory designed
for advanced TV applications such as 100/120 Hz TV,
QUICK REFERENCE DATA
SYMBOL
PARAMETER
WRITE cycle time (SWCK)
READ cycle time (SRCK)
READ access time after SRCK
CONDITIONS
see Fig.3
MIN.
26
TYP. MAX. UNIT
Tcy(SWCK)
Tcy(SRCK)
tACC
−
−
ns
ns
ns
V
see Fig.10
see Fig.10
26
−
−
−
−
21
3.6
5.5
70
VDD, VDD(O) supply voltage (pins 19 and 22)
3.0
3.0
−
3.3
3.3
22
VDD(P)
IDD(tot)
supply voltage (pins 20 and 21)
total supply current
V
minimum read/write cycle;
outputs open
mA
(IDD(tot) = IDD + IDD(O) + IDD(P)
)
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA4955TJ
SOJ40
plastic small outline package; 40 leads (J-bent); body width 10.16 mm
SOT449-1
1999 Apr 29
2
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
BLOCK DIAGRAM
D0 to D11
12
IE
18
WE
17
RSTW SWCK
16 15
14 to 3
IE internal
DATA INPUT AND
WRITE MASK
BUFFER (×13)
3
INPUT BUFFER
SERIAL WRITE CONTROLLER
(×3)
write
control
write
acknowledge
load write
block
address
mini cache write control + cache transfer
IE
internal
D0
12 + 1
SERIAL WRITE REGISTER
20-WORD (×13)
+3.3 V
internal
CLOCK
OSCILLATOR
V
DD 19
20 × (12 + 1)
V
V
V
DD(P) 20
DD(P) 21
refresh clock
PARALLEL WRITE REGISTER
20-WORD (×13)
D0
internal
IE
DD(O) 22
20 × (12 + 1)
internal
WRITE MINI CACHE
12-WORD (×12)
WRITE ADDRESS
COUNTER
100 nF
MEMORY
ARBITRATION
LOGIC
cache
transfer
MEMORY ARRAY
245760-WORD (×12)
12
REFRESH ADDRESS
COUNTER
READ MINI CACHE
12-WORD (×12)
READ ADDRESS
COUNTER
GND
P
1
20 × 12
OE
internal
GND
2
PARALLEL READ REGISTER
GND
O
39
40
20-WORD (×12)
SAA4955TJ
GND
P
20 × 12
12
SERIAL READ REGISTER
20-WORD (×12)
12
load read
block
address
read
control
read
acknowledge
mini cache read control
DATA MUX
OE
internal
3
DATA OUTPUT
INPUT BUFFER
SERIAL READ CONTROLLER
BUFFER (×12)
(×4)
27 to 38
12
23 24 25 26
MGK676
RE
SRCK
RSTR
Q0 to Q11
OE
Pins 20 and 21 (VDD(P)) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance,
5.5 V instead of 3.3 V. Pins 19 and 22 (VDD and VDD(O)) require a 3.3 V supply.
Fig.1 Block diagram.
1999 Apr 29
3
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
PINNING
SYMBOL
PIN
I/O
ground
DESCRIPTION
GNDP
GND
D11
D10
D9
1
ground for protection circuits
general purpose ground
data input 11
data input 10
data input 9
2
ground
3
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
digital input
supply
4
5
D8
6
data input 8
D7
7
data input 7
D6
8
data input 6
D5
9
data input 5
D4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
data input 4
D3
data input 3
D2
data input 2
D1
data input 1
D0
data input 0
SWCK
RSTW
WE
IE
serial write clock
write reset clock
write enable
input enable
VDD
VDD(P)
VDD(P)
VDD(O)
OE
+3.3 V general purpose supply voltage (see figure note in Fig.1)
supply
+3.3 to 5.5 V supply voltage for protection circuits (see figure note in Fig.1)
supply
+3.3 to 5.5 V supply voltage for protection circuits
+3.3 V supply voltage for output circuits
output enable
supply
digital input
digital input
digital input
digital input
digital output
digital output
digital output
digital output
digital output
digital output
digital output
digital output
digital output
digital output
digital output
digital output
ground
RE
read enable
RSTR
SRCK
Q0
reset read
serial read clock
data output 0
Q1
data output 1
Q2
data output 2
Q3
data output 3
Q4
data output 4
Q5
data output 5
Q6
data output 6
Q7
data output 7
Q8
data output 8
Q9
data output 9
Q10
Q11
GNDO
GNDP
data output 10
data output 11
ground for output circuits
ground for protection circuits
ground
1999 Apr 29
4
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, halfpage
GND
GND
GND
1
2
40
39
P
P
GND
D11
D10
D9
O
3
38 Q11
37 Q10
36 Q9
35 Q8
34 Q7
4
5
D8
6
D7
7
D6
33
32
31
30
29
28
27
26
25
24
23
22
21
Q6
Q5
Q4
Q3
Q2
Q1
Q0
8
D5
9
D4
10
11
12
13
14
15
16
17
18
19
20
SAA4955TJ
D3
D2
D1
D0
SWCK
RSTW
WE
IE
SRCK
RSTR
RE
OE
V
V
DD
DD(O)
V
V
DD(P)
DD(P)
MGK675
Fig.2 Pin configuration.
1999 Apr 29
5
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
at the 17th positive transition of SWCK. A write latency
period of 18 additional SWCK clock cycles is required
before write access to the new block address is possible.
During this time, data is transferred from the serial write
and parallel write registers into the memory array and the
write pointer is set to the new block address.
FUNCTIONAL DESCRIPTION
Write operation
Write operations are controlled by the SWCK, RSTW, WE
and IE signals. A write operation starts with a reset write
address pointer (RSTW) operation, followed by a
sequence SWCK clock cycles during which time WE and
IE must be held HIGH. Write operations between two
successive reset write operations must contain at least
40 SWCK write clock cycles while WE is HIGH. To transfer
data temporarily stored in the serial write registers to the
memory array, a reset write operation is required after the
last write operation.
Block address values between 0 and 6143 are valid.
Values outside this range must be avoided because invalid
block addresses can result in abnormal operation or a
lock-up condition. Recovery from lock-up requires a
standard reset write operation.
WE must remain LOW from the 3rd positive transition of
SWCK to the 17th write latency SWCK clock cycle if the
block address is applied to pin D0. If the block address is
applied to pin IE, WE must be HIGH on the 5th positive
transition of SWCK, may be HIGH or LOW on the 6th
transition, and must be LOW from the 7th transition to the
17th write latency SWCK clock cycle.
RESET WRITE: RSTW
The first positive transition of SWCK after RSTW goes
from LOW to HIGH resets the write address pointer to the
lowest address (−12 decimal), regardless of the state of
WE (see Figs 3 and 4). RSTW set-up (tsu(RSTW)) and hold
(th(RSTW)) times are referenced to the rising edge of SWCK
(see Fig.3). The reset write operation may also be
At the 18th write latency SWCK clock cycle, IE and WE
may be switched HIGH to prepare for writing new data at
the next positive transition of SWCK. The complete write
block access entry sequence is finished after the
18th write latency cycle.
asynchronously related to the SWCK signal if WE is LOW.
RSTW needs to stay LOW for a single SWCK cycle before
another reset write operation can take place. If RSTW is
HIGH for 1024 SWCK write clock cycles while WE is
HIGH, the SAA4955TJ will enter a built-in test mode and
will not be in regular operation.
The LOW-to-HIGH transition on RSTW required at the
beginning of the sequence should not be repeated.
Additional LOW-to-HIGH transitions on RSTW would
disable write block address mode and reset the write
pointer.
RANDOM WRITE BLOCK ACCESS MODE
The SAA4955TJ will enter random write block access
mode if the following signal sequence is applied to control
inputs IE and WE during the first four SWCK write clock
cycles after a reset write (see Figs 5 and 6):
ADDRESS ORGANIZATION
Two different types of memory are used in the data
address area: a mini cache for the first 12 data words after
a reset write or a reset read, and a DRAM cell memory
array with a 245760 word capacity. Each word is 12 bits
long. The mini cache is needed to store data immediately
after a reset operation since a latency period is required
before read or write access to the memory array is
possible. Latency periods are needed for read or write
operations in random read or write block access modes
because data is read from, or written to, the memory array.
The data in the mini cache can only be accessed directly
after a standard reset operation. It cannot be accessed in
random read or write block access modes.
At the 1st and 2nd positive transitions of SWCK,
IE must be LOW and WE must be HIGH
At the 3rd and 4th positive transitions of SWCK,
IE must be HIGH and WE must be LOW
At the 5th positive transition of SWCK, the state of WE
determines which input pin is used for the block address.
If WE is LOW the Most Significant Bit (MSB) of the block
address must be applied to the D0 input pin. If WE is
HIGH, the Most Significant Bit (MSB) of the block
address is applied to pin IE.
The address area reserved for the mini cache, accessible
after a standard reset operation, is from decimal −12 to −1.
The memory array starts at decimal 0 and ends at 245759.
Decimal address 0 is identical to block address 0000H.
Because a single block address is defined for every
40 words in the memory array, block address 0001H
During the first four clock cycles, control signals WE and
IE will function as defined for normal operation. The
remaining 12 bits of the 13-bit write block address must be
applied, in turn, to the selected input pin (D0 or IE) at the
following 12 positive transitions of SWCK. The Least
Significant Bit (LSB) of the write block address is applied
1999 Apr 29
6
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
corresponds to decimal address 40. The highest block
address is 17FFH. This block has a decimal start address
of 245720 and an end address 245759.
RESET READ: RSTR
The first positive transition of SRCK after RSTR goes from
LOW to HIGH resets the read address pointer to the lowest
address (−12 decimal; see Figs 10 and 11). If RE is LOW,
however, the reset read operation to the lowest address
will be delayed until the first positive transition of SRCK
after RE goes HIGH. RSTR set-up (tsu(RSTR)) and hold
(th(RSTR)) times are referenced to the rising edge of SRCK
(see Fig.10). The reset read operation may also be
asynchronously related to the SRCK signal if RE is LOW.
If a read or write reset operation is not performed, the next
read or write pointer address after 245759 will be
address 0 due to pointer wraparound. Note that reset read
and reset write operations should occur in a single
sequence. If one pointer wraps around while the other is
reset, either 12 words will be lost or 12 words of undefined
data will be read.
RSTR needs to stay LOW for a single SRCK cycle before
another reset read operation can take place.
DATA INPUTS: D0 TO D11 AND WRITE CLOCK: SWCK
A positive transition on the SWCK write clock latches the
data on inputs D0 to D11, provided WE was HIGH at the
previous positive transition of SWCK. The data input
set-up (tsu(D)) and hold (th(D)) times are referenced to the
positive transition of SWCK (see Fig.4). The latched data
will only be written into memory if IE was HIGH at the
previous positive transition of SWCK.
RANDOM READ BLOCK ACCESS MODE
The SAA4955TJ will enter random read block access
mode if the following signal sequence is applied to control
inputs RE and OE during the first four SRCK read clock
cycles after a reset read (see Fig.12):
At the 1st and 2nd positive transitions of SRCK,
OE must be LOW and RE must be HIGH
WRITE ENABLE: WE
At the 3rd and 4th positive transitions of SRCK,
OE must be HIGH and RE must be LOW.
Pin WE is used to enable or disable a data write operation.
The WE signal controls data inputs D0 to D11. In addition,
the internal write address pointer is incremented if WE is
HIGH at the positive transition of the SWCK write clock.
WE set-up (tsu(WE)) and hold (th(WE)) times are referenced
to the positive edge of SWCK (see Fig.7).
During this time, control signals RE and OE will function as
defined for normal operation. The Most Significant Bit
(MSB) of the block read address is applied to the OE input
pin at the 5th positive transition of SRCK. The remaining
12 bits of the 13-bit read block address must be applied, in
turn, to OE at the following 12 positive transitions of SRCK.
The Least Significant Bit (LSB) of the block address is
applied at the 17th positive transition of SRCK. A read
latency period of 20 additional SRCK clock cycles is
required before read access to the new block address is
possible. During this period, data is transferred from the
memory array to the serial read and parallel read registers
and the read pointer is set to the new block address.
INPUT ENABLE: IE
Pin IE is used to enable or disable a data write operation
from the D0 to D11 data inputs into memory. The latched
data will only be written into memory if the IE and WE
signals were HIGH during the previous positive transition
of SWCK. A LOW level on IE will prevent the data being
written into memory and existing data will not be
overwritten (write mask function; see Fig.9). The IE set-up
(tsu(IE)) and hold (th(IE)) times are referenced to the positive
edge of SWCK (see Fig.8).
Block address values between 0 and 6143 are valid.
Values outside this range must be avoided because invalid
block addresses can result in abnormal operation or a
lock-up condition. Recovery from lock-up requires a
standard reset read operation.
Read operation
Read operations are controlled by the SRCK, RSTR, RE
and OE signals. A read operation starts with a reset read
address pointer (RSTR) operation, followed by a
sequence of SRCK clock cycles during which time RE and
OE must be held HIGH. Read operations between two
successive reset read operations must contain at least
20 SRCK read clock cycles while RE is HIGH.
The data output pins are not controlled by the OE pin and
are forced into high impedance mode from the 3rd to
the 17th positive transition of SRCK. OE should be held
LOW during the read latency period. RE must remain LOW
from the 3rd positive transition of SRCK to the 20th read
latency SRCK clock cycle.
After the 20th read latency SRCK clock cycle, RE and OE
may be switched HIGH to prepare for reading new data
1999 Apr 29
7
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
from the new address block at the next positive transition
of SRCK. The complete read block access entry sequence
is finished after the 20th read latency cycle.
operations (SWCK) followed by a reset write operation
(RSTW). Read and write initialization may be performed
simultaneously.
The LOW-to-HIGH transition on RSTR required at the
beginning of the sequence should not be repeated.
Additional LOW-to-HIGH transitions on RSTR would
disable read block address mode and reset the read
pointer.
If initialization starts earlier than the recommended 100 µs
after power-up, the initialization sequence described
above must be repeated, starting with an additional reset
read operation and an additional reset write operation after
the 100 µs start-up time.
DATA OUTPUTS: Q0 TO Q11 AND READ CLOCK: SRCK
Old and new data access
The new data is shifted out of the data output registers on
the rising edge of the SRCK read clock provided RE and
OE are HIGH. Data output pins are low impedance if OE is
HIGH. If OE is LOW, the data outputs are high impedance
and the data output bus may be used by other devices.
Data output hold (th(Q)) and access (tACC) times are
referenced to the positive transition of SRCK. The output
data becomes valid after access time interval tACC (see
Fig.11).
A minimum delay of 40 SWCK clock cycles is needed
before newly written data can be read back from memory
(see Fig.15). If a reset read operation (RSTR) occurs in a
read cycle before a reset write operation (RSTW) in a write
cycle accessing the same memory location, then old data
will be read.
Old data will be read provided a data read cycle begins
within 20 pointer positions of the start of a write cycle. This
means that if a reset read operation begins within
20 SWCK clock cycles after a reset write operation, the
internal buffering of the SAA4955TJ will ensure that old
data will be read out (see Fig.16).
Data output pins Q0 to Q11 are TTL compatible with the
restriction that when the outputs are high impedance, they
must not be forced higher than VDD(O) + 0.5 V or 5.0 V
absolute. The output data has the same polarity as the
incoming data at inputs D0 to D11.
New data will be read if the read pointer is delayed by
40 pointer positions or more after the write pointer. Old
data is still read out if the write pointer is less than or equal
to 20 pointer positions ahead of the read pointer (internal
buffering). A write pointer to read pointer delay of more
than 20 but less than 40 pointer positions should be
avoided. In this case, the old or the new data may be read,
or a combination of both.
READ ENABLE: RE
RE is used to increment the read pointer. Therefore, RE
needs to be HIGH at the positive transition of SRCK. When
RE is LOW, the read pointer is not incremented. RE set-up
(tsu(RE)) and hold (th(RE)) times are referenced to the
positive edge of SRCK (see Fig.13).
In random read and write block access modes, the
minimum write-to-read new data delay of 40 SWCK clock
cycles must be inserted for each block.
OUTPUT ENABLE: OE
OE is used to enable or disable data outputs Q0 to Q11.
The data outputs are enabled (low impedance) if OE is
HIGH. OE LOW disables the data output pins (high
impedance). Incrementing of the read pointer does not
depend on the status of OE. OE set-up (tsu(OE)) and hold
(th(OE)) times are referenced to the positive edge of SRCK
(see Fig.14).
Memory arbitration logic and self-refresh
Since the data in the memory array is stored in DRAM
cells, it needs to be refreshed periodically. Refresh is
performed automatically under the control of internal
memory arbitration logic which is clocked by a free running
clock oscillator. The memory arbitration logic controls
memory access for read, write and refresh operations.
It uses the contents of the write, read and refresh address
counters to access the memory array to load data from the
parallel write register, store data in the parallel read
register, or to refresh stored data. The values in these
counters correspond to block addresses.
Power-up and initialization
Reliable operation is not guaranteed until at least 100 µs
after power-up, the time needed to stabilize VDD within the
recommended operating range. After the 100 µs power-up
interval has elapsed, the following initialization sequence
must be performed: a minimum of 12 dummy read
operations (SRCK cycles) followed by a reset read
operation (RSTR), and a minimum of 12 dummy write
1999 Apr 29
8
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
continuously for 1024 SWCK clock cycles, the
Cascade operation
SAA4955TJ will enter test mode. It will exit test mode if WE
is LOW for a single SWCK cycle or if RSTW is LOW for
2 SWCK clock cycles.
If a longer delay is needed, the total storage depth can be
increased beyond 2949264 bits by cascading several
SAA4955TJs. For details see the interconnection and
timing diagrams (Figs 17 and 18).
Test mode operation
The SAA4955TJ incorporates a test mode not intended for
customer use. If WE and RSTW are held HIGH
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS
VDD, VDD(O) supply voltages
MIN.
−0.5
MAX.
+5
UNIT
V
V
V
V
V
V
VDD(P)
VI
supply voltage for protection circuits
−0.5
−0.5
+5.5
+5.5
+3.8
+5
input voltage
VDD(P) = 5 V
V
DD = VDD(O) = VDD(P) = 3.3 V −0.5
VDD(P) = 5 V −0.5
DD = VDD(O) = VDD(P) = 3.3 V −0.5
VO
output voltage
V
+3.8
200
+0.5
IDD(tot)
total supply current
−
mA
V
∆V
voltage difference between GND,
GNDO and GNDP
−0.5
IO
short circuit output current
total power dissipation
storage temperature
junction temperature
ambient temperature
electrostatic handling
−
50
mA
mW
°C
°C
°C
V
Ptot
Tstg
Tj
−
750
−20
0
+150
125
Tamb
Ves
0
70
note 1
note 2
−150
−2000
+200
+2000
V
Notes
1. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (‘0 Ω’ is actually
0.75 µH + 10 Ω).
2. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
60
K/W
1999 Apr 29
9
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
CHARACTERISTICS
VDD = VDD(O) = VDD(P) = 3.0 to 3.6 V; Tamb = 0 to 70 °C; 3 ns input transition times; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.(1)
MAX.
UNIT
VDD, VDD(O) supply voltages (pins 19 and 22)
3.0
3.3
3.3
22
3.6
5.5
70
V
V
VDD(P)
IDD(tot)
supply voltage (pins 20 and 21)
3.0
total supply current
minimum write/read
cycle; outputs open
−
mA
(IDD(tot) = IDD + IDD(O) + IDD(P)
operating supply current
stand-by supply current
)
IDD
minimum write/read cycle −
20
3
60
10
mA
mA
IDDstd
after 1 RSTW/RSTR
cycle; WE, RE and
OE LOW
−
IDD(O)
IDD(P)
supply current
supply current
minimum write/read
cycle; outputs open
−
−
2
0
10
1
mA
mA
Inputs (pins 3 to 18 and 23 to 26)
VIH
VIL
ILI
HIGH-level input voltage
LOW-level input voltage
input leakage current
input capacitance
2.0
−0.5
−10
−
−
−
−
−
VDD(P) + 0.3 V
+0.8
+10
7
V
VI = 0 V to VDD(P)
f = 1 MHz; VI = 0 V
µA
pF
Ci
Outputs (pins 27 to 38)
VOH
VOL
ILO
HIGH-level output voltage
IOH = −5 mA
2.4
−
−
−
−
−
V
LOW-level output voltage
output leakage current
IOL = 4.2 mA
0.4
+10
V
VO = 0 V to VDD(Q)
RE and OE LOW
;
−10
µA
Co
output capacitance
f = 1 MHz; VO = 0 V
−
−
10
pF
Write cycle timing; note 2
Tcy(SWCK)
tW(SWCKH)
tW(SWCKL)
tsu(D)
SWCK cycle time
see Fig.3
see Fig.3
see Fig.3
see Fig.3
26
7
−
−
−
−
−
−
−
−
ns
ns
ns
ns
SWCK HIGH pulse width
SWCK LOW pulse width
7
set-up time data inputs
(D0 to D11)
5
th(D)
hold time data inputs (D0 to D11) see Fig.3
3
5
3
5
3
8
5
3
8
−
−
−
−
−
−
−
−
−
−
3
−
−
−
−
−
−
−
−
−
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(RSTW)
th(RSTW)
tsu(WE)
th(WE)
tW(WEL)
tsu(IE)
th(IE)
set-up time RSTW
hold time RSTW
set-up time WE
see Fig.3
see Fig.3
see Fig.7
see Fig.7
see Fig.7
see Fig.8
see Fig.8
see Fig.8
see Fig.3
hold time WE
WE LOW pulse width
set-up time IE
hold time IE
tW(IEL)
tt
IE LOW pulse width
transition time (rise and fall)
1999 Apr 29
10
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.(1)
MAX.
UNIT
Read cycle timing; note 3
tACC
access time after SRCK
see Fig.10
−
−
−
3
−
21
21
12
−
ns
ten(Q)
output enable time after SRCK
output disable time after SRCK
output hold time after SRCK
SRCK cycle time
see Fig.14
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tdis(Q)
note 4; see Fig.14
see Fig.10
th(Q)
Tcy(SRCK)
tW(SRCKH)
tW(SRCKL)
tsu(RSTR)
th(RSTR)
tsu(RE)
th(RE)
see Fig.10
26
7
7
5
3
5
3
9
5
3
9
−
−
HIGH-level pulse width of SRCK see Fig.10
LOW-level pulse width of SRCK see Fig.10
−
−
set-up time RSTR
hold time RSTR
see Fig.10
see Fig.10
see Fig.13
see Fig.13
see Fig.13
see Fig.14
see Fig.14
see Fig.14
see Fig.10
−
−
set-up time RE
−
hold time RE
−
tW(REL)
tsu(OE)
th(OE)
LOW-level pulse width of RE
set-up time OE
−
−
hold time OE
−
tW(OEL)
tt
LOW-level pulse width of OE
transition time (rise and fall)
−
30
Notes
1. Typical values are valid for Tamb = 25 °C, VDD = VDD(O) = VDD(P) = 3.3 V, all voltages referenced to GND. See Fig.1
for configuration.
2. The write cycle timing set-up and hold times are related to VIL of the rising edge of SWCK. They are valid for the
specified LOW- and HIGH-level input voltages (VIL and VIH).
3. The read cycle timing set-up and hold times are related to VIL of the rising edge of SRCK. They are valid for the
specified LOW- and HIGH-level input voltages (VIL and VIH). The load on each output is a 30 pF capacitor to ground
in parallel with a 218 Ω resistor to 1.31 V.
4. Disable times specified are from the initiating edge until the output is no longer driven by the memory. Disable times
are measured by observing the output waveforms. Low values of load resistor and capacitor have to be used to
obtain a short time constant.
1999 Apr 29
11
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N − 2
N − 1
1
2
N
T
cy(SWCK)
−V
IH
SWCK
−V
IL
t
t
h(RSTW)
t
t
t
t
su(RSTW)
w(SWCKH) w(SWCKL)
t
t
su(RSTW)
h(RSTW)
−V
IH
RSTW
−V
IL
t
su(D)
t
h(D)
−V
IH
D0 to D11
N − 2
N − 1
N
1
2
−V
IL
−V
IH
WE
IE
−V
IL
−V
IH
−V
IL
MGK677
Fig.3 Write cycle timing diagram (reset write).
N − 1
disable
disable
1
N
T
cy(SWCK)
−V
IH
SWCK
RSTW
−V
IL
t
t
w(SWCKL)
w(SWCKH)
−V
IH
−V
IL
−V
IH
D0 to D11
N − 1
N
1
−V
IL
−V
IH
WE
IE
−V
IL
−V
IH
−V
IL
MGK678
Fig.4 Write cycle timing diagram (reset write with WE LOW).
12
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
start
sequence
(4 SWCK)
serial input of write block address
(13 SWCK)
write latency
(minimum 18 SWCK)
write data
1
2
3
4
5
17 18 19
34 35 36
SWCK
RSTW
WE
WE LOW: D0 controlled
IE
random write block address
write data
D0
MSB
LSB
0
0
1
2
3
at block address:
write data
1
2
3
D1 to D11
MGK679
Fig.5 D0 controlled entry sequence of random write block access mode.
start
sequence
(4 SWCK)
serial input of write block address
(13 SWCK)
write latency
(minimum 18 SWCK)
write data
1
2
3
4
5
17 18 19
34 35 36
SWCK
RSTW
WE
WE HIGH: IE controlled
random write block address
MSB
LSB
IE
at block address:
write data
0
1
2
3
D0 to D11
MGK680
Fig.6 IE controlled entry sequence of random write block access mode.
13
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N − 1
disable
disable
N + 1
N
−V
IH
SWCK
−V
IL
t
t
h(WE)
t
h(WE)
su(WE)
t
su(WE)
−V
IH
WE
−V
IL
t
w(WEL)
t
su(D)
t
h(D)
−V
−V
IH
IL
D0 to D11
N − 1
N + 1
N
−V
−V
IH
IL
IE
−V
−V
IH
IL
RSTW
MGK681
Fig.7 Write cycle timing diagram (write enable).
N − 1
disable
disable
N + 3
N
−V
IH
SWCK
−V
IL
t
t
h(IE)
t
h(IE)
su(IE)
t
su(IE)
−V
−V
IH
IL
IE
t
w(IEL)
t
su(D)
t
h(D)
−V
−V
IH
IL
D0 to D11
N − 1
N + 3
N
−V
−V
IH
IL
WE
−V
−V
IH
IL
RSTW
MGK682
Fig.8 Write cycle timing diagram (input enable = write mask operation).
14
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
SWCK
−V
IH
−V
IL
−V
IH
IE
−V
IL
−V
IH
WE
−V
IL
−V
IH
D0 to D11
RSTW
N
N + 1
N + 2
N + 3
N + 6
N + 7
N + 8
−V
IL
−V
−V
IH
IL
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
−V
−V
IH
IL
SRCK
−V
−V
IH
IL
OE
−V
−V
IH
IL
RE
new
N
new
old
old
new
N + 6
new
N + 7
new
−V
−V
high-Z
IH
IL
Q0 to Q11
N + 3
N + 4
N + 5
N + 8
−V
−V
IH
IL
RSTR
MGK683
Fig.9 Write mask operation.
15
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N − 1
1
2
3
N
T
cy(SRCK)
−V
IH
SRCK
−V
IL
t
t
h(RSTR)
t
t
w(SRCKH)
t
t
su(RSTR)
t
t
su(RSTR)
w(SRCKL)
h(RSTR)
−V
IH
RSTR
−V
IL
t
t
h(Q)
ACC
−V
IH
Q0 to Q11
N − 2
N − 1
N
1
2
−V
IL
−V
IH
RE
−V
IL
−V
IH
OE
−V
IL
MGK684
Fig.10 Read cycle timing diagram (reset read).
N
N
1
2
N
T
cy(SRCK)
−V
IH
SRCK
−V
IL
t
w(SRCKH)
t
−V
w(SRCKL)
IH
RSTR
−V
IL
t
t
ACC
ACC
−V
IH
Q0 to Q11
N − 1
N
1
−V
IL
−V
IH
RE
−V
IL
−V
IH
OE
−V
IL
MGK685
Fig.11 Read cycle timing diagram (reset read with RE LOW).
16
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
start
sequence
(4 SRCK)
serial input of read block address
(13 SRCK)
read latency
(minimum 20 SRCK)
read data
1
2
3
4
5
17 18 19
36 37 38
SRCK
RSTR
RE
random read block address
MSB
LSB
OE
at block address:
read data
high-Z
0
1
2
Q0 to Q11
MGK686
Fig.12 Entry sequence of random read block access mode.
N
N
N + 1
N + 2
N
−V
IH
SRCK
−V
IL
t
t
h(RE)
t
h(RE)
su(RE)
t
su(RE)
−V
IH
RE
−V
IL
t
t
w(REL)
ACC
−V
IH
Q0 to Q11
N − 1
N + 1
N
−V
IL
−V
IH
OE
−V
IL
−V
IH
RSTR
−V
IL
MGK687
Fig.13 Read cycle timing diagram (read enable).
17
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N
disable
N + 3
N + 4
disable
−V
IH
SRCK
−V
IL
t
t
h(OE)
t
h(OE)
su(OE)
t
su(OE)
−V
IH
OE
−V
IL
t
t
w(OEL)
ACC
t
t
dis(Q)
en(Q)
−V
high-Z
IH
Q0 to Q11
N − 1
N + 3
N
−V
IL
−V
IH
RE
−V
IL
−V
IH
RSTR
−V
IL
MGK688
Fig.14 Read cycle timing diagram (output enable).
1999 Apr 29
18
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
1
2
3
39
40
41
42
SWCK
−V
IH
−V
IL
−V
IH
RSTW
−V
IL
−V
IH
WE and IE
D0 to D11
−V
IL
new
1
new
new
new
39
new
40
new
new
−V
IH
2
3
41
42
−V
IL
minimum number of SWCK cycles delay to get new data
1
2
3
−V
IH
SRCK
−V
IL
−V
IH
RSTR
−V
IL
−V
IH
RE and OE
Q1 to Q11
−V
IL
new
1
new
−V
high-Z
IH
2
−V
IL
MGK689
Fig.15 New data access.
19
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
1
2
3
19
20
21
22
SWCK
−V
IH
−V
IL
−V
IH
RSTW
−V
IL
−V
IH
WE and IE
D0 to D11
−V
IL
new
1
new
new
new
19
new
20
new
new
−V
IH
2
3
21
22
−V
IL
maximum number of SWCK cycles delay to get old data
1
2
3
−V
IH
SRCK
−V
IL
−V
IH
RSTR
−V
IL
−V
IH
RE and OE
Q1 to Q11
−V
IL
old
1
old
−V
high-Z
IH
2
−V
IL
MGK690
Fig.16 Old data access.
20
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
reset
signal
serial
clock
RSTR
SRCK
RSTR
SRCK
RSTW
SWCK
RSTW
16
25
26
25
26
16
15
SWCK
15
SAA4955TJ
SAA4955TJ
D0 to D11
D0 to D11
Q0 to Q11
Q0 to Q11
data
inputs
data
outputs
27 to 38
14 to 3
14 to 3
27 to 38
12
WE
IE
12
12
RE
RE
OE
WE
IE
24
23
17
18
24
23
17
18
OE
enable
signal
MGK691
Fig.17 Cascade operation (signal connections).
write new data
read 2 times delayed old data
1
2
2
3
3
4
4
5
5
6
6
7
1
−V
SWCK
and
SRCK
IH
IL
−V
RSTW
and
RSTR
−V
−V
IH
IL
WE and IE
and
RE and OE
−V
−V
IH
IL
new
1
new
2
new
3
new
4
new
5
new
data
inputs
(×12)
−V
−V
IH
IL
6
old
1
old
2
old
3
old
4
old
5
old
6
data
outputs
(×12)
−V
−V
high-Z
IH
IL
MGK692
Fig.18 Cascade operation (timing waveforms).
21
1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
PACKAGE OUTLINE
SOJ40: plastic small outline package; 40 leads (J-bent); body width 10.16 mm
SOT449-1
X
D
c
e
E
y
b
p
b
1
A
40
21
w
M
H
E
E
A
A
2
1
A
pin 1 index
(A )
3
1
20
L
p
Z
D
e
detail X
v
M
A
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
A
max.
(1)
(1)
A
1
A
2
A
3
b
b
1
c
D
E
e
e
H
L
v
w
y
Z
D
UNIT
p
E
E
p
1.40
1.14
2.29
2.18
0.51
0.38
0.81
0.66
0.32
0.18
26.2
25.9
10.3
10.0
11.30
11.05
1.4
1.1
1.19
0.73
0.25
mm
3.68
1.27
9.4
0.18
0.18
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-06-02
SOT449-1
MS027
1999 Apr 29
22
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Apr 29
23
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Apr 29
24
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
NOTES
1999 Apr 29
25
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
NOTES
1999 Apr 29
26
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
NOTES
1999 Apr 29
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
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Middle East: see Italy
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/00/02/pp28
Date of release: 1999 Apr 29
Document order number: 9397 750 05285
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SAA4955TJ; 2.9-Mbit field memory
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The SAA4955TJ is a 2949264-bit field memory designed for advanced TV applications such as 100/120 Hz TV, PALplus, PIP and 3D comb
filter. The maximum storage depth is 245772 words x 12 bits. A FIFO operation with full word continuous read and write could be used as a
data delay, for example. A FIFO operation with asynchronous read and write could be used as a data rate multiplier. Here the data is
written once, then read as many times as required without being overwritten by new data. In addition to the FIFO operations, a random
block access mode is accessible during the pointer reset operation. When this mode is enabled, reading and/or writing may begin at, or
proceed from, the start address of any of the 6144 blocks. Each block is 40 words in length. Two or more SAA4955TJs can be cascaded to
provide greater storage depth or a longer delay, without the need for additional circuitry.
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Datahandbook system
The SAA4955TJ contains separate 12-bit wide serial ports for reading and writing. The ports are controlled and clocked separately, so
asynchronous read and write operations are supported. Independent read and write clock rates are possible. Addressing is controlled by
read and write address pointers. Before a controlled write operation can begin, the write pointer must be set to zero or to the beginning of a
valid address block. Likewise, the read pointer must be set to zero or to the beginning of a valid address block before a controlled read
operation can begin.
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l 2949264-bit field memory
l 245772 x 12-bit organization
l 3.3 V power supply
SAA4955TJ
SAA4955TJ
l Inputs fully TTL compatible when using an extra 5 V power supply
l High speed read and write operations
l FIFO operations:
- full word continuous read and write
- independent read and write pointers (asynchronous read and write access)
- resettable read and write pointers
l Optional random access by block function (40 words per block) enabled during pointer reset operation
l Quasi static (internal self-refresh and clocking pauses of infinite length)
l Write mask function
l Cascade operation possible
l 16 Mbit CMOS DRAM process technology
l 40-pin SOJ Package.
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SAA4955TJ 2.9-Mbit field memory
29-Apr-99
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Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
SOT449 Full production
Standard Marking * Tube Dry
Pack
SAA4955TJ/V1 SAA4955TJDP
SAA4955TJDP-T
9352 498 00512
Standard Marking * Reel Dry
Pack, SMD, 13"
9352 498 00518
SOT449 Full production
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number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and
products from the same functional category.
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