935271531118 [NXP]
IC LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 5.30 MM, PLASTIC, MO-150, SOT-340-1, SSOP-24, Clock Driver;
| 型号： | 935271531118 |
| 厂家： | 
NXP |
| 描述： | IC LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 5.30 MM, PLASTIC, MO-150, SOT-340-1, SSOP-24, Clock Driver 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总17页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCK351
1:10 clock distribution device with 3-State outputs
Rev. 01 — 14 May 2002
Product data
1. Description
The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The
PCK351 enables a single clock input to be distributed to ten outputs with minimum
output skew and pulse skew. The use of distributed VCC and GND pins in the PCK351
ensures reduced switching noise.
The PCK351 is characterized for operation over the supply range 3.0 V to 3.6 V, and
over the industrial temperature range −40 to +85 °C.
2. Features
■ 1:10 LVTTL clock distribution
■ Low output to output skew
■ Low output pulse skew
■ Over voltage tolerant inputs and outputs
■ LVTTL-compatible inputs and outputs
■ Distributed VCC and ground pins reduce switching noise
■ Balanced High-drive outputs (−32 mA IOH, 32 mA IOL
)
■ Reduced power dissipation due to the state-of-the-art QuBICLP™ process
■ Supply range of +3.0 V to +3.6 V
■ Package options include plastic small-outline (D) and shrink small-outline (DB)
packages
■ Industrial temperature range −40 to +85 °C
■ PCK351 is identical to and replaces PTN3151.
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
Symbol
tPHL/tPLH
Ci
Parameter
Conditions
Min
Typ
4.5
4
Max
Unit
ns
propagation delay: A to Yn
input capacitance
CL = 50 pF; VCC = 3.3 V
VI = VCC or GND
VI = VCC or GND
CL = 50 pF; f = 1 MHz
-
-
-
-
-
-
-
-
pF
Co
output capacitance
power dissipation capacitance
6
pF
CPD
48
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
[2] The condition is VI = GND to VCC
.
4. Ordering information
Table 2:
Ordering information
Temperature range = −65 °C to +150 °C.
Type number
Package
Name
Description
plastic small outline package; 24 leads; body width 7.5 mm
plastic shrink small outline package; 24 leads; body width 5.3 mm
Version
PCK351D
SO24
SOT137-1
SOT340-1
PCK351DB
SSOP24
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
2 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
5. Pinning information
5.1 Pinning
GND
1
2
24 GND
GND
1
2
24 GND
Y
23
22
21
Y
V
Y
Y
23
22
21
Y
V
Y
10
1
10
1
V
3
V
3
CC
CC
2
CC
CC
2
Y
9
4
Y
9
4
OE
A
5
20 GND
OE
A
5
20 GND
6
19
18
Y
Y
6
19
18
Y
Y
3
4
3
4
GND
GND
7
GND
GND
7
8
17 GND
8
17 GND
Y
8
9
16
15
14
Y
V
Y
Y
8
9
16
15
14
Y
V
Y
5
5
V
10
11
V
10
11
CC
CC
6
CC
CC
6
Y
7
Y
7
GND 12
13 GND
GND 12
13 GND
002aaa280
002aaa281
Fig 1. SO24 pin configuration.
Fig 2. SSOP24 pin configuration.
5.2 Pin description
Table 3:
Symbol
Pin description
Pin
Description
GND
Y10 to Y1
VCC
1, 7, 8, 12, 13, 17, 20, 24
ground (0 V)
2, 4, 9, 11, 14, 16, 18, 19, 21, 23
outputs
3, 10, 15, 22
supply voltage
output enable input (Active-LOW)
data input
OE
5
6
A
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
3 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
6. Functional description
6.1 Function table
Table 4:
Function table
Inputs
Outputs
A
L
OE
Yn
Z
H
H
L
H
L
Z
L
H
L
H
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
6.2 Logic symbol
5
OE
EN
23
21
19
18
16
14
11
9
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1
2
3
4
5
6
7
8
9
10
6
A
4
2
002aaa283
Fig 3. Logic symbol.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
4 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
6.3 Logic diagram
5
OE
23
Y
1
21
Y
2
19
Y
3
18
Y
4
6
A
16
Y
5
14
Y
6
11
Y
7
9
Y
8
4
Y
9
2
Y
10
002aaa282
Fig 4. Logic diagram.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
5 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
7. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1], [2]
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
-
Max
+4.6
+7.0
+3.6
−18
−50
64
Unit
V
supply voltage range
input voltage range
output voltage range
input clamp current
output clamp current
output sink current
VCC or GND current
storage temperature
maximum power dissipation
SO package
[3]
[3]
V
VO
V
IIK
VI < 0 V
VI < 0 V
mA
mA
mA
mA
°C
IOK
-
IO
-
ICC, IGND
Tstg
PD
-
±75
+150
−65
Tamb = +55 °C
Tamb = +55 °C
-
-
0.65
1.7
W
W
SSOP package
[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated
under ‘recommended operating conditions’ is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum
junction temperature of this integrated circuit should not exceed 150 °C.
[3] The input and output negative voltage ratings may be exceeded if the input and output clamp currents
are observed.
8. Recommended operating conditions
Table 6:
Recommended operating conditions
See note 1.
Symbol
VCC
Parameter
Conditions
Min
3.0
2.0
0
Max
3.6
Unit
V
supply voltage
VIH
HIGH-level input voltage
input voltage
5.5
V
VI
0.8
V
Tamb
ambient temperature
see Table 7 “DC
characteristics”
and Table 8 “AC
characteristics”
per device
−40
+85
°C
tr, tf
input rise and fall times
VCC = 3.3 ±0.3 V
-
100
ns/V
[1] Unused pins (input or I/O) must be held HIGH or LOW.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
6 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
9. Static characteristics
Table 7:
DC characteristics
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = 25 °C.
Symbol
VIK
Parameter
Conditions
Min
Typ
Max
−1.2
-
Unit
V
input diode voltage
VCC = 3.0 V; II = −18 mA
-
-
-
-
-
-
-
VOH
VOL
ILI
HIGH-level output voltage VCC = 3.0 V; IOH = −32 mA
2.0
V
LOW-level output voltage
input leakage current
output leakage current
VCC = 3.0 V; IOL = 32 mA
VCC = 3.6 V; VI = GND or 5.5 V
VCC = 3.6 V; VO = 2.5 V
VCC = 3.6 V; VO = 3 V
-
0.5
V
-
±1.0
−150
±10
µA
mA
µA
ILO
−15
[1]
IOZ
3-State output OFF-state
current
-
ICC
quiescent supply current
VCC = 3.6 V; VI = VCC or GND; IO = 0;
outputs HIGH
-
-
-
-
-
-
0.3
25
0.3
-
mA
mA
mA
pF
V
CC = 3.6 V; VI = VCC or GND; IO = 0;
outputs LOW
CC = 3.6 V; VI = VCC or GND; IO = 0;
-
V
-
outputs disabled
CI
input capacitance
output capacitance
VCC = 3.3 V; VI = VCC or GND;
f = 10 MHz
4
6
CO
VCC = 3.3 V; VO = VCC or GND;
f = 10 MHz
-
pF
[1] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
7 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
10. Dynamic characteristics
Table 8:
GND = 0 V; tr = tf ≤ 3.0 ns.
Symbol Parameter
VCC = 3.3 V; Tamb = 25 °C
AC characteristics
Conditions
Min
Typ
Max
Unit
tPLH/tPHL
tPZH/tPZL
tPHZ/tPLZ
tsk(o)
propagation delay A to Yn
CL = 50 pF; see Figures 5 and 8
CL = 50 pF; see Figures 6 and 8
CL = 50 pF; see Figures 6 and 8
3.1
3.6
3.8
4.0
0.3
0.2
-
4.1
5.5
5.9
0.5
0.8
1
ns
ns
ns
ns
ns
ns
ns
ns
propagation delay OE to Yn
propagation delay OE to Yn
1.8
1.8
output-to-output skew A to Yn CL = 50 pF; see Figures 7 and 8
-
-
-
-
-
tsk(p)
pulse skew A to Yn
part-to-part skew A to Yn
rise time A to Yn
CL = 50 pF; see Figures 7 and 8
CL = 50 pF; see Figures 7 and 8
CL = 50 pF; see Figures 5 and 8
CL = 50 pF; see Figures 5 and 8
tsk(pr)
tr
-
-
tf
fall time A to Yn
-
-
VCC = 3.3 to 3.6 V; Tamb = 0 °C to +70 °C
tPLH/tPHL
tPZH/tPZL
tPHZ/tPLZ
tsk(o)
propagation delay A to Yn
propagation delay OE to Yn
propagation delay OE to Yn
CL = 50 pF; see Figures 5 and 8
CL = 50 pF; see Figures 6 and 8
CL = 50 pF; see Figures 6 and 8
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
1.3
5.9
6.3
0.5
0.8
1
1.7
output-to-output skew A to Yn CL = 50 pF; see Figures 7 and 8
-
-
-
-
-
tsk(p)
pulse skew A to Yn
part-to-part skew A to Yn
rise time A to Yn
CL = 50 pF; see Figures 7 and 8
CL = 50 pF; see Figures 7 and 8
CL = 50 pF; see Figures 5 and 8
CL = 50 pF; see Figures 5 and 8
tsk(pr)
tr
1.5
1.5
tf
fall time A to Yn
Table 9:
Switching characteristics
Temperature and VCC coefficients over recommended operating free-air temperature and VCC range; note 1.
Symbol
Parameter
Conditions
Max
Unit
∆tPLH(T)
temperature coefficient of LOW-to-HIGH propagation delay A to Yn
(average value)
note 2
65
ps/10 °C
∆tPHL(T)
∆tPLH(V)
∆tPHL(V)
temperature coefficient of HIGH-to-LOW propagation delay A to Yn
(average value)
note 2
note 3
note 3
45
ps/10 °C
VCC coefficient of LOW-to-HIGH propagation delay A to Yn
(average value)
−140
−120
ps/100 mV
ps/100 mV
VCC coefficient of HIGH-to-LOW propagation delay A to Yn
(average value)
[1] These data were extracted from characterization material and are not tested at the factory.
[2] ∆tPLH(T) and ∆tPHL(T) are virtually independent of VCC
.
[3] ∆tPLH(V) and ∆tPHL(V) are virtually independent of temperature.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
8 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
10.1 AC waveforms
3.0 V
0 V
A input
1.5 V
t
t
PLH
PHL
V
OH
2 V
Y
output
1.5 V
0.8 V
n
V
OL
t
t
f
r
002aaa289
Fig 5. The input (A) to outputs (Yn) propagation delays and rise and fall times.
3 V
OE input
1.5 V
0 V
CC
t
PZL
t
PLZ
V
output
1.5 V
LOW-to-OFF
OFF-to-LOW
V
+ 0.3 V
OL
V
V
OL
t
t
PZH
PHZ
V
OH
− 0.3 V
OH
output
1.5 V
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
outputs
outputs
disabled
disabled
disabled
002aaa290
Fig 6. 3-State enable and disable times.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
9 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
A input
Y
output
1
t
t
PHL1
t
t
PLH1
Y
Y
output
output
2
PHL2
PLH2
3
t
t
PHL3
t
t
PLH3
Y
Y
output
output
4
PHL4
PHL5
PHL6
PHL7
PHL8
PLH4
PLH5
PLH6
PLH7
PLH8
5
t
t
t
t
t
t
t
t
Y
Y
output
output
6
7
Y
Y
output
output
output
8
9
t
PHL9
t
PLH9
Y
10
002aaa286
t
t
PLH10
PHL10
(1) Output-to-output skew is the highest values of positive and negative edge skew:
tsk(o) = tPLHn(max) − tPLHn(min) and tsk(o) = tPHLn(max) − tPHLn(min) for n = 1 to 10.
(2) Output pulse skew is the highest value of: tsk(p) = |tPLHn − tPHLn| for n = 1 to 10.
(3) Part-to-part skew tsk(pr) represents the positive and negative edge skew between outputs of several devices operating under
identical conditions.
Fig 7. Calculation of tsk(o), tsk(p), and tsk(pr)
.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
10 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
6 V
S1
open
V
CC
GND
500 Ω
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
50 pF
L
R
500 Ω
T
002aaa285
TEST
S1
t
t
t
/t
open
PLH PHL
/t
6 V
PLZ PZL
/t
GND
PHZ PZH
Fig 8. Load circuitry for switching times.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
11 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
11. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-05-22
99-12-27
SOT137-1
075E05
MS-013
Fig 9. SO24 package outline (SOT137-1).
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
12 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2.0
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
99-12-27
SOT340-1
MO-150
Fig 10. SSOP24 package outline (SOT340-1).
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
13 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferable be kept below 220 °C for thick/large
packages, and below 235 °C small/thin packages.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
14 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
12.5 Package related soldering information
Table 10: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
Wave
Reflow[2]
suitable
suitable
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
not suitable[3]
PLCC[4], SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
suitable
not recommended[4][5]
not recommended[6]
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[3] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[4] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[5] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[6] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
13. Revision history
Table 11: Revision history
Rev Date
CPCN
-
Description
01 20020514
Product data; initial version. Engineering Change Notice 853-2344 28198.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
15 of 17
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
14. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
15. Definitions
16. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
16 of 17
9397 750 09791
Product data
Rev. 01 — 14 May 2002
PCK351
1:10 clock distribution device with 3-State outputs
Philips Semiconductors
Contents
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.1
6.2
6.3
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
8
9
10
10.1
11
12
12.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 15
Package related soldering information . . . . . . 15
12.2
12.3
12.4
12.5
13
14
15
16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
© Koninklijke Philips Electronics N.V. 2002.
Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 14 May 2002
Document order number: 9397 750 09791
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