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INTEGRATED CIRCUITS

PCA9500

8-bit I²C and SMBus I/O port with

2-kbit EEPROM

Product data

2002 Sep 27

Philips

Semiconductors

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

DESCRIPTION

The PCA9500 is an 8-bit I/O expander with an on-board 2-kbit

EEPROM.

The I/O expander’s eight quasi bidirectional data pins can be

independently assigned as inputs or outputs to monitor board level

status or activate indicator devices such as LEDs. The system

master writes to the I/O configuation bits in the same way as for the

PCF8574. The data for each Input or Output is kept in the

corresponding Input or Output register. The system master can read

all registers.

FEATURES

The EEPROM can be used to store error codes or board

manufacturing data for read-back by application software for

diagnostic purposes and is included in the I/O expander package.

• 8 general purpose input/output expander/collector

• Drop in replacement for PCF8574 with integrated 2-kbit EEPROM

• Internal 256 × 8 EEPROM

The PCA9500 has three address pins with internal pull-up resistors

2

allowing up to 8 devices to share the common two-wire I C software

2

• Self timed write cycle

protocol serial data bus. The fixed GPIO I C address is the same as

2

the PCF8574 and the fixed EEPROM I C address is the same as

• 4 byte page write operation

the PCF8582C-2, so the PCA9500 appears as two separate devices

to the bus master.

2

• I C and SMBus interface logic

• Internal power-on reset

• Noise filter on SCL/SDA inputs

• 3 address pins allowing up to 8 devices on the I C/SMBus

• No glitch on power-up

The PCA9500 supports hot insertion to facilitate usage in removable

cards on backplane systems.

2

The PCA9501 is an alternative to the functionally similar PCA9500

for systems where a higher number of devices are required to share

2

the same I C-bus or an interrupt output is required.

• Supports hot insertion

• Power-up with all channels configured as inputs

• Low standby current

• Operating power supply voltage range of 2.5 V to 3.6 V

• 5 V tolerant inputs/outputs

• 0 to 400 kHz clock frequency

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

• Package offer: SO16, TSSOP16

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

16-Pin Plastic SO (wide)

16-Pin Plastic TSSOP

–40 to +85 °C

PCA9500D

PC9500

SOT162-1

SOT403-1

PCA9500PW

Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.

2

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I C patent.

2

I C is a trademark of Philips Semiconductors Corporation.

2

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

PIN CONFIGURATION

PIN DESCRIPTION

NUMBER

SYMBOL

NAME AND FUNCTION

V

1

16

DD

A0

1,2,3

A0–2

Address lines (internal pull-up)

Quasi-bidirectional I/O pins

Supply ground

A1

2

3

4

5

6

7

8

15 SDA

4,5,6,7

I/O0–3

SCL

14

A2

8

V

SS

WC

13

I/O0

9,10,11,12

I/O4–7

WC

Quasi-bidirectional I/O pins

Active low write control pin

PCA9500

I/O7

I/O6

I/O1

12

11

10

9

13

14

15

16

I/O2

I/O3

2

SCL

I C Serial Clock

I/O5

I/O4

2

SDA

I C Serial Data

V

SS

V

DD

Supply Voltage

SW00902

Figure 1. Pin configuration

BLOCK DIAGRAM

PCA9500

300 k Ω

A0

A1

A2

I/O0

I/O1

I/O2

I/O3

SCL

SDA

INPUT

FILTER

INPUT/

OUTPUT

PORTS

8-BIT

2

I C/SMBus

CONTROL

I/O4

I/O5

WRITE pulse

READ pulse

I/O6

I/O7

V

DD

V

SS

POWER-ON

RESET

EEPROM

256 x 8

WC

SW01074

Figure 2. Block diagram

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

FUNCTIONAL DESCRIPTION

V

DD

WRITE PULSE

100 µA

DATA FROM

SHIFT REGISTER

D

C

Q

FF

I/O0 TO I/O7

I

S

POWER-ON

RESET

V

SS

D

C

Q

FF

I

READ PULSE

S

DATA TO

SHIFT REGISTER

SW00546

Figure 3. Simplified schematic diagram of each I/O

DEVICE ADDRESSING

Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in

Figure 4. Internal pullup resistors are incorporated on the hardware selectable address pins.

SLAVE ADDRESS

R/W

0

1

0

A2 A1 A0

HARDWARE

1

0

1

0

A2 A1 A0

FIXED

HARDWARE

PROGRAMMABLE

(a) I/O EXPANDER

(b) MEMORY

a.

b.

SW01075

Figure 4. PCA9500 slave addresses

The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write

operation.

CONTROL REGISTER

2

The PCA9500 contains a single 8-bit register called the Control Register, which can be written and read via the I C bus. This register is sent

after a successful acknowledgment of the slave address.

It contains the I/O operation information.

I/O OPERATIONS (see also Figure 3)

Each of the PCA9500’s eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE

mode (see Figure 5). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 6).

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

SCL

SDA

1

2

3

4

5

6

7

8

SLAVE ADDRESS (I/O EXPANDER)

DATA TO PORT

DATA 2

DATA TO PORT

DATA 1

S

0

1

0

A2 A1 A0

0

A

START CONDITION

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

WRITE TO

PORT

DATA OUT

FROM PORT

DATA 1 VALID

DATA 2 VALID

SW00548

t

pv

Figure 5. I/O WRITE mode (output)

SLAVE ADDRESS (I/O EXPANDER)

DATA FROM PORT

DATA 4

SDA

S

0

1

0

A2 A1 A0

1

A

DATA 1

A

1

P

START CONDITION

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

STOP

CONDITION

READ FROM

PORT

DATA INTO

PORT

DATA 1

DATA 2

DATA 3

DATA 4

t

ps

ph

SW00549

Figure 6. I/O READ mode (input)

Quasi-bidirectional I/Os (see Figure 7)

A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH.

In this mode, only a current source to V is active. An additional strong pull-up to V allows fast rising edges into heavily loaded outputs.

DD

5

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before

being used as inputs.

SLAVE ADDRESS (I/O EXPANDER)

DATA TO PORT

0

DATA TO PORT

1

SDA

S

0

1

0

4

A2 A1 A0

0

A

P

START CONDITION

R/W ACKNOWLEDGE

FROM SLAVE

I/O3

ACKNOWLEDGE

FROM SLAVE

I/O3

SCL

1

2

3

5

6

7

8

I/O3

OUTPUT

VOLTAGE

I/O3

PULL-UP

OUTPUT

CURRENT

I

OHt

OH

SW00905

Figure 7. Transient pull-up current I

while I/O3 changes from LOW-to-HIGH and back to LOW

OHt

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

the word address and the eight bits after the word address as the

data. The PCA9500 will issue an acknowledge after the receipt of

both the word address and the data. To terminate the data transfer

the master issues the stop condition, initiating the internal write cycle

to the non-volatile memory. Only write and read operations to the

Quasi-bidirectional I/O are allowed during the internal write cycle.

MEMORY OPERATIONS

Write operations

Write operations require an additional address field to indicate the

memory address location to be written. The address field is eight

bits long, providing access to any one of the 256 words of memory.

There are two types of write operations, byte write and page write.

Page Write (see Figure 9)

Write operation is possible when WC control pin put at a low logic

level (0). When this control signal is set at 1, write operation is not

possible and data in the memory is protected.

A page write is initiated in the same way as the byte write. If after

sending the first word of data, the stop condition is not received the

PCA9500 considers subsequent words as data. After each data

word the PCA9500 responds with an acknowledge and the two least

significant bits of the memory address field are incremented. Should

the master not send a stop condition after four data words the

address counter will return to its initial value and overwrite the data

previously written. After the receipt of the stop condition the inputs

will behave as with the byte write during the internal write cycle.

Byte Write and Page Write explained below assume that Write

Control pin (WC) is set to 0.

Byte Write (see Figure 8)

To perform a byte write the start condition is followed by the memory

slave address and the R/W bit set to 0. The PCA9500 will respond

with an acknowledge and then consider the next eight bits sent as

SLAVE ADDRESS (MEMORY)

DATA

WORD ADDRESS

DATA

SDA

S

1

0

1

0

A2 A1 A0

0

A

P

START CONDITION

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE STOP CONDITION.

FROM SLAVE WRITE TO THE

MEMORY IS

PERFORMED

SW02036

Figure 8. Byte write

SLAVE ADDRESS (MEMORY)

DATA TO MEMORY

DATA n

DATA TO MEMORY

WORD ADDRESS

DATA n + 3

SDA

S

1

0

1

0

A2 A1 A0

0

A

P

START CONDITION

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

STOP CONDITION.

WRITE TO THE MEMORY

IS PERFORMED

SW02037

Figure 9. Page Write

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

The master must perform a byte write to the address location to be

read, but instead of transmitting the data after receiving the

acknowledge from the PCA9500 the master reissues the start

condition and memory slave address with the R/W bit set to one.

The PCA9500 will then transmit an acknowledge and use the next

eight clock cycles to transmit the data contained in the addressed

location. The master ceases the transmission by issuing the stop

condition after the eighth bit, omitting the ninth clock cycle

acknowledge.

Read operations

PCA9500 read operations are initiated in an identical manner to

write operations with the exception that the memory slave address’

R/W bit is set to a one. There are three types of read operations;

current address, random and sequential.

Current Address Read (see Figure 10)

The PCA9500 contains an internal address counter that increments

after each read or write access, as a result if the last word accessed

was at address n then the address counter contains the address

n+1.

Sequential Read (see Figure 12)

The PCA9500 sequential read is an extension of either the current

address read or random read. If the master doesn’t issue a stop

condition after it has received the eighth data bit, but instead issues

an acknowledge, the PCA9500 will increment the address counter

and use the next eight cycles to transmit the data from that location.

The master can continue this process to read the contents of the

entire memory. Upon reaching address 255 the counter will return to

address 0 and continue transmitting data until a stop condition is

received. The master ceases the transmission by issuing the stop

condition after the eighth bit, omitting the ninth clock cycle

acknowledge.

When the PCA9500 receives its memory slave address with the

R/W bit set to one it issues an acknowledge and uses the next eight

clocks to transmit the data contained at the address stored in the

address counter. The master ceases the transmission by issuing the

stop condition after the eighth bit. There is no ninth clock cycle for

the acknowledge.

Random Read (see Figure 11)

The PCA9500’s random read mode allows the address to be read

from to be specified by the master. This is done by performing a

dummy write to set the address counter to the location to be read.

SLAVE ADDRESS (MEMORY)

DATA FROM MEMORY

SDA

S

1

0

1

0

A2 A1 A0

1

A

P

START CONDITION

R/W ACKNOWLEDGE

FROM SLAVE

STOP

CONDITION

SW00556

Figure 10. Current Address Read

SLAVE ADDRESS (MEMORY)

WORD ADDRESS

DATA FROM MEMORY

SDA

P

S

1

0

1

0

A2 A1 A0

A

S

1

0

1

0

A2 A1 A0

R/W

A

0

1

ACKNOWLEDGE

FROM SLAVE

R/W

START

CONDITION

STOP

CONDITION

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

START

CONDITION

SW00557

Figure 11. Random Read

SLAVE ADDRESS (MEMORY)

DATA FROM MEMORY

DATA n+1

DATA FROM MEMORY

DATA n+X

SDA

P

S

1

0

1

0

A2 A1 A0

A

1

DATA n

R/W

START CONDITION

STOP

CONDITION

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

SW00558

Figure 12. Sequential Read

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

2

CHARACTERISTICS OF THE I C-BUS

2

The I C-bus is for 2-way, 2-line communication between different ICs

Start and stop conditions

or modules. The two lines are a serial data line (SDA) and a serial

clock line (SCL). Both lines must be connected to a positive supply

via a pull-up resistor when connected to the output stages of a device.

Data transfer may be initiated only when the bus is not busy.

Both data and clock lines remain HIGH when the bus is not busy. A

HIGH-to-LOW transition of the data line, while the clock is HIGH is

defined as the start condition (S). A LOW-to-HIGH transition of the

data line while the clock is HIGH is defined as the stop condition (P)

(see Figure 14).

Bit transfer

One data bit is transferred during each clock phase. The data on the

SDA line must remain stable during the HIGH period of the clock

pulse as changes in the data line at this time will be interpreted as

control signals (See Figure 13).

System configuration

A device generating a message is a “transmitter”, a device receiving

is the “receiver”. The device that controls the message is the

“master” and the devices which are controlled by the master are the

“slaves” (see Figure 15).

SDA

SCL

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

SW00542

Figure 13. Bit transfer

SDA

SCL

S

P

START CONDITION

STOP CONDITION

SW00543

Figure 14. Definition of start and stop conditions

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SW00544

Figure 15. System configuration

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that

the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse, set-up and hold times must be

taken into account.

Acknowledge (see Figure 16)

The number of data bytes transferred between the start and the stop

conditions from transmitter to receiver is not limited. Each byte of

eight bits is followed by one acknowledge bit. The acknowledge bit

is a HIGH level put on the bus by the transmitter whereas the

master generates an extra acknowledge related clock pulse.

A master receiver must signal an end of data to the transmitter by

not generating an acknowledge on the last byte that has been

clocked out of the slave. In this event the transmitter must leave the

data line HIGH to enable the master to generate a stop condition.

A slave receiver which is addressed must generate an acknowledge

after the reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has been clocked

DATA OUTPUT

BY TRANSMITTER

NOT ACKNOWLEDGE

ACKNOWLEDGE

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

1

2

8

9

S

CLOCK PULSE FOR

ACKNOWLEDGEMENT

START

CONDITION

SW00545

2

Figure 16. Acknowledgment on the I C-bus

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

TYPICAL APPLICATION

Applications

• Board version tracking and configuration

• Board health monitoring and status reporting

• General-purpose integrated I/O with memory

• Drop in replacement for PCF8574 with integrated 2-kbit EEPROM

• Bus master sees GPIO and EEPROM as two separate devices

• Three hardware address pins allow up to 8 PCA9500s to be

• Multi-card systems in Telecom, Networking, and Base Station

Infrastructure Equipment

2

• Field recall and troubleshooting functions for installed boards

located in the same I C/SMBus

UP TO 8 CARDS

2

I C

ASIC

2

I C

CPU

2

I C

OR

2

I C

µC

CONFIGURATION CONTROL

2

PCA9500

I C

CONTROL

INPUTS

ALARM

LEDs

2

I C

GPIO

MONITORING

AND

CONTROL

EEPROM

CARD ID, SUBROUTINES, CONFIGURATION DATA, OR REVISION HISTORY

SW02003

Figure 17. Typical application

A central processor/controller typically located on the system main

board can use the 400 kHz I C/SMBus to poll the PCA9500 devices

located on the system cards for status or version control type of

information. The PCA9500 may be programmed at manufacturing to

store information regarding board build, firmware version,

manufacturer identification, configuration option data… Alternately,

2

these devices can be used as convenient interface for board

2

configuration, thereby utilizing the I C/SMBus as an intra-system

communication bus.

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

TYPICAL APPLICATION

V

DD

2 kΩ

1.6 kΩ

2 kΩ

(optional)

V

DD

V

DD

SUBSYSTEM 1

(e.g. temp sensor)

SCL

SDA

SCL

SDA

I/0

0

MASTER

CONTROLLER

INT

1

I/0

2

RESET

GND

3

PCA9500

SUBSYSTEM 2

(e.g. counter)

I/0

4

I/0

5

I/0

6

I/0

7

A

A2

Controlled Switch

(e.g. CBT device)

ENABLE

A1

A0

B

V

SS

ALARM

SUBSYSTEM 3

(e.g. alarm

system)

NOTE: GPIO device address configured as 0100100 for this example

EEPROM device address configured as 1010100 for this example

I/0 , I/0 , I/0 , configured as outputs

0

2

3

I/0 , I/0 , I/0 , configured as inputs

1

4

5

V

DD

I/0 , I/0 , are not used and have to be configured as outputs

06

7

SW01076

Figure 18. Typical application

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

SYMBOL

PARAMETER

MIN

MAX

4.0

UNIT

V

CC

Supply Voltage

–0.5

V

I

Input Voltage

V

SS

– 0.5

5.5

V

I

DC Input Current

DC Output Current

Supply Current

–20

–25

–100

—

20

mA

mW

_C

I

O

25

I

100

400

100

+150

+85

DD

I

Supply Current

SS

P

tot

Total Power Dissipation

P

O

Total Power Dissipation per Output

Storage Temperature

—

T

–65

–40

STG

T

Operating Temperature

_C

AMB

DC ELECTRICAL CHARACTERISTICS

T

= –40_C to +85_C unless otherwise specified; V = 3.3 V

amb

CC

SYMBOL

Supply

PARAMETER

MIN

TYP

MAX

UNIT

V

Supply Voltage

2.5

—

3.3

—

3.6

60

1

V

DD

I

Standby Current; A0, A1, A2, WC = HIGH

Supply Current Read

µA

mA

V

DDQ

I

DD1

DD2

I

Supply Current Write

2

V

POR

Power on Reset Voltage

2.4

Input SCL; input, output SDA

V

Input LOW voltage

Input HIGH voltage

–0.5

—

0.3 V

V

IL

IH

DD

V

0.7 V

3

5.5

—

1

DD

I

OL

Output LOW current @ V = 0.4 V

mA

µA

pF

OL

I

L

Input leakage current @ V = V or V

SS

–1

I

DD

C

Input capacitance @ V = V

SS

—

7

I

I/O Expander Port

V

Input LOW voltage

Input HIGH voltage

–0.5

0.7 V

—

25

100

2

0.3 V

V

IL

DD

V

IH

5.5

400

—

V

DD

I

Input current through protection diodes

Output LOW current @ V = 1 V

–400

10

µA

mA

µA

mA

pF

IHL(max)

I

OL

I

Output HIGH current @ V = V

ss

30

300

—

OH

I

Transient pull-up current

Input Capacitance

—

OHt

C

—

10

I

C

Output Capacitance

—

10

O

Address Inputs (A0, A1, A2), WC input

V

Input LOW voltage

Input HIGH voltage

–0.5

—

25

0.3 V

V

IL

IH

L

DD

V

I

0.7 V

–1

5.5

1

DD

Input leakage current @ V = V

µA

I

DD

Input leakage (pull-up) current @ V = V

10

100

I

SS

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2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

NON-VOLATILE STORAGE SPECIFICATIONS

PARAMETER

SPECIFICATION

Memory cell data retention

10 years minimum

Number of memory cell write cycles

100,000 cycles minimum

2

I C-BUS TIMING CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

2

I C-bus timing (see Figure 19; Note 1)

f

SCL clock frequency

tolerable spike width on bus

bus free time

—

400

50

—

kHz

ns

µs

ns

µs

SCL

t

SW

t

1.3

0.6

—

BUF

t

START condition set-up time

START condition hold time

SCL and SDA rise time

SCL and SDA fall time

data set-up time

—

SU;STA

HD;STA

t

—

t

r

0.3

—

t

f

—

t

250

0

SU;DAT

HD;DAT

t

data hold time

—

t

SCL LOW to data out valid

STOP condition set-up time

—

1.0

—

VD;DAT

t

0.6

SU;STO

NOTE:

1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V and V with an input

IL

IH

voltage swing of V to V

.

SS

DD

PORT TIMING CHARACTERISTICS

SYMBOL

PARAMETER

Output data valid; C ≤ 100 pF

MIN

—

0

TYP

—

MAX

4

UNIT

µs

t

pv

t

ps

ph

L

Input data setup time; C ≤ 100 pF

—

µs

L

t

Input data hold time; C ≤ 100 pF

4

—

µs

L

handbook, full pagewidth

PROTOCOL

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

BIT 0

LSB

(R/W)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

t

SU;STA

1 / f

SCL

SDA

t

f

BUF

r

t

HD;STA

SU;DAT

VD;DAT

SU;STO

HD;DAT

MBD820

SW00561

Figure 19.

14

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

POWER-UP TIMING

SYMBOL

PARAMETER

MAX.

UNIT

ms

1

t

Power-up to Read Operation

Power-up to Write Operation

1

5

PUR

1

t

ms

PUW

NOTE:

1. t

and t are the delays required from the time V is stable until the specified operation can be initiated. These parameters are

PUW CC

PUR

guaranteed by design.

WRITE CYCLE LIMITS

(5)

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

1

t

Write Cycle Time

—

5

10

ms

WR

NOTE:

1. t

is the maximum time that the device requires to perform the internal write operation.

WR

Write Cycle Timing

SCL

8th Bit

Word n

ACK

SDA

MEMORY

ADDRESS

t

WR

Stop

Condition

Start

Condition

SW00560

Figure 20.

15

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

SOLDERING

seconds depending on heating method. Typical reflow temperatures

range from 215 to 250°C.

Introduction

There is no soldering method that is ideal for all IC packages. Wave

soldering is often preferred when through-hole and surface mounted

components are mixed on one printed-circuit board. However, wave

soldering is not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these situations

reflow soldering is often used.

Preheating is necessary to dry the paste and evaporate the binding

agent. Preheating duration: 45 minutes at 45°C.

Wave soldering

Wave soldering is not recommended for SSOP packages. This is

because of the likelihood of solder bridging due to closely-spaced

leads and the possibility of incomplete solder penetration in

multi-lead devices.

This text gives a very brief insight to a complex technology. A more

in-depth account of soldering ICs can be found in our IC Package

Databook (order code 9398 652 90011).

If wave soldering cannot be avoided, the following conditions

must be observed:

DIP

• A double-wave (a turbulent wave with high upward pressure

followed by a smooth laminar wave) soldering technique

should be used.

Soldering by dipping or by wave

The maximum permissible temperature of the solder is 260°C;

solder at this temperature must not be in contact with the joint for

more than 5 seconds. The total contact time of successive solder

waves must not exceed 5 seconds.

• The longitudinal axis of the package footprint must be

parallel to the solder flow and must incorporate solder

thieves at the downstream end.

The device may be mounted up to the seating plane, but the

temperature of the plastic body must not exceed the specified

Even with these conditions, only consider wave soldering

SSOP packages that have a body width of 4.4 mm, that is

SSOP16 (SOT369-1) or SSOP20 (SOT266-1).

maximum storage temperature (T max). If the printed-circuit board

stg

has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

During placement and before soldering, the package must be fixed

with a droplet of adhesive. The adhesive can be applied by screen

printing, pin transfer or syringe dispensing. The package can be

soldered after the adhesive is cured.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of

the package, below the seating plane or not more than 2 mm above

it. If the temperature of the soldering iron bit is less than 300°C it

may remain in contact for up to 10 seconds. If the bit temperature is

between 300 and 400°C, contact may be up to 5 seconds.

Maximum permissible solder temperature is 260°C, and maximum

duration of package immersion in solder is 10 seconds, if cooled to

less than 150°C within 6 seconds. Typical dwell time is 4 seconds at

250°C.

SO and SSOP

A mildly-activated flux will eliminate the need for removal of

corrosive residues in most applications.

Reflow soldering

Reflow soldering techniques are suitable for all SO and SSOP

packages.

Repairing soldered joints

Reflow soldering requires solder paste (a suspension of fine solder

particles, flux and binding agent) to be applied to the printed-circuit

board by screen printing, stencilling or pressure-syringe dispensing

before package placement.

Fix the component by first soldering two diagonally opposite end

leads. Use only a low voltage soldering iron (less than 24 V) applied

to the flat part of the lead. Contact time must be limited to

10 seconds at up to 300 °C. When using a dedicated tool, all other

leads can be soldered in one operation within 2 to 5 seconds

between 270 and 320°C.

Several techniques exist for reflowing; for example, thermal

conduction by heated belt. Dwell times vary between 50 and 300

16

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

SO16: plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

17

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

18

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

REVISION HISTORY

Rev

Date

Description

_1

2002 Sep 27

Product data (9397 750 10326); initial version

Engineering Change Notice: 853–2369 28875 (2002 Sep 09)

19

2002 Sep 27

Philips Semiconductors

Product data

8-bit I²C and SMBus I/O port with 2-kbit EEPROM

PCA9500

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 09-02

9397 750 10326

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

20

2002 Sep 27


型号：	935271534112
厂家：	NXP
描述：	IC 256 X 8 EEPROM, 8 I/O, PIA-GENERAL PURPOSE, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16, Parallel IO Port 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管外围集成电路
文件：	总20页 (文件大小：131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935271534112 [NXP]

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