935277415112 [NXP]
4 I/O, PIA-GENERAL PURPOSE, PDSO8;
| 型号： | 935277415112 |
| 厂家： | 
NXP |
| 描述： | 4 I/O, PIA-GENERAL PURPOSE, PDSO8 光电二极管 |
| 文件： | 总22页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9536
4-bit I2C-bus and SMBus I/O port
Rev. 05 — 25 January 2010
Product data sheet
1. General description
The PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders
provide a simple solution when additional I/O is needed for ACPI power switches,
sensors, push buttons, LEDs, fans, etc.
The PCA9536 consists of a 4-bit Configuration register (input or output selection), 4-bit
Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the read
register can be inverted with the Polarity Inversion register. All registers can be read by
the system master.
The power-on reset sets the registers to their default values and initializes the device state
machine.
The I2C-bus address is fixed and allows only one device on the same I2C-bus/SMBus.
2. Features
4-bit I2C-bus GPIO
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
4 I/O pins which default to 4 inputs with 100 kΩ internal pull-up resistor
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8, TSSOP8 (MSOP8), HVSON8
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
3. Ordering information
Table 1.
Ordering information
Tamb = −40 °C to +85 °C
Type
number
Topside
mark
Package
Name
Description
Version
PCA9536D
PCA9536 SO8
plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
SOT505-1
SOT908-1
PCA9536DP 9536
PCA9536TK 9536
TSSOP8[1] plastic thin shrink small outline package;
8 leads; body width 3 mm
HVSON8
plastic thermal enhanced very thin small
outline package; no leads; 8 terminals;
body 3 × 3 × 0.85 mm
[1] Also known as MSOP8.
4. Block diagram
PCA9536
SCL
SDA
INPUT
FILTER
IO0
IO1
IO2
IO3
4-bit
INPUT/
OUTPUT
PORTS
2
I C-BUS/SMBus
CONTROL
write pulse
read pulse
V
DD
POWER-ON
RESET
V
SS
002aab851
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9536
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
2 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
5. Pinning information
5.1 Pinning
1
2
3
4
8
7
6
5
IO0
IO1
IO2
V
DD
1
2
3
4
8
7
6
5
IO0
IO1
IO2
V
DD
SDA
SCL
IO3
SDA
SCL
IO3
PCA9536D
PCA9536DP
V
SS
V
SS
002aab850
002aab849
Fig 2. Pin configuration for SO8
Fig 3. Pin configuration for TSSOP8
terminal 1
index area
IO0
IO1
IO2
1
2
3
4
8
7
6
5
V
DD
SDA
SCL
IO3
PCA9536TK
V
SS
002aac459
Transparent top view
Fig 4. Pin configuration for HVSON8
5.2 Pin description
Table 2.
Pin description
Symbol
IO0
Pin
1
Description
input/output 0
input/output 1
input/output 2
supply ground
input/output 3
serial clock line
serial data line
supply voltage
IO1
2
IO2
3
VSS
4
IO3
5
SCL
SDA
VDD
6
7
8
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
3 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
6. Functional description
Refer to Figure 1 “Block diagram of PCA9536”.
6.1 Registers
6.1.1 Command byte
Table 3.
Command byte
Command
Protocol
Function
0
1
2
3
read byte
Input Port register
Output Port register
read/write byte
read/write byte
read/write byte
Polarity Inversion register
Configuration register
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level, normally logic 1 when
no external signal externally applied because of the internal pull-up resistors.
Table 4.
Register 0 - Input Port register bit description
Legend: * default value
Bit
7
Symbol
Access
Value
1*
1*
1*
1*
X
Description
I7
I6
I5
I4
I3
I2
I1
I0
read only
read only
read only
read only
read only
read only
read only
read only
not used
6
5
4
3
determined by externally applied logic level
2
X
1
X
0
X
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
4 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
‘Not used’ bits can be programmed with either logic 0 or logic 1.
Table 5.
Register 1 - Output Port register bit description
Legend: * default value
Bit
7
Symbol
O7
Access
Value
1*
Description
R
R
R
R
R
R
R
R
not used
6
O6
1*
5
O5
1*
4
O4
1*
3
O3
1*
reflects outgoing logic levels of pins defined as
outputs by Register 3
2
O2
1*
1
O1
1*
0
O0
1*
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
‘Not used’ bits can be programmed with either logic 0 or logic 1.
Table 6.
Register 2 - Polarity Inversion register bit description
Legend: * default value
Bit
7
Symbol
N7
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0*
Description
not used
6
N6
0*
5
N5
0*
4
N4
0*
3
N3
0*
inverts polarity of Input Port register data
0 = Input Port register data retained (default
value)
2
N2
0*
1
N1
0*
1 = Input Port register data inverted
0
N0
0*
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
5 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to VDD
.
‘Not used’ bits can be programmed with either logic 0 or logic 1.
Table 7.
Register 3 - Configuration register bit description
Legend: * default value
Bit
7
Symbol
C7
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
1*
Description
not used
6
C6
1*
5
C5
1*
4
C4
1*
3
C3
1*
configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
2
C2
1*
1 = corresponding port pin configured as input
(default value)
1
C1
1*
0
C0
1*
6.2 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9536 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.3 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 kΩ typical) to VDD. The input voltage may
be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS
.
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
6 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
data from
shift register
output port
register data
configuration
register
V
DD
data from
shift register
Q1
D
Q
100 kΩ
FF
write configuration
pulse
D
Q
CK
Q
FF
IO0 to IO3
write pulse
CK
Q2
output port
register
V
SS
input port
register
D
Q
input port
register data
FF
read pulse
CK
polarity inversion
register
data from
shift register
polarity inversion
register data
D
Q
FF
write polarity
pulse
CK
002aab852
Remark: At power-on reset, all registers return to default values.
Fig 5. Simplified schematic of IO0 to IO3
6.4 Device address
slave address
1
0
0
0
0
0
1
R/W
fixed
002aab853
Fig 6. PCA9536 device address
6.5 Bus transactions
Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure 7
and Figure 8. Data is read from the PCA9536 registers using the Read mode as shown in
Figure 9 and Figure 10. These devices do not implement an auto-increment function, so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
7 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
SCL
SDA
1
2
3
4
5
6
7
8
9
slave address
command byte
data to port
S
1
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
1
A
DATA 1
A
P
START condition
R/W
acknowledge
from slave
acknowledge
from slave
STOP
condition
acknowledge
from slave
write to port
t
v(Q)
data out
from port
data 1 valid
002aab854
Fig 7. Write to Output Port register
SCL
SDA
1
2
3
4
5
6
7
8
9
slave address
command byte
data to register
DATA
S
1
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
1/0
A
A
P
START condition
R/W
acknowledge
from slave
acknowledge
from slave
STOP
condition
acknowledge
from slave
data to
register
002aab855
Fig 8. Write to Configuration register or Polarity Inversion register
slave address
(cont.)
SDA
S
1
0
0
0
0
0
1
0
A
command byte
A
START condition
R/W
acknowledge
from slave
acknowledge
from slave
slave address
data from register
DATA (first byte)
data from register
DATA (last byte)
(cont.)
S
1
0
0
0
0
0
1
1
A
A
NA
P
(repeated)
START condition
R/W
acknowledge
from master
no acknowledge
from master
STOP
condition
acknowledge
from slave
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aab856
Fig 9. Read from register
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
8 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
SCL
SDA
1
2
3
4
5
6
7
8
9
slave address
data from port
DATA 1
data from port
S
1
0
0
0
0
0
1
1
A
A
DATA 4
NA
P
START condition
R/W
acknowledge
from master
no acknowledge
from master
STOP
condition
acknowledge
from slave
read from
port
t
t
su(D)
h(D)
data into
port
DATA 2
DATA 3
DATA 4
002aab857
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Fig 10. Read Input Port register
7. Application design-in information
V
DD
2 kΩ
V
DD
10 kΩ
10 kΩ
V
DD
SUBSYSTEM 1
IO0
IO1
IO2
IO3
SDA
SCL
SDA
SCL
(e.g. temp. sensor)
INT
PCA9536
MASTER
CONTROLLER
RESET
SUBSYSTEM 2
(e.g. counter)
V
SS
A
V
SS
controlled switch
(e.g. CBT device)
enable
B
002aab858
Device address is 1000 001X; IO0, IO2, IO3 configured as outputs; IO1 configured as input.
Fig 11. Typical application
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
9 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
8. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
II
Parameter
Conditions
Min
Max
+6.0
±20
5.5
Unit
V
supply voltage
−0.5
input current
-
mA
V
VI/O
voltage on an input/output pin
output current on pin IOn
supply current
VSS − 0.5
IO(IOn)
IDD
-
±50
85
mA
mA
mA
mW
°C
-
ISS
ground supply current
total power dissipation
storage temperature
ambient temperature
maximum junction temperature
-
100
200
+150
+85
+125
Ptot
-
Tstg
−65
−40
-
Tamb
Tj(max)
°C
°C
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
10 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
9. Static characteristics
Table 9.
Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
supply current
2.3
-
-
5.5
V
IDD
operating mode; VDD = 5.5 V;
no load; fSCL = 100 kHz
290
400
μA
Istb
standby current
Standby mode; VDD = 5.5 V; no load;
VI = VSS; fSCL = 0 kHz; I/O = inputs
-
-
-
225
0.25
1.5
350
1
μA
μA
V
Standby mode; VDD = 5.5 V; no load;
VI = VDD; fSCL = 0 kHz; I/O = inputs
[1]
VPOR
power-on reset voltage
1.65
Input SCL; input/output SDA
VIL
VIH
IOL
IL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
leakage current
−0.5
-
+0.3VDD
V
0.7VDD
-
5.5
-
V
VOL = 0.4 V
VI = VDD = VSS
VI = VSS
3
6
-
mA
μA
pF
−1
-
+1
10
Ci
input capacitance
6
I/Os
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
−0.5
2.0
8
-
+0.8
V
-
5.5
-
V
[2]
[2]
[2]
[2]
[2]
[2]
[3]
[3]
[3]
[3]
[3]
[3]
VOL = 0.5 V; VDD = 2.3 V
VOL = 0.7 V; VDD = 2.3 V
VOL = 0.5 V; VDD = 3.0 V
VOL = 0.7 V; VDD = 3.0 V
VOL = 0.5 V; VDD = 4.5 V
VOL = 0.7 V; VDD = 4.5 V
10
13
14
19
17
24
-
mA
mA
mA
mA
mA
mA
V
10
8
-
-
10
8
-
-
10
1.8
1.7
2.6
2.5
4.1
4.0
-
-
VOH
HIGH-level output voltage IOH = −8 mA; VDD = 2.3 V
IOH = −10 mA; VDD = 2.3 V
-
-
-
V
IOH = −8 mA; VDD = 3.0 V
-
-
V
IOH = −10 mA; VDD = 3.0 V
-
-
V
IOH = −8 mA; VDD = 4.75 V
-
-
V
IOH = −10 mA; VDD = 4.75 V
-
-
V
ILIH
ILIL
HIGH-level input leakage
current
VDD = 3.6 V; VI = VDD
-
1
μA
LOW-level input leakage
current
VDD = 5.5 V; VI = VSS
-
-
−100
μA
Ci
input capacitance
output capacitance
-
-
3.7
3.7
5
5
pF
pF
Co
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
11 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
10. Dynamic characteristics
Table 10. Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus Unit
Min
Max
100
-
Min
0
Max
400
-
fSCL
tBUF
SCL clock frequency
0
kHz
bus free time between a STOP and
START condition
4.7
1.3
μs
tHD;STA
tSU;STA
hold time (repeated) START condition
4.0
4.7
-
-
0.6
0.6
-
-
μs
μs
set-up time for a repeated START
condition
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
tHIGH
tr
set-up time for STOP condition
data hold time
4.0
0
-
0.6
-
μs
μs
μs
ns
ns
μs
μs
ns
ns
ns
-
0
-
0.9
-
[1]
[2]
data valid acknowledge time
data valid time
0.3
300
250
4.7
4.0
-
3.45
0.1
-
50
data set-up time
-
-
100
1.3
-
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
-
-
0.6
-
[3]
[3]
1000
300
50
20 + 0.1Cb
20 + 0.1Cb
-
300
300
50
tf
-
tSP
pulse width of spikes that must be
suppressed by the input filter
-
Port timing
tv(Q)
data output valid time
data input set-up time
data input hold time
-
100
1
200
-
100
1
200
ns
ns
μs
tsu(D)
-
-
-
-
th(D)
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
SDA
t
BUF
t
t
LOW
t
t
SU;DAT
HD;STA
SP
t
f
t
r
t
r
t
f
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
HIGH
S
Sr
P
S
t
HD;DAT
002aab271
Fig 12. Definition of timing
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
12 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
START
condition
(S)
bit 7
MSB
(A7)
STOP
bit 0 acknowledge
condition
bit 6
(A6)
protocol
(R/W)
(A)
(P)
t
t
t
HIGH
SU;STA
LOW
1
/f
SCL
SCL
SDA
t
t
f
BUF
t
r
t
t
t
t
t
t
HD;DAT
VD;DAT
VD;ACK
SU;STO
HD;STA
SU;DAT
002aab175
Rise and fall times refer to VIL and VIH
Fig 13. I2C-bus timing diagram
11. Test information
V
DD
open
V
SS
V
DD
R
500 Ω
L
V
I
V
O
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
002aab880
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 14. Test circuitry for switching times
S1
2V
DD
open
500 Ω
from output
under test
V
SS
C
50 pF
L
500 Ω
002aab88
1
Fig 15. Test circuit
Table 11. Test data
Test
Load
CL
Switch
RL
500 Ω
tv(Q)
50 pF
2VDD
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
13 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
12. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 16. Package outline SOT96-1 (SO8)
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
14 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
4
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.05
0.95
0.80
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
5.1
4.7
0.7
0.4
0.70
0.35
6°
0°
mm
1.1
0.65
0.25
0.94
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-04-09
03-02-18
SOT505-1
Fig 17. Package outline SOT505-1 (TSSOP8)
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
15 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm
SOT908-1
0
1
2 mm
scale
X
D
B
A
E
A
A
1
c
detail X
terminal 1
index area
e
1
terminal 1
index area
C
M
M
v
w
C A
C
B
e
b
y
1
y
C
1
4
L
exposed tie bar (4×)
E
h
exposed tie bar (4×)
8
5
D
h
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
A
b
E
e
e
y
c
D
D
E
L
v
w
y
1
1
h
1
h
0.05
0.00
0.3
0.2
3.1
2.9
2.25
1.95
3.1
2.9
1.65
1.35
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
1.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
05-09-26
05-10-05
SOT908-1
MO-229
Fig 18. Package outline SOT908-1 (HVSON8)
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
16 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
13. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
© NXP B.V. 2010. All rights reserved.
PCA9536_5
Product data sheet
Rev. 05 — 25 January 2010
17 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 13. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
18 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 14. Abbreviations
Acronym
ACPI
CDM
DUT
Description
Advanced Configuration and Power Interface
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
Field-Effect Transistor
General Purpose Input/Output
Human Body Model
FET
GPIO
HBM
I2C-bus
I/O
Inter-Integrated Circuit bus
Input/Output
LED
Light-Emitting Diode
MM
Machine Model
POR
Power-On Reset
SMBus
System Management Bus
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
19 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
16. Revision history
Table 15. Revision history
Document ID
PCA9536_5
Modifications:
Release date
20100125
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCA9536_4
• Table 9 “Static characteristics”, sub-section “Supplies”:
–
I
DD Typical value changed from “104 μA” to “290 μA”
–
IDD Maximum value changed from “175 μA” to “400 μA”
• Table 10 “Dynamic characteristics”: Unit for “tf, fall time of both SDA and SCL signals”
changed from “μs” to “ns”
Remark: The changes made in this revision are to correct typographical errors only. There is
no change in the performance of the device.
PCA9536_4
PCA9536_3
20070911
20061009
20040930
Product data sheet
Product data sheet
Objective data sheet
-
-
-
PCA9536_3
PCA9536_2
PCA9536_1
PCA9536_2
(9397 750 14124)
PCA9536_1
20040820
Objective data sheet
-
-
(9397 750 12895)
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
20 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9536_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 25 January 2010
21 of 22
PCA9536
NXP Semiconductors
4-bit I2C-bus and SMBus I/O port
19. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
Functional description . . . . . . . . . . . . . . . . . . . 4
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4
Register 0 - Input Port register . . . . . . . . . . . . . 4
Register 1 - Output Port register. . . . . . . . . . . . 5
Register 2 - Polarity Inversion register . . . . . . . 5
Register 3 - Configuration register . . . . . . . . . . 6
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device address. . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus transactions. . . . . . . . . . . . . . . . . . . . . . . . 7
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
6.5
7
Application design-in information . . . . . . . . . . 9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
Static characteristics. . . . . . . . . . . . . . . . . . . . 11
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
Test information. . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Handling information. . . . . . . . . . . . . . . . . . . . 17
8
9
10
11
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 17
Introduction to soldering . . . . . . . . . . . . . . . . . 17
Wave and reflow soldering . . . . . . . . . . . . . . . 17
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 17
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 18
14.1
14.2
14.3
14.4
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 January 2010
Document identifier: PCA9536_5
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