935278202118 [NXP]
SERIAL INPUT LOADING, 24-BIT DAC, PDSO16, 4.40 MM, PLASTIC, MO-152, SOT369-1, SSOP-16;
| 型号： | 935278202118 |
| 厂家： | 
NXP |
| 描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO16, 4.40 MM, PLASTIC, MO-152, SOT369-1, SSOP-16 输入元件 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UDA1334BTS
Low power audio DAC
Product specification
2000 Jul 31
Supersedes data of 2000 Feb 07
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
CONTENTS
13
14
DC CHARACTERISTICS
AC CHARACTERISTICS
1
FEATURES
14.1
14.2
14.3
2.0 V supply voltage
3.0 V supply voltage
Timing
1.1
1.2
1.3
1.4
General
Multiple format data interface
DAC digital sound processing
Advanced audio configuration
15
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
16
2
3
4
5
6
7
8
APPLICATIONS
17
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
17.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
17.2
17.3
17.4
17.5
PINNING
Suitability of surface mount IC packages for
wave and reflow soldering methods
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
System clock
Interpolation filter
Noise shaper
18
19
DATA SHEET STATUS
DISCLAIMERS
8.4
Filter stream DAC
8.5
Power-on reset
8.6
Feature settings
8.6.1
8.6.2
8.6.3
8.6.4
Digital interface format select
Mute control
De-emphasis control
Power control and sampling frequency select
9
LIMITING VALUES
10
11
12
HANDLING
THERMAL CHARACTERISTICS
QUALITY SPECIFICATION
2000 Jul 31
2
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
1
FEATURES
General
1.1
• 1.8 to 3.6 V power supply voltage
• Integrated digital filter plus DAC
• Supports sample frequencies from 8 to 100 kHz
• Automatic system clock versus sample rate detection
• Low power consumption
• No analog post filtering required for DAC
• Slave mode only applications
2
APPLICATIONS
This audio DAC is excellently suitable for digital audio
portable application, such as portable MD, MP3 and
DVD players.
• Easy application
• SSOP16 package.
1.2
Multiple format data interface
3
GENERAL DESCRIPTION
• I2S-bus and LSB-justified format compatible
• 1fs input data rate.
The UDA1334BTS supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.
1.3
DAC digital sound processing
The UDA1334BTS has basic features such as
de-emphasis (at 44.1 kHz sampling rate) and mute.
• Digital de-emphasis for 44.1 kHz sampling rate
• Mute function.
1.4
Advanced audio configuration
• High linearity, wide dynamic range and low distortion
• Standby or Sleep mode in which the DAC is powered
down.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
UDA1334BTS
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2000 Jul 31
3
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
5
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
VDDA
DAC analog supply voltage
digital supply voltage
1.8
1.8
−
2.0
2.0
2.3
125
1.4
3.6
3.6
−
V
VDDD
V
IDDA
DAC analog supply current
normal operating mode
Sleep mode
mA
μA
mA
−
−
IDDD
digital supply current
normal operating mode
Sleep mode
−
−
clock running
−
250
20
−
−
μA
μA
°C
no clock running
−
−
Tamb
ambient temperature
−40
+85
Digital-to-analog converter (VDDA = VDDD = 2.0 V)
Vo(rms)
(THD + N)/S total harmonic
distortion-plus-noise to signal
output voltage (RMS value)
at 0 dB (FS) digital input; note 1
fs = 44.1 kHz; at 0 dB
−
−
−
−
−
−
−
−
600
−80
−37
−75
−35
97
−
−
−
−
−
−
−
−
mV
dB
dB
dB
dB
dB
dB
dB
fs = 44.1 kHz; at −60 dB; A-weighted
fs = 96 kHz; at 0 dB
ratio
fs = 96 kHz; at −60 dB; A-weighted
fs = 44.1 kHz; code = 0; A-weighted
fs = 96 kHz; code = 0; A-weighted
S/N
signal-to-noise ratio
channel separation
95
αcs
100
Digital-to-analog converter (VDDA = VDDD = 3.0 V)
Vo(rms)
(THD + N)/S total harmonic
distortion-plus-noise to signal
output voltage (RMS value)
at 0 dB (FS) digital input; note 1
fs = 44.1 kHz; at 0 dB
−
−
−
−
−
−
−
−
900
−90
−40
−85
−37
100
98
−
−
−
−
−
−
−
−
mV
dB
dB
dB
dB
dB
dB
dB
fs = 44.1 kHz; at −60 dB; A-weighted
fs = 96 kHz; at 0 dB
ratio
fs = 96 kHz; at −60 dB; A-weighted
fs = 44.1 kHz; code = 0; A-weighted
fs = 96 kHz; code = 0; A-weighted
S/N
signal-to-noise ratio
channel separation
αcs
100
Power dissipation (at fs = 44.1 kHz)
P
power dissipation
playback mode
at 2.0 V supply voltage
at 3.0 V supply voltage
Sleep mode; at 2.0 V supply voltage
clock running
−
−
7.4
17
−
−
mW
mW
−
−
0.75
0.3
−
−
mW
mW
no clock running
Note
1. The DAC output voltage scales proportionally to the power supply voltage.
2000 Jul 31
4
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
6
BLOCK DIAGRAM
V
V
SSD
5
DDD
4
1
2
3
BCK
WS
DIGITAL INTERFACE
DE-EMPHASIS
DATAI
UDA1334BTS
6
7
SYSCLK
MUTE
DEEM
PCS
SFOR1
SFOR0
8
11
INTERPOLATION FILTER
NOISE SHAPER
9
10
16
DAC
DAC
14
VOUTR
VOUTL
13
15
12
ref(DAC)
MGL964
V
V
V
DDA
SSA
Fig.1 Block diagram.
2000 Jul 31
5
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
7
PINNING
SYMBOL
PIN
PAD TYPE
DESCRIPTION
BCK
1
2
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
digital supply pad
bit clock input
WS
word select input
serial data input
digital supply voltage
digital ground
DATAI
VDDD
3
4
VSSD
5
digital ground pad
SYSCLK
SFOR1
MUTE
DEEM
PCS
6
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
5 V tolerant digital input pad; note 1
3-level input pad; note 2
digital input pad; note 2
system clock input
serial format select 1
mute control
7
8
9
de-emphasis control
10
11
12
13
14
15
16
power control and sampling frequency select
serial format select 0
SFOR0
Vref(DAC)
VDDA
analog pad
DAC reference voltage
DAC analog supply voltage
DAC output left
analog supply pad
VOUTL
VSSA
analog output pad
analog ground pad
DAC analog ground
VOUTR
analog output pad
DAC output right
Notes
1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages
this is maximum 3.3 V tolerant.
2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a
maximum of 0.5 V above that level.
handbook, halfpage
BCK
WS
1
2
3
4
5
6
7
8
16
15
VOUTR
V
SSA
DATAI
14 VOUTL
V
V
V
13
12
DDD
DDA
UDA1334BTS
V
SSD
ref(DAC)
SYSCLK
SFOR1
MUTE
11 SFOR0
10 PCS
9
DEEM
MGL963
Fig.2 Pin configuration.
2000 Jul 31
6
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
8
FUNCTIONAL DESCRIPTION
System clock
Table 2 Example using a 12.228 MHz system clock
8.1
CLOCK MODE
128fs
SAMPLING FREQUENCY
96 kHz
64 kHz(1)
48 kHz
32 kHz
24 kHz
16 kHz
The UDA1334BTS operates in slave mode only; this
means that in all applications the system must provide the
system clock and the digital audio interface signals
(BCK and WS).
192fs
256fs
384fs
The system clock must be locked in frequency to the digital
interface signals.
512fs
768fs
The UDA1334BTS automatically detects the ratio between
the SYSCLK and WS frequencies.
Note
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in 192fs
mode the sampling frequency should be limited to
55 kHz.
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: fBCK ≤ 64 × fWS
.
Remarks:
8.2
Interpolation filter
1. The WS edge MUST fall on the negative edge of the
BCK at all times for proper operation of the digital I/O
data interface
The interpolation digital filter interpolates from 1fs to 64fs
by cascading FIR filters (see Table 3).
2. For LSB-justified formats it is important to have a WS
signal with a duty factor of 50%.
Table 3 Interpolation filter characteristics
The modes which are supported are given in Table 1.
ITEM
CONDITION
0 to 0.45fs
>0.55fs
VALUE (dB)
±0.02
Pass-band ripple
Stop band
Table 1 Supported sampling ranges
−50
CLOCK MODE
SAMPLING RANGE
Dynamic range
0 to 0.45fs
>114
768fs
512fs
384fs
256fs
192fs
128fs
8 to 55 kHz
8 to 100 kHz
8.3
Noise shaper
8 to 100 kHz
The 5th-order noise shaper operates at 64fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter Stream DAC (FSDAC).
8 to 100 kHz
8 to 100 kHz(1)(2)
8 to 100 kHz(2)
Notes
1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in
192fs mode the sampling frequency should be limited
to 55 kHz.
2. Not supported in the low sampling frequency mode.
An example is given in Table 2 for a 12.228 MHz system
clock input.
2000 Jul 31
7
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
8.4
Filter stream DAC
8.5
Power-on reset
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. No post-filter is needed due to the
inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The UDA1334BTS has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1 μs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) < 0.75 V.
During the reset time the system clock should be running.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
3.0
handbook, halfpage
V
DDD
(V)
1.5
0
t
3.0
V
handbook, halfpage
DDA
13
12
V
DDA
3.0 V
(V)
50 kΩ
50 kΩ
1.5
RESET
CIRCUIT
V
ref(DAC)
C1 >
10 μF
0
t
UDA1334BTS
3.0
V
MGL985
ref(DAC)
(V)
1.5
1.25
0.75
0
t
>1 μs
MGL984
Fig.3 Power-on reset circuit.
Fig.4 Power-on reset timing.
2000 Jul 31
8
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
8.6
Feature settings
8.6.4
POWER CONTROL AND SAMPLING FREQUENCY
SELECT
The features of the UDA1334BTS can be set by control
pins SFOR1, SFOR0, MUTE, DEEM and PCS.
Pin PCS is a 3-level pin and is used to set the mode of the
UDA1334BTS. The definition is given in Table 7.
8.6.1
DIGITAL INTERFACE FORMAT SELECT
Table 7 PCS function definition
The digital audio interface formats (see Fig.5) can be
selected via the pins SFOR1 and SFOR0 as shown in
Table 4.
PCS
LOW
MID
FUNCTION
normal operating mode
low sampling frequency mode
Power-down or Sleep mode
Table 4 Data format selection
HIGH
SFOR1
LOW
SFOR0
LOW
INPUT FORMAT
I2S-bus input
The low sampling frequency mode is required to have a
higher oversampling rate in the noise shaper in order to
improve the signal-to-noise ratio. In this mode the
oversampling ratio of the noise shaper will be 128fs instead
of 64fs.
LOW
HIGH
LOW
LSB-justified 16 bits input
LSB-justified 20 bits input
LSB-justified 24 bits input
HIGH
HIGH
HIGH
8.6.2
MUTE CONTROL
The output signal can be soft muted by setting pin MUTE
to HIGH level as shown in Table 5.
Table 5 Mute control
MUTE
FUNCTION
LOW
HIGH
mute off
mute on
8.6.3
DE-EMPHASIS CONTROL
De-emphasis can be switched on for fs = 44.1 kHz by
setting pin DEEM at HIGH level. The function description
of pin DEEM is given in Table 6.
Table 6 De-emphasis control
DEEM
LOW
FUNCTION
de-emphasis off
de-emphasis on
HIGH
Remark: the de-emphasis function in only supported in the
normal operating mode, not in the low sampling frequency
mode.
2000 Jul 31
9
RIGHT
LEFT
WS
1
2
3
> = 8
1
2
3
> = 8
BCK
DATA
MSB B2
MSB B2
MSB
2
I S-BUS FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
15
2
1
BCK
DATA
B15 LSB
B15 LSB
MSB B2
MSB B2
LSB-JUSTIFIED FORMAT 16 BITS
WS
LEFT
20
RIGHT
20
19
18
17
16
15
2
1
19
18
17
16
15
2
1
BCK
DATA
B19 LSB
B19 LSB
MSB B2
B3
B4
B5
B6
MSB B2
B3
B4
B5
B6
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
20
RIGHT
20
24
23
22
21
19
18
17
16
15
2
1
24
23
22
21
19
18
17
16
15
2
1
BCK
DATA
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MSB B2
B3
B4
B5
B6
B7
B8
B9 B10
B23 LSB
MGS752
LSB-JUSTIFIED FORMAT 24 BITS
Fig.5 Digital audio formats
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
4.0
UNIT
VDD
note 1
−
−
V
Txtal(max)
Tstg
maximum crystal temperature
storage temperature
150
°C
°C
°C
V
−65
+125
+85
Tamb
Ves
ambient temperature
−40
electrostatic handling voltage
human body model
machine model
−2000
−200
+2000
+200
V
Isc(DAC)
short-circuit current of DAC
note 2
output short-circuited to VSSA
output short-circuited to VDDA
−
−
450
300
mA
mA
Note
1. All supply connections must be made to the same power supply.
2. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices.
11 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
145
K/W
12 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-E”.
13 DC CHARACTERISTICS
VDDD = VDDA = 2.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD); unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDA
DAC analog supply voltage note 1
1.8
1.8
2.0
2.0
3.6
3.6
V
VDDD
digital supply voltage
note 1
V
IDDA
DAC analog supply current normal operating mode
at 2.0 V supply voltage
−
−
2.3
3.5
−
−
mA
mA
at 3.0 V supply voltage
Sleep mode
at 2.0 V supply voltage
−
−
125
175
−
−
μA
μA
at 3.0 V supply voltage
2000 Jul 31
11
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
SYMBOL
PARAMETER
CONDITIONS
normal operating mode
at 2.0 V supply voltage
at 3.0 V supply voltage
MIN.
TYP.
MAX.
UNIT
IDDD
digital supply current
−
−
1.4
2.1
−
−
mA
mA
Sleep mode;
at 2.0 V supply voltage
clock running
−
−
250
20
−
−
μA
μA
no clock running
Sleep mode;
at 3.0 V supply voltage
clock running
−
−
375
30
−
−
μA
μA
no clock running
Digital input pins; note 2
VIH
HIGH-level input voltage
at 2.0 V supply voltage
at 3.0 V supply voltage
at 2.0 V supply voltage
at 3.0 V supply voltage
1.3
2.0
−
−
−
−
−
−
3.3
5.0
V
V
VIL
LOW-level input voltage
−0.5
−0.5
−
+0.5
+0.8
1
V
V
⎪ILI⎪
input leakage current
input capacitance
μA
pF
Ci
−
10
3-level input: pin PCS
VIH
VIM
VIL
HIGH-level input voltage
0.9VDDD
0.4VDDD
−0.5
−
−
−
VDDD + 0.5
0.6VDDD
+0.5
V
V
V
MID-level input voltage
LOW-level input voltage
DAC
Vref(DAC)
Ro(ref)
reference voltage
with respect to VSSA
0.45VDDA
0.5VDDA
25
0.55VDDA
V
output resistance on
pin Vref(DAC)
−
−
kΩ
Io(max)
maximum output current
(THD + N)/S < 0.1%;
−
1.6
−
mA
RL = 800 Ω
RL
CL
load resistance
3
−
−
−
kΩ
load capacitance
note 3
−
50
pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
2000 Jul 31
12
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
14 AC CHARACTERISTICS
14.1 2.0 V supply voltage
VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ.; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
DAC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vo(rms)
output voltage (RMS value)
unbalance between channels
at 0 dB (FS) digital input
fs = 44.1 kHz; at 0 dB
−
−
−
−
600
−
mV
ΔVo
0.1
−
−
−
dB
dB
dB
(THD + N)/S total harmonic
distortion-plus-noise to signal
−80
−37
fs = 44.1 kHz; at −60 dB;
A-weighted
ratio
fs = 96 kHz; at 0 dB
−
−
−75
−35
97
−
−
−
−
−
−
dB
dB
dB
dB
dB
dB
fs = 96 kHz; at −60 dB; A-weighted
S/N
signal-to-noise ratio
fs = 44.1 kHz; code = 0; A-weighted −
fs = 96 kHz; code = 0; A-weighted
fripple = 1 kHz; Vripple = 30 mV (p-p)
−
−
−
95
αcs
channel separation
100
60
PSRR
power supply rejection ratio
14.2 3.0 V supply voltage
VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified.
SYMBOL
DAC
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vo(rms)
output voltage (RMS value)
unbalance between channels
at 0 dB (FS) digital input
fs = 44.1 kHz; at 0 dB
−
−
−
−
900
−
mV
ΔVo
0.1
−
−
−
dB
dB
dB
(THD + N)/S total harmonic
distortion-plus-noise to signal
−90
−40
fs = 44.1 kHz; at −60 dB;
A-weighted
ratio
fs = 96 kHz; at 0 dB
−
−
−85
−37
100
98
−
−
−
−
−
−
dB
dB
dB
dB
dB
dB
fs = 96 kHz; at −60 dB; A-weighted
S/N
signal-to-noise ratio
fs = 44.1 kHz; code = 0; A-weighted −
fs = 96 kHz; code = 0; A-weighted
fripple = 1 kHz; Vripple = 30 mV (p-p)
−
−
−
αcs
channel separation
100
60
PSRR
power supply rejection ratio
2000 Jul 31
13
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
14.3 Timing
VDDD = VDDA = 1.8 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages with respect to ground (pins VSSA and VSSD);
unless otherwise specified; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock timing (see Fig.6)
Tsys
system clock cycle time
fsys = 256fs
fsys = 384fs
fsys = 512fs
35
88
780
520
390
ns
23
59
44
−
ns
ns
17
tCWH
system clock HIGH time
system clock LOW time
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
fsys < 19.2 MHz
fsys ≥ 19.2 MHz
0.3Tsys
0.4Tsys
0.3Tsys
0.4Tsys
0.7Tsys ns
0.6Tsys ns
0.7Tsys ns
0.6Tsys ns
−
tCWL
−
−
Reset timing
treset
reset time
1
−
−
μs
Serial interface timing (see Fig.7)
fBCK
bit clock frequency
bit clock HIGH time
bit clock LOW time
rise time
−
−
−
−
−
−
−
−
−
−
64fs
−
Hz
ns
ns
ns
ns
ns
ns
ns
ns
tBCKH
tBCKL
tr
50
50
−
−
20
20
−
tf
fall time
−
tsu(DATAI)
th(DATAI)
tsu(WS)
th(WS)
set-up time data input
hold time data input
set-up time word select
hold time word select
20
0
−
20
10
−
−
Note
1. The typical value of the timing is specified at fs = 44.1 kHz (sampling frequency).
2000 Jul 31
14
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
t
CWH
MGR984
t
CWL
T
sys
Fig.6 System clock timing.
WS
t
h(WS)
t
BCKH
t
su(WS)
t
t
f
r
BCK
t
su(DATAI)
t
BCKL
T
t
cy(BCK)
h(DATAI)
DATAI
MGL880
Fig.7 Serial interface timing.
15
2000 Jul 31
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
15 APPLICATION INFORMATION
analog
digital
supply voltage
supply voltage
R7
1 Ω
R6
1 Ω
C9
C5
47 μF
(16 V)
47 μF
(16 V)
C10
C6
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
SSA
DDA
SSD
DDD
14
15
13
5
4
R5
SYSCLK
system
clock
6
47 Ω
C3
R3
VOUTL
left
output
100 Ω
BCK
WS
47 μF
1
R1
220 kΩ
(16 V)
C1
10 nF
(63 V)
2
DATAI
SFOR1
SFOR0
3
7
C4
R4
100 Ω
VOUTR
right
output
16
12
11
UDA1334BTS
47 μF
(16 V)
R2
220 kΩ
10 nF
(63 V)
C2
MUTE
DEEM
PCS
8
V
ref(DAC)
9
C8
100 nF
(63 V)
C7
47 μF
(16 V)
10
MGL965
Fig.8 Typical application diagram.
2000 Jul 31
16
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
16 PACKAGE OUTLINE
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0.00
1.4
1.2
0.32
0.20
0.25
0.13
5.3
5.1
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1
1.5
0.65
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT369-1
MO-152
2000 Jul 31
17
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
17 SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
17.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
17.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
17.4 Manual soldering
17.3 Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Jul 31
18
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
REFLOW(1)
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
not suitable
suitable
suitable
suitable
suitable
suitable
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Jul 31
19
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
18 DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
19 DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2000 Jul 31
20
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Semiconductors’ product specifications.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2000 Jul 31
21
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/25/02/pp22
Date of release: 2000 Jul 31
Document order number: 9397 750 07239
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