935283722115 [NXP]
AVC SERIES, DUAL 2-BIT TRANSCEIVER, TRUE OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8;
| 型号： | 935283722115 |
| 厂家： | 
NXP |
| 描述： | AVC SERIES, DUAL 2-BIT TRANSCEIVER, TRUE OUTPUT, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, SON-8 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总27页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AVCH2T45
Dual-bit, dual-supply voltage level translator/transceiver;
3-state
Rev. 6 — 2 April 2013
Product data sheet
1. General description
The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (nA and nB), a direction control input
(DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at
any voltage between 0.8 V and 3.6 V making the device suitable for translating between
any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR
are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows
transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
500 Mbps (1.8 V to 3.3 V translation)
320 Mbps (< 1.8 V to 3.3 V translation)
320 Mbps (translate to 2.5 V or 1.8 V)
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
280 Mbps (translate to 1.5 V)
240 Mbps (translate to 1.2 V)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVCH2T45DC
74AVCH2T45GT
74AVCH2T45GF
74AVCH2T45GD
74AVCH2T45GN
74AVCH2T45GS
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
VSSOP8
XSON8
XSON8
XSON8
XSON8
XSON8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 1.95 0.5 mm
extremely thin small outline package; no leads;
SOT1089
8 terminals; body 1.35 1 0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
SOT1116
SOT1203
extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74AVCH2T45DC
74AVCH2T45GT
74AVCH2T45GF
74AVCH2T45GD
74AVCH2T45GN
74AVCH2T45GS
K45
K45
K5
K45
K5
K5
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
2 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
5. Functional diagram
5
DIR
DIR
1A
2
1A
7
6
1B
1B
3
2A
2A
2B
2B
V
V
CC(B)
CC(A)
V
V
CC(B)
CC(A)
001aag577
001aag578
Fig 1. Logic symbol
Fig 2. Logic diagram
6. Pinning information
6.1 Pinning
74AVCH2T45
1
2
3
4
8
7
6
5
V
V
CC(B)
CC(A)
1A
1B
2A
2B
GND
DIR
001aag583
Fig 3. Pin configuration SOT765-1
74AVCH2T45
V
1
2
3
4
8
7
6
5
V
CC(B)
CC(A)
74AVCH2T45
V
1
2
3
4
8
7
6
5
V
CC(B)
CC(A)
1A
1B
1A
1B
2A
2B
2A
2B
GND
DIR
GND
DIR
001aag584
001aaj473
Transparent top view
Transparent top view
Fig 4. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
Fig 5. Pin configuration SOT996-2
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
3 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
6.2 Pin description
Table 3.
Symbol
VCC(A)
1A
Pin description
Pin
1
Description
supply voltage port A and DIR
data input or output
data input or output
ground (0 V)
2
2A
3
GND
DIR
4
5
direction control
2B
6
data input or output
data input or output
supply voltage port B
1B
7
VCC(B)
8
7. Functional description
Table 4.
Function table[1]
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
GND[4]
Input
DIR[3]
Input/output[2]
nA
nB
L
nA = nB
input
Z
input
nB = nA
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The input circuit of the data I/O is always active.
[3] The DIR input circuit is referenced to VCC(A)
.
[4] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
4 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
0.5
0.5
50
0.5
50
0.5
0.5
-
Max
+4.6
+4.6
-
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+4.6
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+4.6
50
100
-
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B)
V
IO
output current
mA
mA
mA
C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
100
65
-
storage temperature
total power dissipation
+150
250
[4]
Tamb = 40 C to +125 C
[1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] CCO is the supply voltage associated with the output port.
V
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
supply voltage A
supply voltage B
input voltage
3.6
V
3.6
V
[1]
VO
output voltage
Active mode
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
40
-
+125
5
C
ns/V
t/V
input transition rise and fall rate
VCCI =0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
5 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
10. Static characteristics
Table 7.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Typical static characteristics at Tamb = 25 C[1][2]
Symbol Parameter Conditions
HIGH-level output voltage VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
LOW-level output voltage VI = VIH or VIL
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
Min
Typ
0.69
0.07
Max
Unit
V
VOH
VOL
II
-
-
-
-
-
V
input leakage current
DIR input; VI = 0 V or 3.6 V;
0.025 0.25 A
VCC(A) = VCC(B) = 0.8 V to 3.6 V
[3]
[4]
[5]
IBHL
bus hold LOW current
bus hold HIGH current
VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V
-
-
-
26
-
-
-
A
A
A
IBHH
IBHLO
24
28
bus hold LOW overdrive
current
[6]
[7]
IBHHO
IOZ
bus hold HIGH overdrive
current
VI = GND to VCCI; VCC(A) = VCC(B) = 1.2 V
-
-
-
-
-
-
26
0.5
0.1
0.1
1.0
-
A
A
A
A
pF
pF
OFF-state output current
A or B port; VO = 0 V or VCCO
;
2.5
1
1
-
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IOFF
power-off leakage current A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
CI
input capacitance
DIR input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
CI/O
input/output capacitance
A and B port; Suspend mode;
4.0
-
VO = VCCO or GND; VCC(A) = VCC(B) = 3.3 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND
and then raising it to VIL max.
[4] The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC
and then lowering it to VIH min.
[5] An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7] For I/O ports, the parameter IOZ includes the input leakage current.
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
6 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 8.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Static characteristics [1][2]
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VIH
HIGH-level
data input
input voltage
VCCI = 0.8 V
0.70VCCI
0.65VCCI
1.6
-
-
-
-
0.70VCCI
0.65VCCI
1.6
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
2
2
VCC(A) = 0.8 V
0.70VCC(A)
-
-
-
-
0.70VCC(A)
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
data input
0.65VCC(A)
0.65VCC(A)
1.6
2
1.6
2
VIL
LOW-level
input voltage
VCCI = 0.8 V
-
-
-
-
0.30VCCI
0.35VCCI
0.7
-
-
-
-
0.30VCCI
0.35VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIR input
0.9
0.9
VCC(A) = 0.8 V
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
VI = VIH or VIL
0.9
0.9
VOH
HIGH-level
output voltage
IO = 100 A;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCCO 0.1
0.85
-
-
-
-
-
-
VCCO 0.1
0.85
-
-
-
-
-
-
V
V
V
V
V
V
IO = 3 mA;
VCC(A) = VCC(B) = 1.1 V
IO = 6 mA;
1.05
1.05
VCC(A) = VCC(B) = 1.4 V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
1.2
1.2
IO = 9 mA;
VCC(A) = VCC(B) = 2.3 V
1.75
1.75
IO = 12 mA;
2.3
2.3
VCC(A) = VCC(B) = 3.0 V
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
7 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
[1][2]
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 100 A;
-
0.1
-
0.1
V
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
IO = 8 mA;
-
-
-
0.25
0.35
0.45
-
-
-
0.25
0.35
0.45
V
V
V
VCC(A) = VCC(B) = 1.65 V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
-
-
0.55
0.7
-
-
0.55
0.7
V
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
II
input leakage DIR input; VI = 0 V or 3.6 V;
current VCC(A) = VCC(B) = 0.8 V to 3.6 V
-
1
-
1.5
A
[3]
IBHL
bus hold LOW A or B port
current
VI = 0.49 V;
15
25
-
-
-
-
15
25
45
90
-
-
-
-
A
A
A
A
VCC(A) = VCC(B) = 1.4 V
VI = 0.58 V;
VCC(A) = VCC(B) = 1.65 V
VI = 0.70 V;
VCC(A) = VCC(B) = 2.3 V
45
VI = 0.80 V;
100
VCC(A) = VCC(B) = 3.0 V
[4]
IBHH
bus hold HIGH A or B port
current
VI = 0.91 V;
VCC(A) = VCC(B) = 1.4 V
15
25
-
-
-
-
15
25
-
-
-
-
A
A
A
A
VI = 1.07 V;
VCC(A) = VCC(B) = 1.65 V
VI = 1.60 V;
VCC(A) = VCC(B) = 2.3 V
45
45
VI = 2.00 V;
100
100
VCC(A) = VCC(B) = 3.0 V
[5]
[6]
[7]
IBHLO
IBHHO
IOZ
bus hold LOW A or B port
overdrive
VCC(A) = VCC(B) = 1.6 V
125
200
300
500
-
-
-
-
125
200
300
500
-
-
-
-
A
A
A
A
current
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
VCC(A) = VCC(B) = 3.6 V
bus hold HIGH A or B port
overdrive
VCC(A) = VCC(B) = 1.6 V
125
200
300
500
-
-
-
125
200
300
500
-
-
A
A
A
A
A
current
VCC(A) = VCC(B) = 1.95 V
VCC(A) = VCC(B) = 2.7 V
-
-
-
-
VCC(A) = VCC(B) = 3.6 V
-
OFF-state
A or B port; VO = 0 V or VCCO
;
5
7.5
output current VCC(A) = VCC(B) = 0.8 to 3.6 V
74AVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
8 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
[1][2]
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
5
-
35
A
A
B port; VI or VO = 0 V to 3.6 V;
-
-
5
-
-
35
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
8
11.5
A
V
CC(A) = 3.6 V; VCC(B) = 0 V
-
8
-
-
11.5
-
A
A
VCC(A) = 0 V; VCC(B) = 3.6 V
2
8
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
8
-
11.5
A
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
A plus B port (ICC(A) + ICC(B));
2
-
-
8
8
-
-
A
A
A
11.5
23
-
16
-
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
;
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND
and then raising it to VIL max.
[4] The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC
and then lowering it to VIH min.
[5] An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6] An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7] For I/O ports, the parameter IOZ includes the input leakage current.
74AVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
9 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
11. Dynamic characteristics
Table 9.
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1]
Symbol Parameter
Conditions
VCC(B)
1.5 V
Unit
0.8 V
15.8
15.8
12.2
11.7
27.5
28.0
1.2 V
8.4
1.8 V
8.0
2.5 V
8.7
3.3 V
9.5
tpd
tdis
ten
propagation delay A to B
8.0
12.4
12.2
7.6
ns
ns
ns
ns
ns
ns
B to A
12.7
12.2
7.9
12.2
12.2
8.2
12.0
12.2
8.7
11.8
12.2
10.2
22.0
21.7
disable time
enable time
DIR to A
DIR to B
DIR to A
DIR to B
20.6
20.6
20.0
20.2
20.4
20.2
20.7
20.9
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions
VCC(A)
1.5 V
Unit
0.8 V
15.8
15.8
12.2
11.7
27.5
28.0
1.2 V
12.7
8.4
1.8 V
12.2
8.0
2.5 V
12.0
8.7
3.3 V
11.8
9.5
tpd
tdis
ten
propagation delay A to B
12.4
8.0
ns
ns
ns
ns
ns
ns
B to A
disable time
enable time
DIR to A
DIR to B
DIR to A
DIR to B
4.9
3.8
3.7
2.8
3.4
9.2
9.0
8.8
8.7
8.6
17.6
17.6
17.0
16.2
16.8
15.9
17.4
14.8
18.1
15.2
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) and VCC(B)
Unit
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
CPD
power dissipation A port: (direction A to B);
1
2
2
2
2
2
pF
pF
capacitance
B port: (direction B to A)
A port: (direction B to A);
B port: (direction A to B)
9
11
11
12
14
17
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = .
74AVCH2T45
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Product data sheet
Rev. 6 — 2 April 2013
10 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 12. Dynamic characteristics for temperature range 40 C to +85 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions VCC(B)
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
2.2
2.2
-
9.0
9.0
0.7
0.8
2.2
1.8
-
6.8
8.0
0.6
0.7
2.2
2.0
-
6.1
7.7
0.5
0.6
2.2
1.7
-
5.7
7.2
0.5
0.5
2.2
2.4
-
6.1 ns
7.1 ns
8.8 ns
7.2 ns
14.3 ns
14.9 ns
B to A
disable time DIR to A
DIR to B
8.8
8.8
8.8
8.8
8.4
6.7
6.9
6.2
enable time DIR to A
DIR to B
17.4
17.8
14.7
15.6
14.6
14.9
13.4
14.5
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
2.0
-
8.0
6.8
0.7
0.8
1.6
1.8
-
5.4
5.4
0.6
0.7
1.6
1.6
-
4.6
5.1
0.5
0.6
1.6
1.2
-
3.7
4.7
0.5
0.5
1.6
1.7
-
3.5 ns
4.5 ns
6.3 ns
5.5 ns
10.0 ns
9.8 ns
B to A
disable time DIR to A
DIR to B
6.3
6.3
6.3
6.3
7.6
5.9
6.0
4.8
enable time DIR to A
DIR to B
14.4
14.3
11.3
11.7
11.1
10.9
9.5
-
-
-
-
10.0
-
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
1.8
-
7.7
6.1
0.6
0.7
1.6
1.8
-
5.1
4.6
0.5
0.5
1.6
1.4
-
4.3
4.4
0.5
0.5
1.6
1.0
-
3.4
3.9
5.5
4.5
8.4
8.9
0.5
0.5
1.6
1.5
-
3.1 ns
3.7 ns
5.5 ns
5.2 ns
8.9 ns
8.6 ns
B to A
disable time DIR to A
DIR to B
5.5
5.5
5.5
7.8
5.7
5.8
enable time DIR to A
DIR to B
13.9
13.2
10.3
10.6
10.2
9.8
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
7.2
5.7
0.5
0.6
1.5
2.0
-
4.7
3.8
4.2
5.2
9.0
8.9
0.5
0.5
1.5
1.5
-
3.9
3.4
4.2
5.1
8.5
8.1
0.5
0.5
1.5
0.6
-
3.0
3.0
4.2
4.2
7.2
7.2
0.5
0.5
1.5
1.1
-
2.6 ns
2.8 ns
4.2 ns
4.8 ns
7.6 ns
6.8 ns
B to A
disable time DIR to A
DIR to B
4.2
7.3
enable time DIR to A
DIR to B
13.0
11.4
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
7.1
6.1
0.5
0.6
1.5
0.7
-
4.5
3.6
4.7
5.5
9.1
9.2
0.5
0.5
1.5
0.6
-
3.7
3.1
4.7
5.5
8.6
8.4
0.5
0.5
1.5
0.7
-
2.8
2.6
4.7
4.1
6.7
7.5
0.5
0.5
1.5
1.7
-
2.4 ns
2.4 ns
4.7 ns
4.7 ns
7.1 ns
7.1 ns
B to A
disable time DIR to A
DIR to B
4.7
7.2
enable time DIR to A
DIR to B
13.3
11.8
-
-
-
-
-
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
74AVCH2T45
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Product data sheet
Rev. 6 — 2 April 2013
11 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7
Symbol Parameter
Conditions VCC(B)
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
2.2
2.2
-
9.9
9.9
0.7
0.8
2.2
1.8
-
7.5
8.8
0.6
0.7
2.2
2.0
-
6.8
8.5
0.5
0.6
2.2
1.7
-
6.3
8.0
0.5
0.5
2.2
2.4
-
6.8 ns
7.9 ns
9.7 ns
8.0 ns
15.9 ns
16.5 ns
B to A
disable time DIR to A
DIR to B
9.7
9.7
9.7
9.7
9.2
7.4
7.6
6.9
enable time DIR to A
DIR to B
19.1
19.6
16.2
17.2
16.1
16.5
14.9
16.0
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
2.0
-
8.8
7.5
0.7
0.8
1.6
1.8
-
6.0
6.0
0.6
0.7
1.6
1.6
-
5.1
5.7
0.5
0.6
1.6
1.2
-
4.1
5.2
0.5
0.5
1.6
1.7
-
3.9 ns
5.0 ns
7.0 ns
6.1 ns
11.1 ns
10.9 ns
B to A
disable time DIR to A
DIR to B
7.0
7.0
7.0
7.0
8.3
6.5
6.6
5.3
enable time DIR to A
DIR to B
15.8
15.8
12.5
13.0
12.3
12.7
10.5
11.1
-
-
-
-
-
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.6
1.8
-
8.5
6.8
0.6
0.7
1.6
1.8
-
5.7
5.1
0.5
0.5
1.6
1.4
-
4.8
4.9
0.5
0.5
1.6
1.0
-
3.8
4.3
6.1
5.0
9.3
9.9
0.5
0.5
1.6
1.5
-
3.5 ns
4.1 ns
6.1 ns
5.8 ns
9.9 ns
9.6 ns
B to A
disable time DIR to A
DIR to B
6.1
6.1
6.1
8.6
6.3
6.4
enable time DIR to A
DIR to B
15.4
14.6
11.4
11.8
11.3
10.9
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
8.0
6.3
0.5
0.6
1.5
2.0
-
5.2
4.2
4.7
5.8
10.0
9.9
0.5
0.5
1.5
1.5
-
4.3
3.8
4.7
5.7
9.5
9.0
0.5
0.5
1.5
0.6
-
3.3
3.3
4.7
4.7
8.0
8.0
0.5
0.5
1.5
1.1
-
2.9 ns
3.1 ns
4.7 ns
5.3 ns
8.4 ns
7.6 ns
B to A
disable time DIR to A
DIR to B
4.7
8.0
enable time DIR to A
DIR to B
14.3
12.7
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation A to B
delay
1.0
1.0
1.5
1.7
-
7.9
6.8
0.5
0.6
1.5
0.7
-
5.0
4.0
0.5
0.5
1.5
0.6
-
4.1
3.5
5.2
6.1
9.6
9.3
0.5
0.5
1.5
0.7
-
3.1
2.9
5.2
4.6
7.5
8.3
0.5
0.5
1.5
1.7
-
2.7 ns
2.7 ns
5.2 ns
5.2 ns
7.9 ns
7.9 ns
B to A
disable time DIR to A
DIR to B
5.2
5.2
7.9
6.1
enable time DIR to A
DIR to B
14.7
13.1
10.1
10.2
-
-
-
-
-
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
12 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
12. Waveforms
V
I
V
M
nA, nB input
GND
t
t
PLH
PHL
V
OH
nB, nA output
V
M
001aak114
V
OL
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. The data input (nA, nB) to output (nB, nA) propagation delay times
V
I
DIR input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae968
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
Table 14. Measurement points
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input[1]
Output[2]
VM
VM
VX
VOL + 0.1 V
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOH 0.1 V
VOH 0.15 V
VOH 0.3 V
VOL + 0.15 V
VOL + 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] CCO is the supply voltage associated with the output port.
V
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
13 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
V
EXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
Table 15. Test data
Supply voltage
VCC(A), VCC(B)
1.1 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI[1]
Load
CL
VEXT
[3]
t/V[2]
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCCO
VCCI
VCCI
VCCI
1.0 ns/V
1.0 ns/V
1.0 ns/V
15 pF
15 pF
15 pF
2 k
2 k
2 k
open
GND
2VCCO
open
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns
[3]
VCCO is the supply voltage associated with the output port.
74AVCH2T45
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Product data sheet
Rev. 6 — 2 April 2013
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74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 9 is an example of the 74AVCH2T45 being used in an
unidirectional logic level-shifting application.
V
V
CC2
CC1
74AVCH2T45
V
V
CC(B)
V
V
V
V
CC(A)
1A
CC1
CC1
CC2
CC2
1
2
3
4
8
7
6
5
1B
2A
2B
GND
DIR
system-1
system-2
001aag585
Fig 9. Unidirectional logic level-shifting application
Table 16. Unidirectional logic level-shifting application
Pin
1
Name
VCC(A)
1A
Function
VCC1
OUT1
OUT2
GND
DIR
Description
supply voltage of system-1 (0.8 V to 3.6 V)
output level depends on VCC1 voltage
output level depends on VCC1 voltage
device GND
2
3
2A
4
GND
DIR
5
the GND (LOW level) determines B port to A port direction
input threshold value depends on VCC2 voltage
input threshold value depends on VCC2 voltage
supply voltage of system-2 (0.8 V to 3.6 V)
6
2B
IN2
7
1B
IN1
8
VCC(B)
VCC2
74AVCH2T45
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Product data sheet
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15 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 10 shows the 74AVCH2T45 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable (OE) pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
V
V
CC1
V
V
CC2
CC1
CC2
74AVCH2T45
V
V
CC(B)
CC(A)
1A
I/O-1
I/O-2
1
2
3
4
8
7
6
5
1B
2A
2B
GND
DIR
DIR CTRL
system-1
system-2
001aag586
Fig 10. Bidirectional logic level-shifting application
Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
Table 17. Bidirectional logic level-shifting application[1]
State DIR CTRL I/O-1
I/O-2
input
Z
Description
1
2
H
H
output
Z
system-1 data to system-2
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on bus hold.
input
output
system-2 data to system-1
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
74AVCH2T45
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Product data sheet
Rev. 6 — 2 April 2013
16 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 18. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
0 V
0
Unit
0.8 V
0.1
0.1
0.1
0.1
0.1
0.7
2.3
1.2 V
0.1
0.1
0.1
0.1
0.1
0.3
1.4
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.9
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.5
2.5 V
0.1
0.7
0.3
0.1
0.1
0.1
0.1
3.3 V
0.1
2.3
1.4
0.9
0.5
0.1
0.1
0 V
A
A
A
A
A
A
A
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
13.4 Enable times
The enable times for the 74AVCH2T45 are calculated from the following formulas:
• ten (DIR to nA) = tdis (DIR to nB) + tpd (nB to nA)
• ten (DIR to nB) = tdis (DIR to nA) + tpd (nA to nB)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74AVCH2T45
initially is transmitting from A to B, then the DIR bit is switched, the B port of the device
must be disabled before presenting it with an input. After the B port has been disabled, an
input signal applied to it appears on the corresponding A port after the specified
propagation delay.
74AVCH2T45
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 2 April 2013
17 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
14. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 11. Package outline SOT765-1 (VSSOP8)
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Product data sheet
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74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 12. Package outline SOT833-1 (XSON8)
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19 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
D
A
A
1
detail X
(2)
(4×)
e
L
(2)
(8×)
b
4
5
e
1
1
8
terminal 1
index area
L
1
X
0
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.5 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1089_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-09
10-04-12
SOT1089
MO-252
Fig 13. Package outline SOT1089 (XSON8)
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Product data sheet
Rev. 6 — 2 April 2013
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74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
v
C
C
A
B
b
e
L
1
y
1
y
w
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
1
L
2
v
w
y
y
1
max
mm nom 0.5
min
0.05 0.35 2.1 3.1
0.00 0.15 1.9 2.9
0.5 0.15 0.6
0.3 0.05 0.4
0.5 1.5
0.1 0.05 0.05 0.1
sot996-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
07-12-21
12-11-20
SOT996-2
Fig 14. Package outline SOT996-2 (XSON8)
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Rev. 6 — 2 April 2013
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74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
b
4
(2)
1
2
3
(4×)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.35 0.04 0.20 1.25 1.05
0.35 0.40
0.15 1.20 1.00 0.55 0.3 0.30 0.35
0.12 1.15 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1116_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1116
Fig 15. Package outline SOT1116 (XSON8)
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Product data sheet
Rev. 6 — 2 April 2013
22 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
b
4
(2)
(4×)
1
2
3
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1203_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1203
Fig 16. Package outline SOT1203 (XSON8)
74AVCH2T45
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Product data sheet
Rev. 6 — 2 April 2013
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NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
15. Abbreviations
Table 19. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
16. Revision history
Table 20. Revision history
Document ID
Release date
20130402
Data sheet status
Change notice
Supersedes
74AVCH2T45 v.6
Modifications:
Product data sheet
-
74AVCH2T45 v.5
• For type number 74AVCH2T45GD XSON8U has changed to XSON8.
74AVCH2T45 v.5
Modifications:
20111214
Product data sheet
-
74AVCH2T45 v.4
• Legal pages updated.
74AVCH2T45 v.4
74AVCH2T45 v.3
74AVCH2T45 v.2
74AVCH2T45 v.1
20101124
20090506
20090203
20070703
Product data sheet
-
-
-
-
74AVCH2T45 v.3
74AVCH2T45 v.2
74AVCH2T45 v.1
-
Product data sheet
Product data sheet
Product data sheet
74AVCH2T45
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Product data sheet
Rev. 6 — 2 April 2013
24 of 27
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NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
17.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74AVCH2T45
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Product data sheet
Rev. 6 — 2 April 2013
25 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
Rev. 6 — 2 April 2013
26 of 27
74AVCH2T45
NXP Semiconductors
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
19. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
Application information. . . . . . . . . . . . . . . . . . 15
Unidirectional logic level-shifting application . 15
Bidirectional logic level-shifting application. . . 16
Power-up considerations . . . . . . . . . . . . . . . . 17
Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 17
13.1
13.2
13.3
13.4
14
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 26
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 April 2013
Document identifier: 74AVCH2T45
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