935284761125 [NXP]
LVC/LCX/Z SERIES, 2-BIT TRANSCEIVER, TRUE OUTPUT, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8;
| 型号： | 935284761125 |
| 厂家： | 
NXP |
| 描述： | LVC/LCX/Z SERIES, 2-BIT TRANSCEIVER, TRUE OUTPUT, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总36页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Rev. 8 — 29 March 2013
Product data sheet
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two 2-bits
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A)
and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and
pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features and benefits
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 16 A maximum ICC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2T45DC
74LVCH2T45DC
74LVC2T45GT
74LVCH2T45GT
74LVC2T45GF
74LVCH2T45GF
74LVC2T45GD
74LVCH2T45GD
74LVC2T45GM
74LVCH2T45GM
74LVC2T45GN
74LVCH2T45GN
74LVC2T45GS
74LVCH2T45GS
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
XSON8
XSON8
XSON8
XQFN8
XSON8
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 1.95 0.5 mm
extremely thin small outline package; no leads;
SOT1089
8 terminals; body 1.35 1 0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm
plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm
SOT902-2
SOT1116
SOT1203
extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC2T45DC
74LVCH2T45DC
74LVC2T45GT
74LVCH2T45GT
74LVC2T45GF
74LVCH2T45GF
74LVC2T45GD
74LVCH2T45GD
74LVC2T45GM
74LVCH2T45GM
V45
X45
V45
X45
V5
X5
V45
X45
V45
X45
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
2 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 2.
Marking …continued
Type number
Marking code[1]
74LVC2T45GN
74LVCH2T45GN
74LVC2T45GS
74LVCH2T45GS
V5
X5
V5
X5
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
5
DIR
DIR
2
1A
1A
7
1B
1B
2B
3
2A
2A
6
2B
V
V
CC(B)
CC(A)
V
V
CC(A)
CC(B)
001aag577
001aag578
Fig 1. Logic symbol
Fig 2. Logic diagram
6. Pinning information
6.1 Pinning
74LVC2T45
74LVCH2T45
V
1
2
3
4
8
7
6
5
V
CC(B)
CC(A)
1A
1B
74LVC2T45
74LVCH2T45
2A
2B
1
2
3
4
8
7
6
5
V
V
CC(B)
CC(A)
1A
1B
GND
DIR
2A
2B
GND
DIR
001aai905
Transparent top view
001aai904
Fig 3. Pin configuration SOT765-1
Fig 4. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
3 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
74LVC2T45
74LVCH2T45
terminal 1
index area
74LVC2T45
74LVCH2T45
1B
1
7
6
5
V
CC(A)
V
1
2
3
4
8
7
6
5
V
CC(B)
CC(A)
2B
2
3
1A
2A
1A
1B
2A
2B
DIR
GND
DIR
001aai906
001aaj617
Transparent top view
Transparent top view
Fig 5. Pin configuration SOT996-2
Fig 6. Pin configuration SOT902-2
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT902-2
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
VCC(A)
1A
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
8
supply voltage A (port A and DIR)
data input or output
data input or output
ground (0 V)
2A
GND
DIR
2B
direction control
data input or output
data input or output
supply voltage B (port B)
1B
VCC(B)
7. Functional description
Table 4.
Function table[1]
Supply voltage
VCC(A), VCC(B)
1.2 V to 5.5 V
1.2 V to 5.5 V
GND[3]
Input
DIR
L
Input/output[2]
nA
nB
nA = nB
input
Z
input
nB = nA
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The input circuit of the data I/O is always active.
[3] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
4 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
0.5
0.5
50
0.5
50
0.5
0.5
-
Max
+6.5
+6.5
-
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+6.5
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+6.5
50
100
-
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B)
V
[2]
IO
output current
mA
mA
mA
C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
100
65
-
storage temperature
total power dissipation
+150
250
[4]
Tamb = 40 C to +125 C
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] CCO is the supply voltage associated with the output port.
V
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
Max
5.5
5.5
5.5
VCCO
5.5
+125
20
Unit
V
supply voltage A
supply voltage B
input voltage
1.2
1.2
V
0
V
[1]
[2]
VO
output voltage
Active mode
0
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
40
C
t/V
input transition rise and fall rate VCCI = 1.2 V
VCCI = 1.4 V to 1.95 V
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
ns/V
20
VCCI = 2.3 V to 2.7 V
VCCI = 3 V to 3.6 V
VCCI = 4.5 V to 5.5 V
20
10
5
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
5 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
10. Static characteristics
Table 7.
Typical static characteristics at Tamb = 25 C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
HIGH-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V
LOW-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V
Min
Typ
Max
Unit
VOH
VOL
II
[1]
-
1.09
-
V
[1]
[2]
-
-
0.07
-
-
V
input leakage current
DIR input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V
1
A
[2]
[2]
IBHL
bus hold LOW current
bus hold HIGH current
A or B port; VI = 0.42 V; VCCI = 1.2 V
A or B port; VI = 0.78 V; VCCI = 1.2 V
A or B port; VCCI = 1.2 V
-
-
-
19
-
-
-
A
A
A
IBHH
IBHLO
19
19
[2][3]
bus hold LOW overdrive
current
[2][3]
[1]
IBHHO
IOZ
bus hold HIGH overdrive
current
A or B port; VCCI = 1.2 V
-
-
-
-
-
-
19
-
-
A
A
A
A
pF
pF
OFF-state output current
A or B port; VO = 0 V or VCCO
VCCO = 1.2 V to 5.5 V
;
1
1
1
-
IOFF
power-off leakage current A port; VI or VO = 0 V to 5.5 V;
VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V
-
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V
-
CI
input capacitance
DIR input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
2.2
6.0
CI/O
input/output capacitance
A and B port; suspend mode;
-
VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH
.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
6 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
[1]
VIH
HIGH-level
data input
input voltage
VCCI = 1.2 V
0.8VCCI
0.65VCCI
1.7
-
-
-
-
-
0.8VCCI
0.65VCCI
1.7
-
-
-
-
-
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
DIR input
2.0
2.0
0.7VCCI
0.7VCCI
VCCI = 1.2 V
0.8VCC(A)
0.65VCC(A)
1.7
-
-
-
-
-
0.8VCC(A)
0.65VCC(A)
1.7
-
-
-
-
-
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
data input
2.0
2.0
0.7VCC(A)
0.7VCC(A)
[1]
VIL
LOW-level
input voltage
VCCI = 1.2 V
-
-
-
-
-
0.2VCCI
0.35VCCI
0.7
-
-
-
-
-
0.2VCCI
0.35VCCI
0.7
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
DIR input
0.8
0.8
0.3VCCI
0.3VCCI
VCCI = 1.2 V
-
-
-
-
-
0.2VCC(A)
0.35VCC(A)
0.7
-
-
-
-
-
0.2VCC(A)
0.35VCC(A)
0.7
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
VI = VIH
0.8
0.8
0.3VCC(A)
0.3VCC(A)
VOH
HIGH-level
output voltage
[2]
IO = 100 A;
VCCO 0.1
-
VCCO 0.1
-
V
VCCO = 1.2 V to 4.5 V
IO = 6 mA; VCCO = 1.4 V
IO = 8 mA; VCCO = 1.65 V
IO = 12 mA; VCCO = 2.3 V
IO = 24 mA; VCCO = 3.0 V
IO = 32 mA; VCCO = 4.5 V
1.0
1.2
1.9
2.4
3.8
-
-
-
-
-
1.0
1.2
1.9
2.4
3.8
-
-
-
-
-
V
V
V
V
V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
7 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
[2]
VOL
LOW-level
VI = VIL
output voltage
IO = 100 A;
-
0.1
-
0.1
V
VCCO = 1.2 V to 4.5 V
IO = 6 mA; VCCO = 1.4 V
IO = 8 mA; VCCO = 1.65 V
IO = 12 mA; VCCO = 2.3 V
IO = 24 mA; VCCO = 3.0 V
IO = 32 mA; VCCO = 4.5 V
-
-
-
-
-
-
0.3
0.45
0.3
-
-
-
-
-
-
0.3
0.45
0.3
V
V
V
0.55
0.55
2
0.55
0.55
10
V
V
II
input leakage DIR input; VI = 0 V to 5.5 V;
current CCI = 1.2 V to 5.5 V
A
V
[1]
IBHL
bus hold LOW A or B port
current
VI = 0.49 V; VCCI = 1.4 V
15
25
-
-
-
-
-
10
20
-
-
-
-
-
A
A
A
A
A
VI = 0.58 V; VCCI = 1.65 V
VI = 0.70 V; VCCI = 2.3 V
VI = 0.80 V; VCCI = 3.0 V
VI = 1.35 V; VCCI = 4.5 V
45
45
100
100
80
100
[1]
IBHH
IBHLO
IBHHO
IOZ
bus hold HIGH A or B port
current
VI = 0.91 V; VCCI = 1.4 V
VI = 1.07 V; VCCI = 1.65 V
VI = 1.60 V; VCCI = 2.3 V
VI = 2.00 V; VCCI = 3.0 V
VI = 3.15 V; VCCI = 4.5 V
15
25
-
-
-
-
-
10
20
45
80
100
-
-
-
-
-
A
A
A
A
A
45
100
100
[1][3]
[1][3]
[2]
bus hold LOW A or B port
overdrive
VCCI = 1.6 V
125
200
300
500
900
-
-
-
-
-
125
200
300
500
900
-
-
-
-
-
A
A
A
A
A
current
VCCI = 1.95 V
VCCI = 2.7 V
VCCI = 3.6 V
VCCI = 5.5 V
bus hold HIGH A or B port
overdrive
VCCI = 1.6 V
125
200
300
500
900
-
-
-
125
200
300
500
900
-
-
A
A
A
A
A
A
current
VCCI = 1.95 V
VCCI = 2.7 V
-
-
-
VCCI = 3.6 V
-
-
-
VCCI = 5.5 V
-
OFF-state
A or B port; VO = 0 V or VCCO
;
2
10
output current VCCO = 1.2 V to 5.5 V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
8 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 5.5 V;
VCC(A) = 0 V;
-
2
-
10
A
V
CC(B) = 1.2 V to 5.5 V
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V;
-
2
-
10
A
VCC(A) = 1.2 V to 5.5 V
[1]
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(A), VCC(B) = 1.65 V to 5.5 V
VCC(A) = 5.5 V; VCC(B) = 0 V
-
-
8
3
2
-
-
-
8
3
2
-
A
A
A
A
-
-
VCC(A) = 0 V; VCC(B) = 5.5 V
2
2
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(A), VCC(B) = 1.65 V to 5.5 V
VCC(B) = 0 V; VCC(A) = 5.5 V
-
-
8
3
-
-
-
8
3
-
A
A
A
A
2
-
2
-
VCC(B) = 5.5 V; VCC(A) = 0 V
2
2
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(A), VCC(B) = 1.65 V to 5.5 V
-
-
16
4
-
-
16
4
A
A
ICC
additional
per input;
supply current VCC(A), VCC(B) = 3.0 V to 5.5 V
[4]
[4]
A port; A port at VCC(A) 0.6 V;
DIR at VCC(A); B port = open
-
-
50
50
-
-
75
75
A
A
DIR input; DIR at VCC(A) 0.6 V;
A port at VCC(A) or GND;
B port = open
B port; B port at VCC(B) 0.6 V;
-
50
-
75
A
DIR at GND; A port = open
[1] VCCI is the supply voltage associated with the data input port.
[2] CCO is the supply voltage associated with the output port.
V
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH
.
[4] For non bus hold parts only (74LVC2T45).
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
9 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
11. Dynamic characteristics
Table 9.
Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V
10.6
10.6
10.1
10.1
9.4
1.5 V
8.1
1.8 V
2.5 V
5.8
3.3 V
5.3
5.0 V
5.1
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
7.0
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B to A
9.5
8.5
8.3
8.2
HIGH to LOW
propagation delay
A to B
7.1
6.0
5.3
5.2
5.4
B to A
8.6
8.1
7.8
7.6
7.6
HIGH to OFF-state
propagation delay
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
9.4
9.4
9.4
9.4
9.4
12.0
7.1
9.4
9.0
7.8
8.4
7.9
LOW to OFF-state
propagation delay
7.1
7.1
7.1
7.1
7.1
9.5
7.8
7.7
6.9
7.6
7.0
[1]
[1]
[1]
[1]
OFF-state to HIGH
propagation delay
20.1
17.7
22.1
19.5
17.3
15.2
18.0
16.5
16.7
14.1
17.1
15.4
15.4
12.9
15.6
14.7
15.9
12.4
16.0
14.6
15.2
12.2
15.5
14.8
OFF-state to LOW
propagation delay
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”.
Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(A)
Unit
1.2 V
10.6
10.6
10.1
10.1
9.4
1.5 V
9.5
1.8 V
2.5 V
8.5
3.3 V
8.3
5.0 V
8.2
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
9.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B to A
8.1
5.8
5.3
5.1
HIGH to LOW
propagation delay
A to B
8.6
8.1
7.8
7.6
7.6
B to A
7.1
6.0
5.3
5.2
5.4
HIGH to OFF-state
propagation delay
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
6.5
5.7
4.1
4.1
3.0
12.0
7.1
6.1
5.4
4.6
4.3
4.0
LOW to OFF-state
propagation delay
4.9
4.5
3.2
3.4
2.5
9.5
7.3
6.6
5.9
5.7
5.6
[1]
[1]
[1]
[1]
OFF-state to HIGH
propagation delay
20.1
17.7
22.1
19.5
15.4
14.4
13.2
15.1
13.6
13.5
11.4
13.8
11.7
11.7
9.9
11.0
11.7
9.5
10.7
10.7
9.4
OFF-state to LOW
propagation delay
11.9
11.7
10.6
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
10 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) and VCC(B)
Unit
1.8 V
2.5 V
3.3 V
5.0 V
CPD
power dissipation A port: (direction A to B);
2
3
3
4
pF
pF
capacitance
B port: (direction B to A)
A port: (direction B to A);
B port: (direction A to B)
15
16
16
18
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = .
Table 12. Dynamic characteristics for temperature range 40 C to +85 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.8
2.8
2.6
2.6
3.0
3.5
2.4
2.8
-
21.3
21.3
19.3
19.3
18.7
24.8
11.4
18.3
39.6
32.7
44.1
38.0
2.4
2.6
2.2
2.4
3.0
3.5
2.4
3.0
-
17.6
19.1
15.3
17.3
18.7
23.6
11.4
17.2
36.3
29.0
40.9
34.0
2.0
2.3
1.8
2.3
3.0
3.0
2.4
2.5
-
13.5
14.9
11.8
13.2
18.7
11.0
11.4
9.4
1.7
2.3
1.7
2.2
3.0
3.3
2.4
3.0
-
11.8
12.4
10.9
11.3
18.7
11.3
11.4
10.1
22.5
23.2
22.6
29.6
1.6
2.2
1.7
2.3
3.0
2.8
2.4
2.5
-
10.5 ns
12.0 ns
10.8 ns
11.0 ns
18.7 ns
10.3 ns
11.4 ns
9.4 ns
21.4 ns
21.9 ns
21.3 ns
29.5 ns
HIGH to LOW
propagation delay
HIGH to OFF-state DIR to A
propagation delay
DIR to B
LOW to OFF-state DIR to A
propagation delay
DIR to B
[1]
[1]
[1]
[1]
OFF-state to HIGH DIR to A
propagation delay
24.3
24.9
24.2
30.5
DIR to B
-
-
-
-
-
OFF-state to LOW DIR to A
propagation delay
-
-
-
-
-
DIR to B
-
-
-
-
-
VCC(A) = 1.65 V to 1.95 V
tPLH
tPHL
tPHZ
tPLZ
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.6
2.4
2.4
2.2
2.9
3.2
2.4
2.5
19.1
17.6
17.3
15.3
17.1
24.1
10.5
17.6
2.2
2.2
2.0
2.0
2.9
3.2
2.4
2.6
17.7
17.7
14.3
14.3
17.1
21.9
10.5
16.0
2.2
2.3
1.6
2.1
2.9
2.7
2.4
2.2
9.3
16.0
8.5
1.7
2.1
1.8
2.0
2.9
3.0
2.4
2.7
7.2
15.5
7.1
1.4
1.9
1.7
1.8
2.9
2.5
2.4
2.4
6.8 ns
15.1 ns
7.0 ns
12.2 ns
17.1 ns
8.2 ns
10.5 ns
7.1 ns
HIGH to LOW
propagation delay
12.9
17.1
11.5
10.5
9.2
12.6
17.1
10.3
10.5
8.4
HIGH to OFF-state DIR to A
propagation delay
DIR to B
LOW to OFF-state DIR to A
propagation delay
DIR to B
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
11 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range 40 C to +85 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max Min Max Min Max Min Max
[1]
tPZH
OFF-state to HIGH DIR to A
propagation delay
-
-
-
-
35.2
29.6
39.4
34.4
-
-
-
-
33.7
28.2
36.2
31.4
-
-
-
-
25.2
19.8
24.4
25.6
-
-
-
-
23.9
17.7
22.9
24.2
-
-
-
-
22.2 ns
[1]
[1]
[1]
DIR to B
17.3 ns
20.4 ns
24.1 ns
tPZL
OFF-state to LOW DIR to A
propagation delay
DIR to B
VCC(A) = 2.3 V to 2.7 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.3
2.0
2.3
1.8
2.1
3.0
1.7
2.3
-
17.9
13.5
15.8
11.8
8.1
2.3
2.2
2.1
1.9
2.1
3.0
1.7
2.5
-
16.0
9.3
1.5
1.5
1.4
1.4
2.1
2.5
1.7
2.0
-
8.5
8.5
1.3
1.4
1.3
1.3
2.1
2.8
1.7
2.5
-
6.2
8.0
1.1
1.0
0.9
0.9
2.1
2.3
1.7
1.8
-
4.8 ns
7.5 ns
4.6 ns
6.2 ns
8.1 ns
6.9 ns
5.8 ns
5.8 ns
13.3 ns
10.6 ns
13.1 ns
12.7 ns
HIGH to LOW
propagation delay
12.9
8.5
7.5
5.4
7.5
7.0
HIGH to OFF-state DIR to A
propagation delay
8.1
8.1
8.1
DIR to B
22.5
5.8
21.4
5.8
11.0
5.8
9.3
LOW to OFF-state DIR to A
propagation delay
5.8
DIR to B
14.6
28.1
23.7
34.3
23.9
13.2
22.5
21.8
29.9
21.0
9.0
8.4
[1]
[1]
[1]
[1]
OFF-state to HIGH DIR to A
propagation delay
17.5
14.3
18.5
15.6
16.4
12.0
16.3
13.5
DIR to B
-
-
-
-
-
OFF-state to LOW DIR to A
propagation delay
-
-
-
-
-
DIR to B
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.3
1.7
2.2
1.7
2.3
2.9
2.0
2.3
-
17.1
11.8
15.6
10.9
7.3
2.1
1.7
2.0
1.8
2.3
2.9
2.0
2.4
-
15.5
7.2
1.4
1.3
1.3
1.3
2.3
2.3
2.0
1.9
-
8.0
6.2
0.8
0.7
0.8
0.8
2.3
2.7
2.0
2.3
-
5.6
5.6
0.7
0.6
0.7
0.7
2.7
2.2
2.0
1.7
-
4.4 ns
5.4 ns
4.0 ns
4.5 ns
7.3 ns
6.3 ns
5.6 ns
4.9 ns
10.3 ns
10.0 ns
10.8 ns
11.3 ns
HIGH to LOW
propagation delay
12.6
7.1
7.0
5.0
5.4
5.0
HIGH to OFF-state DIR to A
propagation delay
7.3
7.3
7.3
DIR to B
18.0
5.6
16.5
5.6
10.1
5.6
8.6
LOW to OFF-state DIR to A
propagation delay
5.6
DIR to B
13.6
25.4
22.7
28.9
22.9
12.5
19.7
21.1
23.6
19.9
7.8
7.1
[1]
[1]
[1]
[1]
OFF-state to HIGH DIR to A
propagation delay
14.0
13.6
15.5
14.3
12.7
11.2
13.6
12.3
DIR to B
-
-
-
-
-
OFF-state to LOW DIR to A
propagation delay
-
-
-
-
-
DIR to B
-
-
-
-
-
VCC(A) = 4.5 V to 5.5 V
tPLH
tPHL
tPHZ
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.2
1.6
2.3
1.7
1.7
2.9
16.6
10.5
15.3
10.8
5.4
1.9
1.4
1.8
1.7
1.7
2.9
15.1
6.8
1.0
1.0
1.0
0.9
1.7
2.3
7.5
4.8
6.2
4.6
5.4
9.7
0.7
0.7
0.7
0.7
1.7
2.7
5.4
4.4
4.5
4.0
5.4
8.0
0.5
0.5
0.5
0.5
1.7
2.5
3.9 ns
3.9 ns
3.5 ns
3.5 ns
5.4 ns
5.7 ns
HIGH to LOW
propagation delay
12.2
7.0
HIGH to OFF-state DIR to A
propagation delay
5.4
DIR to B
17.3
16.1
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
12 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range 40 C to +85 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max Min Max Min Max Min Max
tPLZ
tPZH
tPZL
LOW to OFF-state DIR to A
1.4
3.7
1.4
3.7
1.3
3.7
7.4
1.0
3.7
7.0
0.9
3.7 ns
propagation delay
DIR to B
2.3
13.1
23.6
20.3
28.1
20.7
2.4
12.1
18.9
18.8
23.1
17.6
1.9
2.3
1.8
4.5 ns
8.4 ns
7.6 ns
9.2 ns
8.9 ns
[1]
[1]
[1]
[1]
OFF-state to HIGH DIR to A
-
-
-
-
-
-
-
-
-
-
-
-
12.2
11.2
14.3
11.6
-
-
-
-
11.4
9.1
-
-
-
-
propagation delay
DIR to B
OFF-state to LOW DIR to A
12.0
9.9
propagation delay
DIR to B
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”.
Table 13. Dynamic characteristics for temperature range 40 C to +125 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max
Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.5
2.5
2.3
2.3
2.7
3.1
2.1
2.5
-
23.5
23.5
21.3
21.3
20.6
27.3
12.6
20.2
43.7
36.1
48.6
41.9
2.1
2.3
1.9
2.1
2.7
3.1
2.1
2.7
-
19.4
21.1
16.9
19.1
20.6
26.0
12.6
19.0
40.1
32.0
45.1
37.5
1.8
2.0
1.6
2.0
2.7
2.7
2.1
2.2
-
14.9
16.4
13.0
14.6
20.6
12.1
12.6
10.4
26.8
27.5
26.7
33.6
1.5
2.0
1.5
1.9
2.7
2.9
2.1
2.7
-
13.0
13.7
12.0
12.5
20.6
12.5
12.6
11.2
24.9
25.6
25.0
32.6
1.4
1.9
1.5
2.0
2.7
2.5
2.1
2.2
-
11.6 ns
13.2 ns
11.9 ns
12.1 ns
20.6 ns
11.4 ns
12.6 ns
10.4 ns
23.6 ns
24.2 ns
23.5 ns
32.5 ns
HIGH to LOW
propagation delay
HIGH to OFF-state DIR to A
propagation delay
DIR to B
LOW to OFF-state DIR to A
propagation delay
DIR to B
[1]
[1]
[1]
[1]
OFF-state to HIGH DIR to A
propagation delay
DIR to B
-
-
-
-
-
OFF-state to LOW DIR to A
propagation delay
-
-
-
-
-
DIR to B
-
-
-
-
-
VCC(A) = 1.65 V to 1.95 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.3
2.1
2.1
1.9
2.6
2.8
2.1
2.2
-
21.1
19.4
19.1
16.9
18.9
26.6
11.6
19.4
38.8
32.7
1.9
1.9
1.8
1.8
2.6
2.8
2.1
2.3
-
19.5
19.5
15.8
15.8
18.9
24.1
11.6
17.6
37.1
31.1
1.9
2.0
1.4
1.8
2.6
2.4
2.1
1.9
-
10.3
17.6
9.4
1.5
1.8
1.6
1.8
2.6
2.7
2.1
2.4
-
8.0
17.1
7.9
1.2
1.7
1.5
1.6
2.6
2.2
2.1
2.1
-
7.5 ns
16.7 ns
7.7 ns
13.5 ns
18.9 ns
9.1 ns
11.6 ns
7.9 ns
24.6 ns
19.1 ns
HIGH to LOW
propagation delay
14.2
18.9
12.7
11.6
10.2
27.8
21.9
13.9
18.9
11.4
11.6
9.3
HIGH to OFF-state DIR to A
propagation delay
DIR to B
LOW to OFF-state DIR to A
propagation delay
DIR to B
[1]
[1]
OFF-state to HIGH DIR to A
propagation delay
26.4
19.6
DIR to B
-
-
-
-
-
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
13 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range 40 C to +125 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max
39.9
34.7
Min Max Min Max Min Max
[1]
tPZL
OFF-state to LOW DIR to A
-
-
43.5
38.0
-
-
-
-
26.9
28.3
-
-
25.3
26.8
-
-
22.6 ns
propagation delay
[1]
DIR to B
26.6 ns
VCC(A) = 2.3 V to 2.7 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.0
1.8
2.0
1.6
1.8
2.7
1.5
2.0
-
19.7
14.9
17.4
13.0
9.0
2.0
1.9
1.8
1.7
1.8
2.7
1.5
2.2
-
17.6
10.3
14.2
9.4
1.3
1.3
1.2
1.2
1.8
2.2
1.5
1.8
-
9.4
9.4
1.1
1.2
1.1
1.1
1.8
2.5
1.5
2.2
-
6.9
8.8
0.9
0.9
0.8
0.8
1.8
2.0
1.5
1.6
-
5.3 ns
8.3 ns
5.1 ns
6.9 ns
9.0 ns
7.6 ns
6.4 ns
6.4 ns
14.7 ns
11.7 ns
14.5 ns
14.1 ns
HIGH to LOW
propagation delay
8.3
6.0
8.3
7.7
HIGH to OFF-state DIR to A
propagation delay
9.0
9.0
9.0
DIR to B
24.8
6.4
23.6
6.4
12.1
6.4
10.3
6.4
LOW to OFF-state DIR to A
propagation delay
DIR to B
16.1
31.0
26.1
37.8
26.4
14.6
24.9
24.0
33.0
23.2
9.9
9.3
[1]
[1]
[1]
[1]
OFF-state to HIGH DIR to A
propagation delay
19.3
15.8
20.4
17.3
18.1
13.3
18.0
15.0
DIR to B
-
-
-
-
-
OFF-state to LOW DIR to A
propagation delay
-
-
-
-
-
DIR to B
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.0
1.5
1.9
1.5
2.0
2.6
1.8
2.0
-
18.9
13.0
17.2
12.0
8.1
1.8
1.5
1.8
1.6
2.0
2.6
1.8
2.1
-
17.1
8.0
1.2
1.1
1.1
1.1
2.0
2.0
1.8
1.7
-
8.8
6.9
0.7
0.6
0.7
0.7
2.0
2.4
1.8
2.0
-
6.2
6.2
0.6
0.5
0.6
0.6
2.4
1.9
1.8
1.5
-
4.9 ns
6.0 ns
4.4 ns
5.0 ns
8.1 ns
7.0 ns
6.2 ns
5.4 ns
11.4 ns
11.1 ns
12.0 ns
12.5 ns
HIGH to LOW
propagation delay
13.9
7.9
7.7
5.5
6.0
5.5
HIGH to OFF-state DIR to A
propagation delay
8.1
8.1
8.1
DIR to B
19.8
6.2
18.2
6.2
11.2
6.2
9.5
LOW to OFF-state DIR to A
propagation delay
6.2
DIR to B
15.0
28.0
25.1
31.8
25.3
13.8
21.8
23.3
26.1
22.0
8.6
7.9
[1]
[1]
[1]
[1]
OFF-state to HIGH DIR to A
propagation delay
15.5
15.0
17.2
15.8
14.1
12.4
15.0
13.6
DIR to B
-
-
-
-
-
OFF-state to LOW DIR to A
propagation delay
-
-
-
-
-
DIR to B
-
-
-
-
-
VCC(A) = 4.5 V to 5.5 V
tPLH
tPHL
tPHZ
tPLZ
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
1.9
1.4
2.0
1.5
1.5
2.6
1.2
2.0
18.3
11.6
16.9
11.9
6.0
1.7
1.2
1.6
1.5
1.5
2.6
1.2
2.1
16.7
7.5
0.9
0.9
0.9
0.8
1.5
2.0
1.1
1.7
8.3
5.3
6.9
5.1
6.0
10.7
4.1
8.2
0.6
0.6
0.6
0.6
1.5
2.4
0.9
2.0
6.0
4.9
5.0
4.4
6.0
8.8
4.1
7.7
0.4
0.4
0.4
0.4
1.5
2.2
0.8
1.6
4.3 ns
4.3 ns
3.9 ns
3.9 ns
6.0 ns
6.3 ns
4.1 ns
5.0 ns
HIGH to LOW
propagation delay
13.5
7.7
HIGH to OFF-state DIR to A
propagation delay
6.0
DIR to B
19.1
4.1
17.8
4.1
LOW to OFF-state DIR to A
propagation delay
DIR to B
14.5
13.4
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
14 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range 40 C to +125 C …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max
20.9
20.8
25.5
19.5
Min Max Min Max Min Max
[1]
tPZH
OFF-state to HIGH DIR to A
propagation delay
-
-
-
-
26.1
22.4
31.0
22.9
-
-
-
-
-
-
-
-
13.5
12.4
15.8
12.9
-
-
-
-
12.6
10.1
13.2
11.0
-
-
-
-
9.3 ns
[1]
[1]
[1]
DIR to B
8.4 ns
10.2 ns
9.9 ns
tPZL
OFF-state to LOW DIR to A
propagation delay
DIR to B
[1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”.
12. Waveforms
V
I
V
M
nA, nB input
GND
t
t
PLH
PHL
V
OH
nB, nA output
V
V
M
001aaj644
OL
Measurement points are given in Table 14.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 7. The data input (A, B) to output (B, A) propagation delay times
V
I
DIR input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae968
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Enable and disable times
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
15 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Table 14. Measurement points
Supply voltage
VCC(A), VCC(B)
1.2 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 5.5 V
Input[1]
Output[2]
VM
VM
VX
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.1 V
VOL + 0.15 V
VOL + 0.3 V
VOH 0.1 V
VOH 0.15 V
VOH 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
V
EXT = External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
Table 15. Test data
Supply voltage
VCC(A), VCC(B)
1.2 V to 5.5 V
Input
VI[1]
Load
CL
VEXT
[3]
t/V[2]
RL
2 k
tPLH, tPHL
tPZH, tPHZ
GND
tPZL, tPLZ
VCCI
1.0 ns/V
15 pF
open
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns.
[3]
VCCO is the supply voltage associated with the output port.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
16 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
13. Typical propagation delay characteristics
001aai907
001aai908
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
(1)
(1)
10
8
10
8
(2)
(3)
(2)
(3)
(4)
(4)
(5)
(6)
6
6
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai909
001aai910
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
(1)
(1)
(2)
(3)
(4)
(2)
(3)
10
8
10
8
(5)
(6)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3)
VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6)
VCC(B) = 5.0 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.2 V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
17 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
001aai911
001aai912
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
(1)
10
8
10
8
(1)
(2)
(2)
(3)
6
6
(3)
(4)
(4)
(5)
(6)
4
4
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai913
001aai914
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
10
8
10
8
(1)
(1)
(2)
(3)
(4)
(2)
(3)
(4)
6
6
(5)
(6)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.5 V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
18 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
001aai915
001aai916
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
(1)
10
8
10
8
(1)
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai917
001aai918
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
10
8
10
8
(1)
(1)
(2)
(3)
(4)
(5)
(6)
6
6
(2)
(3)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.8 V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
19 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
001aai919
001aai920
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
(1)
10
8
10
8
(1)
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
4
4
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai921
001aai922
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
10
8
10
8
(1)
6
6
(1)
(2)
(3)
(2)
(3)
(4)
(5)
(6)
4
4
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 13. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 2.5 V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
20 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
001aai923
001aai924
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
10
8
10
8
(1)
(1)
(2)
(3)
(2)
(3)
6
6
4
4
(4)
(5)
(6)
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai925
001aai926
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
10
8
10
8
6
6
(1)
(1)
(2)
(3)
(2)
(3)
(4)
(5)
(6)
4
4
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 14. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 3.3 V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
21 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
001aai927
001aai928
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
10
8
10
8
(1)
(1)
(2)
(3)
(2)
(3)
6
6
4
4
(4)
(5)
(6)
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai929
001aai930
14
PHL
14
t
t
PLH
(ns)
12
(ns)
12
10
8
10
8
6
6
(1)
(1)
(2)
(3)
(2)
(3)
4
4
(4)
(5)
(6)
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 15. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 5 V
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
22 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
14. Application information
14.1 Unidirectional logic level-shifting application
The circuit given in Figure 16 is an example of the 74LVC2T45; 74LVCH2T45 being used
in a unidirectional logic level-shifting application.
V
V
CC2
CC1
V
V
CC(B)
V
V
V
V
CC(A)
1A
CC1
CC1
CC2
CC2
1
2
3
4
8
7
6
5
1B
74LVC2T45
74LVCH2T45
2A
2B
GND
DIR
system-1
system-2
001aai931
Fig 16. Unidirectional logic level-shifting application
Table 16. Description of unidirectional logic level-shifting application
Pin
1
Name
VCC(A)
1A
Function
VCC1
OUT
OUT
GND
DIR
Description
supply voltage of system-1 (1.2 V to 5.5 V)
output level depends on VCC1 voltage
output level depends on VCC1 voltage
device GND
2
3
2A
4
GND
DIR
5
the GND (LOW level) determines B port to A port direction
input threshold value depends on VCC2 voltage
input threshold value depends on VCC2 voltage
supply voltage of system-2 (1.2 V to 5.5 V)
6
2B
IN
7
1B
IN
8
VCC(B)
VCC2
14.2 Bidirectional logic level-shifting application
Figure 17 shows the 74LVC2T45; 74LVCH2T45 being used in a bidirectional logic
level-shifting application. Since the device does not have an output enable pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
23 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
V
CC1
V
CC1
V
V
CC2
CC2
V
V
CC(B)
CC(A)
I/O-1
PULL-UP/DOWN
1
2
3
4
8
7
6
5
PULL-UP/DOWN
I/O-2
1A
1B
74LVC2T45
74LVCH2T45
2A
2B
GND
DIR
DIR CTRL
DIR CTRL
system-1
Pull-up or pull-down only needed for 74LVC2T45.
system-2
001aai932
Fig 17. Bidirectional logic level-shifting application
Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
Table 17. Description of bidirectional logic level-shifting application[1]
State
DIR CTRL
I/O-1
output
Z
I/O-2
input
Z
Description
1
2
H
H
system-1 data to system-2
system-2 is getting ready to send data to system-1. I/O-1 and I/O-2
are disabled. The bus-line state depends on bus hold
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line
state depends on bus hold
input
output
system-2 data to system-1
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
14.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 18. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
0 V
0
Unit
1.8 V
< 1
< 2
< 2
< 2
2
2.5 V
< 1
3.3 V
< 1
5.0 V
< 1
2
0 V
A
A
A
A
A
1.8 V
2.5 V
3.3 V
5.0 V
< 1
< 1
< 1
< 1
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
24 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
14.4 Enable times
Calculate the enable times for the 74LVC2T45; 74LVCH2T45 using the following
formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74LVC2T45;
74LVCH2T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of
the device must be disabled before presenting it with an input. After the B port has been
disabled, an input signal applied to it appears on the corresponding A port after the
specified propagation delay.
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
25 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
15. Package outline
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 18. Package outline SOT765-1 (VSSOP8)
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
26 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 19. Package outline SOT833-1 (XSON8)
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
27 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
D
A
A
1
detail X
(2)
(4×)
e
L
(2)
(8×)
b
4
5
e
1
1
8
terminal 1
index area
L
1
X
0
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.5 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1089_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-09
10-04-12
SOT1089
MO-252
Fig 20. Package outline SOT1089 (XSON8)
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
28 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
v
C
C
A
B
b
e
L
1
y
1
y
w
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
1
L
2
v
w
y
y
1
max
mm nom 0.5
min
0.05 0.35 2.1 3.1
0.00 0.15 1.9 2.9
0.5 0.15 0.6
0.3 0.05 0.4
0.5 1.5
0.1 0.05 0.05 0.1
sot996-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
07-12-21
12-11-20
SOT996-2
Fig 21. Package outline SOT996-2 (XSON8)
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
29 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-2
X
D
B
A
E
terminal 1
index area
A
A
1
detail X
e
C
v
C
C
A
B
b
y
y
w
C
1
4
3
2
5
e
1
6
7
1
terminal 1
index area
8
L
metal area
not for soldering
L
1
0
1
2 mm
scale
Dimensions
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max 0.5 0.05 0.25 1.65 1.65
0.35 0.15
0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.1 0.05 0.05 0.05
0.00 0.15 1.55 1.55 0.25 0.05
mm nom
min
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot902-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
10-11-02
11-03-31
SOT902-2
MO-255
Fig 22. Package outline SOT902-2 (XQFN8)
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
30 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
b
4
(2)
1
2
3
(4×)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.35 0.04 0.20 1.25 1.05
0.35 0.40
0.15 1.20 1.00 0.55 0.3 0.30 0.35
0.12 1.15 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1116_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1116
Fig 23. Package outline SOT1116 (XSON8)
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
31 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
b
4
(2)
(4×)
1
2
3
L
L
1
e
8
7
6
5
e
1
e
1
e
1
(2)
(8×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1203_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1203
Fig 24. Package outline SOT1203 (XSON8)
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
32 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
16. Abbreviations
Table 19. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
17. Revision history
Table 20. Revision history
Document ID
Release date
20130329
Data sheet status
Change notice
Supersedes
74LVC_LVCH2T45 v.8
Modifications:
Product data sheet
-
74LVC_LVCH2T45 v.7
• For type numbers 74LVC2T45GD and 74LVCH2T45GD XSON8U has changed to XSON8.
20120619 Product data sheet 74LVC_LVCH2T45 v.6
74LVC_LVCH2T45 v.7
Modifications:
-
• For type numbers 74LVC2T45GM and 74LVCH2T45GM the SOT code has changed to
SOT902-2.
74LVC_LVCH2T45 v.6
Modifications:
20111209
Product data sheet
-
74LVC_LVCH2T45 v.5
• Legal pages updated.
74LVC_LVCH2T45 v.5
74LVC_LVCH2T45 v.4
74LVC_LVCH2T45 v.3
74LVC_LVCH2T45 v.2
74LVC_LVCH2T45 v.1
20110927
20100820
20100119
20090205
20081118
Product data sheet
-
-
-
-
-
74LVC_LVCH2T45 v.4
74LVC_LVCH2T45 v.3
74LVC_LVCH2T45 v.2
74LVC_LVCH2T45 v.1
-
Product data sheet
Product data sheet
Product data sheet
Product data sheet
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
33 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
18.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
34 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC_LVCH2T45
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 8 — 29 March 2013
35 of 36
74LVC2T45; 74LVCH2T45
NXP Semiconductors
Dual supply translating transceiver; 3-state
20. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical propagation delay characteristics . . 17
8
9
10
11
12
13
14
Application information. . . . . . . . . . . . . . . . . . 23
Unidirectional logic level-shifting application . 23
Bidirectional logic level-shifting application. . . 23
Power-up considerations . . . . . . . . . . . . . . . . 24
Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.1
14.2
14.3
14.4
15
16
17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 33
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 34
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 35
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 March 2013
Document identifier: 74LVC_LVCH2T45
相关型号：
935284847118
CBTLV/3B SERIES, DUAL 24-BIT DRIVER, TRUE OUTPUT, PDSO56, 4.40 MM, PLASTIC, MO-194, SOT481-1, TSSOP-56
NXP
935284877551
32-BIT, FLASH, 60MHz, RISC MICROCONTROLLER, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
NXP
935284881151
32-BIT, FLASH, 60MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
NXP
935284889151
32-BIT, FLASH, 60MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64
NXP
935285102000
32-BIT, FLASH, 72MHz, RISC MICROCONTROLLER, PBGA100, 9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100
NXP
935285102518
32-BIT, FLASH, 72MHz, RISC MICROCONTROLLER, PBGA100, 9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100
NXP
935285102551
32-BIT, FLASH, 72MHz, RISC MICROCONTROLLER, PBGA100, 9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100
NXP
935285103518
32-BIT, FLASH, 72MHz, RISC MICROCONTROLLER, PBGA100, 9 X 9 MM, 0.70 MM HEIGHT, PLASTIC, SOT926-1, TFBGA-100
NXP
©2020 ICPDF网 联系我们和版权申明