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935286602026 [NXP]

LIQUID CRYSTAL DISPLAY DRIVER, UUC222, BUMP, DIE-222;
935286602026
型号： 935286602026
厂家： NXP    NXP
描述：

LIQUID CRYSTAL DISPLAY DRIVER, UUC222, BUMP, DIE-222

驱动 接口集成电路
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PCF8531  
34 x 128 pixel matrix driver  
Rev. 05 — 10 August 2010  
Product data sheet  
1. General description  
The PCF8531 is a low-power CMOS1 LCD row and column driver, designed to drive dot  
matrix graphic displays at multiplex rates of 1:17, 1:26, and 1:34. Furthermore, it can drive  
up to 128 icons. All necessary functions for the display are provided in a single chip,  
including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of  
external components and low power consumption. The PCF8531 is compatible with most  
microcontrollers and communicates via a two-line bidirectional I2C-bus. All inputs are  
CMOS compatible.  
Remark: The icon mode is used to reduce current consumption. When only icons are  
displayed, a much lower operating voltage (VLCD) can be used and the switching  
frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as  
VLCD  
.
2. Features and benefits  
„ Single-chip LCD controller and driver  
„ 34 row and 128 column outputs  
„ Display data RAM 34 × 128 bits  
„ 128 icons (last row is used for icons)  
„ Fast-mode I2C-bus interface (400 kbit/s)  
„ Software selectable multiplex rates: 1:17, 1:26, and 1:34  
„ Icon mode with multiplex rate 1:2:  
‹ Featuring reduced current consumption while displaying icons only  
„ On-chip:  
‹ Generation of VLCD (external supply also possible)  
‹ Selectable linear temperature compensation  
‹ Oscillator requires no external components (external clock also possible)  
‹ Generation of intermediate LCD bias voltages  
‹ Power-On Reset (POR)  
„ No external components required  
„ Software selectable bias configuration  
„ Logic supply voltage range VDD1 to VSS1: 1.8 V to 5.5 V  
„ Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2  
:
2.5 V to 4.5 V  
„ Display supply voltage range VLCD to VSS  
‹ Normal mode: 4 V to 9 V  
:
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
‹ Icon mode: 3 V to 9 V  
„ Low-power consumption, suitable for battery operated systems  
„ CMOS compatible inputs  
„ Manufactured in silicon gate CMOS process  
3. Applications  
„ Telecommunication systems  
„ Automotive information systems  
„ Point-of-sale terminals  
„ Instrumentation  
4. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
PCF8531U  
-
chip with bumps in tray  
-
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
2 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
5. Block diagram  
V
V
V
DD3  
R0 to R33  
34  
C0 to C127  
128  
DD1  
DD2  
V
V
SS1  
SS2  
ROW  
DRIVERS  
COLUMN  
DRIVERS  
POWER-ON RESET  
ENR  
RES  
T1  
T2  
T3  
T4  
INTERNAL  
RESET  
PCF8531  
DATA LATCHES  
OSC  
OSCILLATOR  
BIAS  
VOLTAGE  
GENERATOR  
MATRIX  
LATCHES  
V
LCDIN  
TIMING  
GENERATOR  
DISPLAY DATA RAM  
V
LCDSENSE  
DISPLAY  
ADDRESS  
COUNTER  
V
LCD  
MATRIX DATA  
RAM  
GENERATOR  
V
LCDOUT  
SCL  
SDA  
2
INPUT  
FILTERS  
I C-BUS  
COMMAND  
DECODER  
ADDRESS  
COUNTER  
CONTROL  
SDACK  
mgs465  
SA0  
Fig 1. Block diagram of PCF8531  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
3 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
6. Pinning information  
6.1 Pinning  
R0  
.
.
.
.
.
.
R32  
T2  
C0  
.
.
.
SCL  
T1  
T3  
.
.
.
V
SS1  
SS2  
C31  
C32  
.
.
.
V
T4  
ENR  
SA0  
SDACK  
SDA  
.
.
.
y
0,0  
x
C63  
C64  
.
.
.
V
V
V
DD1  
DD2  
DD3  
.
.
.
RES  
C95  
V
LCDIN  
C96  
.
.
.
V
LCDOUT  
V
LCDSENSE  
OSC  
.
.
.
C127  
R33  
.
.
.
.
.
.
R1  
pad1  
mgs486  
The positioning of the bonding pads is not to scale.  
Fig 2. Bonding pad location for PCF8531  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
4 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 2.  
Pad allocation table  
Symbol  
OSC  
Pad  
Pad  
Symbol  
ENR  
T4  
15  
55  
16  
VLCDSENSE  
VLCDOUT  
VLCDIN  
56  
17 to 23  
24 to 30  
31  
57 to 63  
64 to 70  
71  
VSS2  
VSS1  
T3  
RES  
32 to 34  
35 to 42  
43 to 49  
50 to 51  
VDD3  
72  
T1  
VDD2  
73 to 74  
78  
SCL  
T2  
VDD1  
SDA  
87 to 103  
R0, R2, R4, R6, R8,  
R10, R12, R14, R16,  
R18, R20, R22, R24,  
R26, R28, R30, R32  
52  
54  
SDACK  
SA0  
104 to 231  
232 to 248  
C0 to C127  
R33, R31, R29, R27,  
R25, R23, R21, R19,  
R17, R15, R13, R11,  
R9, R7, R5, R3, R1  
100 μm  
80 μm  
100  
μm  
100  
μm  
100  
μm  
y
y
y
center  
center  
center  
x center  
circle  
x center  
C
x center  
F
mgs490  
Fig 3. Alignment markers  
Table 3. Alignment markers for PCF8531  
Alignment marks  
x (μm)  
y (μm)  
823.1  
950.0  
401.9  
798.4  
798.4  
C1  
−5402.0  
5292.4  
5890.3  
−5543.0  
5637.4  
C2  
F
circle 1  
circle 2  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
5 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
L
W
PCF8531  
pitch  
Y
X
001aag908  
Fig 4. Chip dimensions  
Table 4.  
Pad  
Bonding pad dimensions  
Size  
Unit  
pad pitch (minimum)  
bump dimensions  
70  
μm  
50 × 90 × 17.5 (±3)  
381  
μm  
μm  
mm  
wafer thickness (excluding bumps)  
die size L × W  
12.14 × 1.86  
6.2 Pin description  
Table 5.  
Bonding pad description  
All x/y coordinates represent the position of the center of each pad with respect to the center  
(x/y = 0) of the chip (see Figure 2).  
Symbol  
Pad  
1
X (μm)  
5973.6  
5969.5  
5899.5  
5829.5  
5479.5  
5409.5  
5059.5  
4989.5  
4639.5  
4569.5  
4219.5  
4149.5  
3799.5  
3729.5  
3449.5  
3169.5  
Y (μm)  
−821.7  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
Description  
-
dummy  
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-
10  
11  
12  
13  
14  
15  
16  
-
-
-
-
[1]  
[2]  
OSC  
oscillator input  
VLCDSENSE  
voltage multiplier regulation input (VLCD)  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
6 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 5.  
Bonding pad description …continued  
All x/y coordinates represent the position of the center of each pad with respect to the center  
(x/y = 0) of the chip (see Figure 2).  
Symbol  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VLCDIN  
VLCDIN  
VLCDIN  
VLCDIN  
VLCDIN  
VLCDIN  
VLCDIN  
RES  
Pad  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
X (μm)  
3099.5  
3029.5  
2959.5  
2889.5  
2819.5  
2749.5  
2679.5  
2539.5  
2469.5  
2399.5  
2329.5  
2259.5  
2189.5  
2119.5  
1979.5  
1699.5  
1629.5  
1559.5  
1279.5  
1209.5  
1139.5  
1069.5  
999.5  
Y (μm)  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
Description  
[3]  
voltage multiplier output (VLCD  
)
[2]  
LCD supply voltage (VLCD  
)
[4]  
[5]  
external reset input (active LOW)  
supply voltage 3  
VDD3  
VDD3  
VDD3  
[5]  
VDD2  
supply voltage 2  
VDD2  
VDD2  
VDD2  
VDD2  
VDD2  
929.5  
VDD2  
859.5  
VDD2  
789.5  
[5]  
VDD1  
649.5  
supply voltage 1  
VDD1  
579.5  
VDD1  
509.5  
VDD1  
439.5  
VDD1  
369.5  
VDD1  
299.5  
VDD1  
229.5  
SDA  
19.5  
serial data line input of the I2C-bus  
SDA  
−50.5  
[6]  
[7]  
SDACK  
-
−400.5  
−750.5  
−820.5  
−1100.5  
serial data acknowledge output  
dummy  
I2C-bus slave address input; bit 0  
SA0  
ENR  
enable internal Power-On Reset (POR)  
input  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
7 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 5.  
Bonding pad description …continued  
All x/y coordinates represent the position of the center of each pad with respect to the center  
(x/y = 0) of the chip (see Figure 2).  
Symbol  
T4  
Pad  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
X (μm)  
Y (μm)  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
823.4  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
Description  
test input 4  
ground 2  
[8]  
[9]  
−1380.5  
−1660.5  
−1730.5  
−1800.5  
−1870.5  
−1940.5  
−2010.5  
−2080.5  
−2220.5  
−2290.5  
−2360.5  
−2430.5  
−2500.5  
−2570.5  
−2640.5  
−2780.5  
−3060.5  
−3410.5  
−3480.5  
−3830.5  
−4180.5  
−4530.5  
−4600.5  
−4880.5  
−4950.5  
−5230.5  
−5300.5  
−5650.5  
−5720.5  
−5930.5  
−5926.4  
−5786.4  
−5716.4  
−5646.4  
−5576.4  
−5506.4  
−5436.4  
VSS2  
VSS2  
VSS2  
VSS2  
VSS2  
VSS2  
VSS2  
VSS1  
VSS1  
VSS1  
VSS1  
VSS1  
VSS1  
VSS1  
T3  
[9]  
ground 1  
[8]  
[8]  
test 3  
T1  
test 1  
SCL  
SCL  
-
serial clock line input of the I2C-bus  
dummy  
-
-
[10]  
T2  
test 2 output  
dummy  
-
-
-
-
-
-
-
-
R0  
R2  
R4  
R6  
R8  
R10  
LCD row driver output  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
8 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 5.  
Bonding pad description …continued  
All x/y coordinates represent the position of the center of each pad with respect to the center  
(x/y = 0) of the chip (see Figure 2).  
Symbol  
R12  
R14  
R16  
R18  
R20  
R22  
R24  
R26  
R28  
R30  
R32  
C0  
Pad  
93  
X (μm)  
Y (μm)  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
Description  
−5366.4  
−5296.4  
−5226.4  
−5156.4  
−5086.4  
−5016.4  
−4946.4  
−4876.4  
−4806.4  
−4736.4  
−4666.4  
−4526.4  
−4456.4  
−4386.4  
−4316.4  
−4246.4  
−4176.4  
−4106.4  
−4036.4  
−3966.4  
−3896.4  
−3826.4  
−3756.4  
−3688.4  
−3616.4  
−3546.4  
−3476.4  
−3406.4  
−3336.4  
−3266.4  
−3196.4  
−3126.4  
−3056.4  
−2986.4  
−2916.4  
−2846.4  
−2776.4  
−2706.4  
−2636.4  
LCD row driver output  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
LCD column driver output  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
C21  
C22  
C23  
C24  
C25  
C26  
C27  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
9 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 5.  
Bonding pad description …continued  
All x/y coordinates represent the position of the center of each pad with respect to the center  
(x/y = 0) of the chip (see Figure 2).  
Symbol  
C28  
C29  
C30  
C31  
C32  
C33  
C34  
C35  
C36  
C37  
C38  
C39  
C40  
C41  
C42  
C43  
C44  
C45  
C46  
C47  
C48  
C49  
C50  
C51  
C52  
C53  
C54  
C55  
C56  
C57  
C58  
C59  
C60  
C61  
C62  
C63  
C64  
C65  
C66  
Pad  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
X (μm)  
−2566.4  
−2496.4  
−2426.4  
−2356.4  
−2216.4  
−2146.4  
−2076.4  
−2006.4  
−1936.4  
−1866.4  
−1796.4  
−1726.4  
−1656.4  
−1586.4  
−1516.4  
−1446.4  
−1376.4  
−1306.4  
−1236.4  
−1166.4  
−1096.4  
−1026.4  
−956.4  
−886.4  
−816.4  
−746.4  
−676.4  
−606.4  
−534.6  
−466.4  
−396.4  
−326.4  
−256.4  
−186.4  
−116.6  
Y (μm)  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
Description  
LCD column driver output  
−46.4  
93.6  
163.6  
233.6  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
10 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 5.  
Bonding pad description …continued  
All x/y coordinates represent the position of the center of each pad with respect to the center  
(x/y = 0) of the chip (see Figure 2).  
Symbol  
C67  
C68  
C69  
C70  
C71  
C72  
C73  
C74  
C75  
C76  
C77  
C78  
C79  
C80  
C81  
C82  
C83  
C84  
C85  
C86  
C87  
C88  
C89  
C90  
C91  
C92  
C93  
C94  
C95  
C96  
C97  
C98  
C99  
C100  
C101  
C102  
C103  
C104  
C105  
Pad  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
209  
X (μm)  
303.6  
Y (μm)  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
Description  
LCD column driver output  
373.3  
443.6  
513.6  
583.6  
653.6  
723.6  
793.6  
863.6  
933.6  
1003.6  
1073.6  
1143.6  
1213.6  
1283.6  
1353.6  
1423.6  
1493.6  
1563.6  
1633.6  
1703.6  
1773.6  
1843.6  
1913.6  
1983.6  
2053.6  
2123.6  
2193.6  
2263.6  
2403.6  
2473.6  
2543.6  
2613.6  
2683.6  
2753.6  
2823.6  
2893.6  
2963.6  
3033.6  
PCF8531  
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Product data sheet  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 5.  
Bonding pad description …continued  
All x/y coordinates represent the position of the center of each pad with respect to the center  
(x/y = 0) of the chip (see Figure 2).  
Symbol  
C106  
C107  
C108  
C109  
C110  
C111  
C112  
C113  
C114  
C115  
C116  
C117  
C118  
C119  
C120  
C121  
C122  
C123  
C124  
C125  
C126  
C127  
R33  
Pad  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
241  
242  
243  
244  
245  
246  
247  
248  
X (μm)  
3103.6  
3173.6  
3243.6  
3313.6  
3383.6  
3453.6  
3523.6  
3593.6  
3663.6  
3733.6  
3803.6  
3873.6  
3943.6  
4013.6  
4083.6  
4153.6  
4223.6  
4293.6  
4363.6  
4433.6  
4503.6  
4573.6  
4713.6  
4783.6  
4853.6  
4923.6  
4993.6  
5063.6  
5113.6  
5203.6  
5343.6  
5413.6  
5483.6  
5553.6  
5623.6  
5693.6  
5763.6  
5833.6  
5903.6  
Y (μm)  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
−821.7  
Description  
LCD column driver output  
LCD row driver output; icon row  
LCD row driver output  
R31  
R29  
R27  
R25  
R23  
R21  
R19  
R17  
R15  
R13  
R11  
R9  
R7  
R5  
R3  
R1  
PCF8531  
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Product data sheet  
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PCF8531  
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34 x 128 pixel matrix driver  
[1] If the on-chip oscillator is used, this input must be connected to VDD1  
.
[2] If the internal VLCD generation is used, VLCDOUT, VLCDIN, and VLCDSENSE must be connected together.  
[3] If an external VLCD is used in the application, then pin VLCDOUT must be left open-circuit, otherwise the chip  
will be damaged.  
[4] If only the internal Power-On Reset (POR) is used, this input must be connected to VDD1  
[5] VDD1 is for the logic supply, VDD2 and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and  
DD3 must be connected together. If only one supply voltage is available, VDD1, VDD2, and VDD3 must be  
.
V
connected together.  
[6] Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes  
fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is  
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from  
the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus  
pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be  
able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK  
output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where  
the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to  
the system SDA line to guarantee a valid LOW level.  
[7] If ENR is connected to VSS, Power-On Reset (POR) is disabled; to enable Power-On Reset (POR) ENR  
must be connected to VDD1  
.
[8] In the application, this input must be connected to VSS  
[9] VSS1 and VSS2 must be connected together.  
[10] In the application, T2 must be left open-circuit.  
.
PCF8531  
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PCF8531  
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34 x 128 pixel matrix driver  
7. Functional description  
7.1 Oscillator  
The on-chip oscillator provides the clock signal for the display system. No external  
components are required and the OSC input must be connected to VDD. An external clock  
signal, if used, is connected to this input.  
7.2 Power-On Reset (POR)  
The on-chip Power-On Reset (POR) initializes the chip after power-on or power failure.  
7.3 I2C-bus controller  
The I2C-bus controller receives and executes the commands. The PCF8531 acts as an  
I2C-bus slave receiver and therefore it cannot control bus communication.  
7.4 Input filters  
To enhance noise immunity in electrically adverse environments, RC low-pass filters are  
provided on the SDA and SCL lines.  
7.5 Display data RAM  
The PCF8531 contains 34 × 128 bits static RAM for storing the display data, see Figure 7.  
The RAM is divided into 6 banks of 128 bytes (6 × 8 × 128 bits). Bank 5 is used for icon  
data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There  
is a direct correspondence between the X address and column output number.  
7.6 Timing generator  
The timing generator produces the various signals required to drive the internal circuitry.  
Internal chip operation is not affected by operations on the data buses.  
7.7 Address counter  
The address counter sets the addresses of the display data RAM for writing.  
7.8 Display address counter  
The display address counter generates the addresses for read out of the display data.  
7.9 Command decoder  
The command decoder identifies command words that arrive on the I2C-bus and  
determines the destination for the following data bytes.  
PCF8531  
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PCF8531  
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34 x 128 pixel matrix driver  
7.10 Bias voltage generator  
The bias voltage generator generates four buffered intermediate bias voltages. This block  
contains the generator for the reference voltages and the four buffers. This block can  
operate in two voltage ranges:  
• Normal mode: 4.0 V to 9.0 V  
• Power save mode: 3.0 V to 9.0 V.  
7.11 VLCD generator  
The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is  
programmed by software.  
7.12 Reset  
The PCF8531 has the possibility of two reset modes: internal Power-On Reset (POR) or  
external reset (RES). The reset mode is selected using the ENR signal. After a reset, the  
chip has the following state:  
• All row and column outputs are set to VSS (display off)  
• RAM data is undefined  
• Power-down mode  
7.13 Power-down  
During power-down, all static currents are switched off (no internal oscillator, no timing  
and no LCD segment drive system) and all LCD outputs are internally connected to VSS  
The I2C-bus function remains operational.  
.
7.14 Column driver outputs  
The LCD drive section includes 128 column outputs (C0 to C127) which must be  
connected directly to the LCD. The column output signals are generated in accordance  
with the multiplexed row signals and with the data in the display latch. When less than  
128 columns are required, the unused column outputs must be left open-circuit.  
7.15 Row driver outputs  
The LCD drive section includes 34 row outputs (R0 to R33), which must be connected  
directly to the LCD. The row output signals are generated in accordance with the selected  
LCD drive mode. If less than 34 rows or lower multiplex rates are required, the unused  
outputs must be left open-circuit. The row signals are interlaced i.e. the selection order is  
R0, R2, ..., R1, R3, etc.  
PCF8531  
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PCF8531  
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34 x 128 pixel matrix driver  
8. LCD waveforms and DDRAM to data mapping  
The LCD waveforms and the DDRAM to display data mapping are shown in Figure 5,  
Figure 6 and Figure 7.  
frame n  
frame n + 1  
V
V
V
V
V
(t)  
(t)  
LCD  
2
3
state1  
state2  
ROW 0  
R0(t)  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
ROW 1  
R1(t)  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
COL 0  
C0(t)  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
COL 1  
C1(t)  
V
V
V
4
5
SS  
V
V
LCD  
− V  
3
SS  
V
V
− V  
V
− V  
LCD  
0 V  
2
4
5
V
(t)  
0 V  
state1  
− V  
V
SS  
− V  
3
2
5
V
4
− V  
LCD  
−V  
LCD  
V
V
LCD  
− V  
3
SS  
V
V
− V  
V
4
− V  
LCD  
0 V  
2
5
V
(t)  
0 V  
V
state2  
− V  
− V  
3
2
SS  
5
V
4
− V  
LCD  
−V  
LCD  
0 2 4 6 8...  
... 32 1 3 5 7...  
... 33 0 2 4 6 8...  
... 32 1 3 5 7...  
... 33  
mgs466  
(1) Vstate1(t) = C1(t) − R0(t)  
(2) Vstate2(t) = C1(t) − R1(t)  
Fig 5. Typical LCD driver waveforms  
PCF8531  
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34 x 128 pixel matrix driver  
frame n  
frame n + 1  
only icons are driven  
V
V
V
LCD  
2
3
ROW 0 to 32  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
ROW 33  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
COL 1 on/off  
COL 2 off/on  
COL 3 on/on  
COL 4 off/off  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
V
V
V
4
5
SS  
mgs467  
Fig 6. LCD waveforms, icon mode, multiplex rate 1:2  
PCF8531  
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34 x 128 pixel matrix driver  
DDRAM  
bank 0  
top of LCD  
R0  
bank 1  
bank 2  
bank 3  
bank 4  
bank 5  
R8  
R16  
LCD  
R24  
R32  
R33 (icon row)  
mgs468  
Fig 7. DDRAM to display data mapping  
8.1 Addressing  
Data is written in bytes into the RAM matrix of the PCF8531 as shown in Figure 8,  
Figure 9 and Figure 10. The display RAM has a matrix of 34 × 128 bits. The columns are  
addressed by the address pointer. The address ranges are X 0 to X 127 (7Fh) and Y 0 to  
Y 5 (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode  
(V = 1), the Y address increments after each byte (see Figure 9). After the last Y address  
(Y = 4), Y wraps around to 0 and X increments to address the next column. In horizontal  
addressing mode (V = 0), the X address increments after each byte (see Figure 10). After  
the last X address (X = 127), X wraps around to 0 and Y increments to address the next  
PCF8531  
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PCF8531  
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34 x 128 pixel matrix driver  
row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to  
address (X = 0 and Y = 0). The Y address 5 is reserved for icon data and is not affected  
by the addressing mode. Please note that in bank 4 only the LSB (DB0) of the data is  
written into the RAM and in bank 5 only the 5th data bit (DB4) is written into the RAM.  
LSB  
0
1
MSB  
LSB  
2
Y address  
3
MSB  
LSB  
4
icon data  
5
mgs469  
0
X address  
127  
MSB  
Fig 8. RAM format and addressing  
0
1
2
3
4
0
5
6
0
1
2
3
4
5
Y address  
638  
639  
1
icon data  
0
X address  
127  
mgs470  
Fig 9. Sequence of writing data bytes into RAM with vertical addressing (V = 1)  
127  
255  
383  
511  
639  
0
1
2
0
1
2
3
4
5
128  
256  
384  
512  
0
129  
257  
385  
513  
1
130  
258  
386  
514  
Y address  
icon data  
0
X address  
127  
mgs471  
Fig 10. Sequence of writing data bytes into RAM with horizontal addressing (V = 0)  
PCF8531  
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PCF8531  
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34 x 128 pixel matrix driver  
9. Instructions  
Only two PCF8531 registers, the instruction register and the data register can be directly  
controlled by the MPU. Before internal operation, control information is stored temporarily  
in these registers to allow interfacing to various types of MPUs which operate at different  
speeds or to allow interfacing to peripheral control ICs. The PCF8531 operation is  
controlled by the instructions given in Table 11.  
Instructions are of four types:  
• Those that define PCF8531 functions e.g. display configuration, etc.  
• Those that set internal RAM addresses  
• Those that perform data transfer to/from the internal RAM  
• Others  
In normal mode instructions which perform data transfer to/from the internal RAM are  
used most frequently. Automatic incrementing by 1 of internal RAM addresses after each  
data write reduces the MPU program load.  
9.1 Reset  
After reset or internal Power-On Reset (POR) (depending on the application), the LCD  
driver is set to the following state:  
• Power-down mode (PD = 1)  
• Horizontal addressing (V = 0)  
• Display blank (D = 0; E = 0), no icon mode (IM = 0)  
• Address counter X[6:0] = 0; Y[2:0] = 0  
• Bias system BS[2:0] = 0  
• Multiplex rate M[1:0] = 0 (multiplex rate 1:17)  
• Temperature control mode TC[2:0] = 0  
• HV-gen control, HVE = 0 the high voltage (HV) generator is switched off, PRS = 0 and  
S[1:0] = 0  
• VLCD = 0 V  
• RAM data is undefined  
• Command page definition H[1:0] = 0  
PCF8531  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
9.2 Function set  
9.2.1 PD  
When PD = 1, the power-down mode of the LCD driver is active:  
• All LCD outputs at VSS (display off)  
• Power-On Reset (POR) detection active, oscillator off  
• VLCD can be disconnected  
• I2C-bus is operational, commands can be executed  
• RAM contents not cleared; RAM data can be written  
• Register settings remain unchanged  
9.2.2 V  
When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as  
shown in Figure 10. When V = 1 the vertical addressing is selected. The data is written  
into the DDRAM as shown in Figure 9. Icon data is written independently of V when  
Y address is 5.  
9.3 Set Y address  
Bits Y2, Y1 and Y0 define the Y address vector of the display RAM (see Table 6).  
Table 6.  
Y address  
Y2  
0
Y1  
0
Y0  
0
Bank  
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5 (icons)  
9.4 Set X address  
The X address points to the columns. The range of X is 0 to 127 (7Fh).  
9.5 Set multiplex rate  
M[1:0] selects the multiplex rate (see Table 7).  
Table 7.  
Multiplex rates  
Multiplex rate  
1:17  
M1  
0
M0  
0
1:26  
1
0
1:34  
0
1
9.6 Display control (D, E, and IM)  
Bits D and E select the display mode (see Table 13). Bit IM (see Table 12) sets the display  
to icon mode.  
PCF8531  
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PCF8531  
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34 x 128 pixel matrix driver  
9.7 Set bias system  
The bias voltage levels are set in the ratio of R − R − n × R − R − R (see Figure 11).  
V
1
= V  
LCD  
R
V
V
2
R
3
n × R  
V
V
4
R
R
5
V
= V  
SS  
6
013aaa183  
Fig 11. Voltage divider chain  
Different multiplex rates require different bias settings. Bias settings are programmed by  
BS[2:0], which sets the binary number n. The optimum value for n is given by:  
n = muxrate – 3  
Supported values of n are given in Table 8. Table 9 shows the intermediate bias voltages.  
Table 8.  
BS[2:0]  
000  
Programming the required bias system  
n
7
6
5
4
3
2
1
0
Bias system  
Comment  
1
⁄
-
11  
1
001  
⁄
-
10  
1
010  
⁄
9
-
1
⁄
011  
-
8
1
100  
⁄
7
recommended for 1:34  
recommended for 1:26  
recommended for 1:17  
recommended for icon mode  
1
⁄
101  
6
1
110  
⁄
5
1
⁄
111  
4
PCF8531  
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PCF8531  
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34 x 128 pixel matrix driver  
9.8 LCD bias voltage  
Table 9.  
Symbol  
V1  
Intermediate LCD bias voltages  
Bias voltage  
VLCD  
Example for 1⁄7 bias  
VLCD  
V2  
6⁄7 × VLCD  
n + 3  
n + 4  
-----------  
× VLCD  
× VLCD  
× VLCD  
× VLCD  
V3  
5⁄7 × VLCD  
2⁄7 × VLCD  
1⁄7 × VLCD  
VSS  
n + 2  
-----------  
n + 4  
V4  
2
-----------  
n + 4  
V5  
1
-----------  
n + 4  
V6  
VSS  
9.9 Set VLCD value  
VLCD can be set by software. The voltage at intersection temperature [VLCD (T = Tints)] can  
be calculated as: VLCD (Tints) = a + VLCD × b  
The generated voltage is dependent on the temperature, programmed Temperature  
Coefficient (TC) and the programmed voltage at intersection temperature (Tints).  
V
LCD = VLCD (Tints) × [1 + TC × (T − Tints)]  
The parameter values are given in Table 10. Two overlapping VLCD ranges can be  
selected via the command HV-gen control (see Table 10 and Figure 12). The maximum  
voltage which can be generated depends on the VDD2 and VDD3 voltages and the display  
load current. For multiplex rate 1:34, the optimum VLCD can be calculated as:  
1 + 34  
-------------------------------------  
VLCD  
=
× Vth = 5.30 × Vth  
1
⎛
⎞
2 × 1 – ---------  
⎝
⎠
34  
Where Vth is the threshold voltage of the liquid crystal material used.  
The practical value for VLCD is determined by equating Voff(RMS) with a defined LCD  
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast.  
As the programming range for the internally generated VLCD allows values above the  
maximum allowed VLCD, the user must ensure, while setting the VOP register and  
selecting the temperature compensation, that the VLCD limit maximum of 9.0 V is never  
exceeded under all conditions and including all tolerances.  
PCF8531  
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34 x 128 pixel matrix driver  
Table 10. Parameter values for the HV generator programming  
Symbol  
Value  
PRS = 0  
27  
Unit  
PRS = 1  
27  
Tints  
°C  
V
a
2.94  
6.75  
b
0.03  
0.03  
V
programming range  
2.94 to 6.75  
6.75 to 10.56  
V
V
LCD  
b
a
00 01 02 03 04 05 06 . . . 7D 7E 7F 00 01 02 03 04 05 06 . . . 5F 6F 7F  
LOW HIGH  
mgl935  
VOP[6:0] (programmed) [00h to 7Fh] program range LOW to HIGH  
Fig 12. VLCD programming of PCF8531  
9.10 Voltage multiplier control S[1:0]  
The PCF8531 incorporates a software configurable voltage multiplier. After reset (internal  
or external), the voltage multiplier is set to 2 × VDD2. The voltage multiplier factors are set  
by setting bits S[1:0] (see Table 13).  
9.11 Temperature compensation  
Due to the temperature dependency of the viscosity of the liquid crystals, the LCD  
controlling voltage VLCD should usually be increased at lower temperatures to maintain  
optimum contrast. Figure 13 shows VLCD for high multiplex rates.  
PCF8531  
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34 x 128 pixel matrix driver  
mgs473  
V
LCD  
0 °C  
T
Fig 13. VLCD as a function of liquid crystal temperature  
Linear temperature compensation is supported in the PCF8531. The temperature  
coefficient of VLCD can be selected from eight values by setting bits TC[2:0] (see  
Table 13).  
Table 11. Instruction set  
Instruction  
I2C-bus  
command[1]  
I2C-bus command byte  
Description  
RS  
R/W  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
DB0  
H1 and H0 = don’t care (H independent command page)  
NOP  
0
1
0
0
0
0
0
0
0
0
0
0
no operation  
write data  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
write data to  
display RAM  
set default H[1:0]  
0
0
0
0
0
0
0
0
0
1
select H[1:0] = 0  
H1 = 0 and H0 = 0 (function and RAM command page)  
instruction set  
0
0
0
0
0
0
0
1
0
0
H1  
V
H0  
0
select command  
page  
function set  
0
0
0
0
1
PD  
power-down  
control; entry  
mode  
set Y address of  
RAM  
0
0
0
0
0
1
1
0
0
0
Y2  
X2  
Y1  
X1  
Y0  
X0  
Set Y address of  
RAM; 0 ≤ Y ≤ 5  
set X address of  
RAM  
X6  
X5  
X4  
X3  
Set X address of  
RAM; 0 ≤ X ≤ 127  
H1 = 0 and H0 = 1 (display setting command page)  
multiplex rate  
display control  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
M1  
IM  
M0  
E
set multiplex rate  
D
set display  
configuration  
bias system  
0
0
0
0
0
1
0
BS2  
BS1  
BS0  
set bias system  
(BSx)  
H1 = 1 and H0 = 0 (HV-gen command page)  
HV-gen control  
0
0
0
0
0
0
0
0
0
0
1
1
0
PRS  
S1  
HVE  
S0  
set VLCD  
programming  
range  
HV-gen  
configuration  
0
0
0
set voltage  
multiplication  
factor  
PCF8531  
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Table 11. Instruction set …continued  
Instruction  
I2C-bus  
I2C-bus command byte  
Description  
DB0  
command[1]  
RS  
R/W  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
temperature control  
test modes  
0
0
0
0
1
0
0
TC2  
TC1  
TC0  
set temperature  
coefficient  
0
0
0
0
0
1
1
X
X
X
X
X
X
do not use  
(reserved for test)  
VLCD control  
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register  
[1] R/W is set to the slave address byte; Co and RS are set in the control byte.  
Table 12. Explanation for symbols in Table 11  
Bit  
0
1
PD  
chip is active  
chip is in power-down mode  
vertical addressing  
V
horizontal addressing  
normal mode; full display + icons  
see Table 13  
IM  
icon mode; only icons are displayed  
[1]  
H[1:0]  
D and E  
HVE  
PRS  
TC[2:0]  
S[1:0]  
see Table 13  
voltage multiplier disabled  
VLCD programming range LOW  
see Table 13  
voltage multiplier enabled  
VLCD programming range HIGH  
see Table 13  
[1] The bits H[1:0] identify the command page (use set default H[1:0] command to set H[1:0] = 0).  
Table 13. Description of bits H, D and E, TC and S  
Bits  
Value  
Description  
Command page (H)  
H[1:0]  
00  
01  
10  
function and RAM command page  
display setting command page  
HV-gen command page  
Display modes (D, E)  
D and E  
00  
10  
01  
11  
display blank  
normal mode  
all display segments  
inverse video mode  
Temperature coefficient (TC)  
PCF8531  
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34 x 128 pixel matrix driver  
Table 13. Description of bits H, D and E, TC and S …continued  
Bits  
Value  
000  
001  
010  
011  
100  
101  
110  
111  
Description  
TC[2:0]  
temperature coefficient TC0  
temperature coefficient TC1  
temperature coefficient TC2  
temperature coefficient TC3  
temperature coefficient TC4  
temperature coefficient TC5  
temperature coefficient TC6  
temperature coefficient TC7  
Voltage multiplier factor (S)  
S[1:0]  
00  
01  
10  
11  
2 × voltage multiplier  
3 × voltage multiplier  
4 × voltage multiplier  
5 × voltage multiplier  
PCF8531  
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10. I2C-bus interface  
10.1 Characteristics of the I2C-bus  
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.  
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must  
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only  
when the bus is not busy.  
10.1.1 Bit transfer  
One data bit is transferred during each clock pulse. The data on the SDA line must remain  
stable during the HIGH period of the clock pulse as changes in the data line at this time  
will be interpreted as a control signal (see Figure 14).  
SDA  
SCL  
data line  
stable;  
data valid  
change  
of data  
allowed  
mbc621  
Fig 14. Bit transfer  
10.1.2 START and STOP conditions  
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW  
transition of the data line, while the clock is HIGH is defined as the START condition (S).  
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP  
condition (P). The START and STOP conditions are shown in Figure 15.  
SDA  
SCL  
SDA  
SCL  
S
P
START condition  
STOP condition  
mbc622  
Fig 15. Definition of START and STOP conditions  
10.1.3 System configuration  
The system configuration is shown in Figure 16.  
• Transmitter: the device that sends the data to the bus  
• Receiver: the device that receives the data from the bus  
• Master: the device that initiates a transfer, generates clock signals and terminates a  
transfer  
• Slave: the device addressed by a master  
PCF8531  
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• Multi-master: more than one master can attempt to control the bus at the same time  
without corrupting the message  
• Arbitration: procedure to ensure that, if more than one master simultaneously tries to  
control the bus, only one is allowed to do so and the message is not corrupted  
• Synchronization: procedure to synchronize the clock signals of two or more devices.  
MASTER  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER/  
RECEIVER  
SLAVE  
TRANSMITTER/  
RECEIVER  
SLAVE  
RECEIVER  
MASTER  
TRANSMITTER  
SDA  
SCL  
mga807  
Fig 16. System configuration  
10.1.4 Acknowledge  
The number of data bytes transferred between the START and STOP conditions from  
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge  
cycle.  
• A slave receiver which is addressed must generate an acknowledge after the  
reception of each byte.  
• Also a master receiver must generate an acknowledge after the reception of each  
byte that has been clocked out of the slave transmitter.  
• The device that acknowledges must pull-down the SDA line during the acknowledge  
clock pulse, so that the SDA line is stable LOW during the HIGH period of the  
acknowledge related clock pulse (set-up and hold times must be taken into  
consideration).  
• A master receiver must signal an end of data to the transmitter by not generating an  
acknowledge on the last byte that has been clocked out of the slave. In this event the  
transmitter must leave the data line HIGH to enable the master to generate a STOP  
condition.  
Acknowledgement on the I2C-bus is shown in Figure 17.  
PCF8531  
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34 x 128 pixel matrix driver  
data output  
by transmitter  
not acknowledge  
acknowledge  
data output  
by receiver  
SCL from  
master  
1
2
8
9
S
clock pulse for  
acknowledgement  
START  
condition  
mbc602  
Fig 17. Acknowledge on the I2C-bus  
10.2 I2C-bus protocol  
This driver does not support read. The PCF8531 is a slave receiver. Therefore, it only  
responds when R/W = 0 in the slave address byte.  
Before any data is transmitted on the I2C-bus, the device that must respond is addressed  
first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8531.  
The least significant bit of the slave address is set by connecting the input SA0 to either  
logic 0 (VSS) or logic 1 (VDD).  
The I2C-bus protocol is shown in Figure 18.  
The sequence is initiated with a START condition (S) from the I2C-bus master, and is  
followed by the slave address. All slaves with the corresponding address acknowledge in  
parallel, all others ignore the I2C-bus transfer. After acknowledgement, one or more  
command words follow, which define the status of the addressed slaves. A command  
word consists of a control byte, which defines Co and RS, plus a data byte (see Figure 19  
and Table 11).  
The last control byte is tagged with a cleared most significant bit, the continuation bit Co.  
The control and data bytes are also acknowledged by all addressed slaves on the bus.  
After the last control byte, depending on the RS bit setting, either a series of display data  
bytes or command data bytes may follow. If the RS bit was set logic 1, these display bytes  
are stored in the display RAM at the address specified by the data pointer.  
The data pointer is automatically updated and the data is directed to the intended  
PCF8531 device. If the RS bit of the last control byte was set logic 0, these command  
bytes will be decoded and the setting of the device will be changed according to the  
received commands. The acknowledgement after each byte is made only by the  
addressed PCF8531. At the end of the transmission, the I2C-bus master issues a STOP  
condition (P).  
PCF8531  
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34 x 128 pixel matrix driver  
slave address  
control byte  
R/W  
S
0
1
1
1
1
0
SA0  
A
Co RS  
X
X
X
X
X
X
mgs474  
Fig 18. Slave address and control byte  
acknowledge  
acknowledge  
acknowledge  
acknowledge  
acknowledge  
from PCF8531  
from PCF8531  
from PCF8531  
from PCF8531  
from PCF8531  
S
A
0
control byte  
control byte  
S
0
1
1
1
1
0
0
A
1
A
data byte  
A
0
A
data byte  
A P  
RS  
RS  
slave address  
2n ≥ 0 bytes  
1 byte  
n ≥ 0 bytes  
MSB . . . . . . . . . . . LSB  
Co  
Co  
R/W  
mgs475  
Fig 19. Master transmits to slave receiver; write mode  
10.3 Command decoder  
The command decoder identifies command words that arrive on the I2C-bus. The most  
significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates  
that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it  
indicates that a series of data bytes (either command or RAM data) may follow. The DB6  
bit of a control byte is the RAM data/command bit RS. When this bit is logic 1, it indicates  
that another RAM data byte will be transferred next. If the bit is logic 0, it indicates that  
another command byte will be transferred next.  
• Pairs of bytes; information in the second byte, the first byte determines whether  
information is display or instruction data  
• Stream of information bytes after Co = 0; display or instruction data, depending on last  
RS.  
PCF8531  
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34 x 128 pixel matrix driver  
11. Internal circuitry  
PADS 43 to 49  
PADS 32 to 34  
PADS 35 to 42  
V
V
V
DD1  
DD2  
DD3  
V
V
V
SS1  
SS1  
SS1  
PADS 64 to 70  
V
SS2  
PADS 57 to 63  
PADS 57 to 63  
PADS 16, 24 to 30  
PADS 17 to 23  
V
V
(SUPPLY),  
V
V
LCDIN  
SS2  
LCDOUT  
LCDSENSE  
V
V
V
V
SS1  
SS1  
SS1  
V
LCDIN  
DD1  
PADS 73, 74, 50, 51, 52  
SCL, SDA, SDACK  
PADS 87 to 248  
V
V
SS1  
SS1  
V
V
DD1  
DD1  
PADS 15, 54, 71, 72, 56, 31, 55  
OSC, SA0, T3, T1, T4, RES, ENR  
PAD 78  
T2  
V
V
SS1  
SS1  
mgs485  
For all diagrams the maximum forward current is 5 mA and the maximum reverse voltage is 5 V.  
Fig 20. Device protection diagrams  
PCF8531  
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34 x 128 pixel matrix driver  
12. Limiting values  
Table 14. Limiting values [1]  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min Max  
−0.5 +5.5  
−0.5 +4.5  
−0.5 +4.5  
−0.5 +9.0  
−0.5 VDD + 0.5  
−0.5 VDD + 0.5  
−50 +50  
Unit  
V
VDD1  
VDD2  
VDD3  
VLCD  
VI  
supply voltage 1  
logic supply  
supply voltage 2  
multiplier supply  
multiplier supply  
V
supply voltage 3  
V
LCD supply voltage  
input voltage  
V
V
VO  
output voltage  
V
IDD(LCD)  
ISS  
LCD supply current  
ground supply current  
input current  
mA  
mA  
mA  
mA  
mW  
mW  
V
−50 +50  
II  
−10 +10  
IO  
output current  
−10 +10  
Ptot  
total power dissipation  
power dissipation per output  
electrostatic discharge voltage  
-
-
-
-
-
-
300  
P/out  
VESD  
30  
[2]  
[3]  
[4]  
HBM  
MM  
±1500  
±200  
200  
V
Ilu  
latch-up current  
mA  
°C  
°C  
°C  
Tj  
junction temperature  
storage temperature  
ambient temperature  
+150  
[5]  
Tstg  
Tamb  
−65 +150  
−40 +85  
operating device  
[1] Parameters are valid over the whole operating temperature range unless otherwise specified. All voltages  
are referenced to VSS unless otherwise specified.  
[2] Pass level; Human Body Model (HBM), according to Ref. 4 “JESD22-A114”.  
[3] Pass level; Machine Model (MM), according to Ref. 5 “JESD22-A115”.  
[4] Pass level; latch-up testing according to Ref. 6 “JESD78” at maximum ambient temperature (Tamb(max)).  
[5] According to the NXP store and transport requirements (see Ref. 8 “NX3-00092”) the devices have to be  
stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products  
deviant conditions are described in that document.  
PCF8531  
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34 x 128 pixel matrix driver  
13. Static characteristics  
Table 15. Static characteristics  
VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V;  
Tamb = −40 °C to +85 °C; unless otherwise specified.  
Symbol  
Supplies  
VLCD  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
[1]  
[1]  
LCD supply voltage  
supply voltage 1  
4.0  
3.0  
1.9  
1.8  
2.5  
-
-
-
-
-
9.0  
9.0  
5.5  
5.5  
4.5  
V
V
V
V
V
icon mode  
VDD1  
logic supply  
Tamb ≥ −25 °C  
VDD2  
VDD3  
IDD  
supply voltage 2  
supply voltage 3  
supply current  
multiplier supply; LCD voltage  
internally generated  
multiplier supply; LCD voltage  
internally generated  
2.5  
-
4.5  
V
power-down mode; internal VLCD  
normal mode; internal VLCD  
normal mode; external VLCD  
normal mode; external VLCD  
icon mode; external VLCD  
-
2
10  
μA  
μA  
μA  
μA  
μA  
V
[2][3]  
[2]  
-
170  
10  
25  
15  
1.2  
350  
50  
-
[2][4]  
[2][5]  
[6]  
IDD(LCD)  
LCD supply current  
-
100  
70  
-
VPOR  
Logic  
VIL  
power-on reset voltage  
0.9  
1.6  
LOW-level input voltage  
HIGH-level input voltage  
VSS  
-
-
-
0.3VDD  
V
VIH  
0.7VDD  
3.0  
VDD  
-
V
IOL(SDA)  
LOW-level output current VOL = 0.4 V; VDD = 5.0 V  
on pin SDA  
mA  
ILI  
input leakage current  
VI = VDD or VSS  
−1  
-
+1  
μA  
Column and row outputs  
[7]  
[8]  
RO  
output resistance  
column outputs: C0 to C127  
row outputs: R0 to R33  
-
12  
12  
0
20  
kΩ  
kΩ  
mV  
-
20  
ΔVbias  
bias voltage variation  
outputs R0 to R33 and  
C0 to C127  
−100  
+100  
ΔVLCD  
LCD voltage variation  
temperature coefficient  
TC1 to TC7  
-
-
±3.9  
%
TC  
Tamb = −20 °C to +70 °C  
TC0; TC[2:0] = 000  
TC1; TC[2:0] = 001  
TC2; TC[2:0] = 010  
TC3; TC[2:0] = 011  
TC4; TC[2:0] = 100  
TC5; TC[2:0] = 101  
TC6; TC[2:0] = 110  
TC7; TC[2:0] = 111  
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
%/K  
%/K  
%/K  
%/K  
%/K  
%/K  
%/K  
%/K  
°C  
−0.026  
−0.039  
−0.052  
−0.078  
−0.13  
−0.19  
−0.26  
27  
Tints  
intersection temperature  
PCF8531  
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34 x 128 pixel matrix driver  
[1] As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure,  
while setting the VOP register and selecting the temperature compensation, that the VLCD maximum limit of 9 V will never be exceeded  
under all conditions and including all tolerances.  
[2] LCD outputs are open circuit, inputs at VDD or VSS; bus inactive.  
[3] VDD1 to VDD3 = 2.85 V; VLCD = 7.0 V; voltage multiplier = 3 × VDD; fosc = 34 kHz.  
[4] VDD1 to VDD3 = 2.75 V; VLCD = 9.0 V; fosc = 34 kHz.  
[5] VDD1 to VDD3 = 2.75 V; VLCD = 3.5 V; fosc = 34 kHz.  
[6] Resets all logic when VDD1 < VPOR  
.
[7] Iload ≤ 50 μA; outputs are tested one at a time.  
[8] VLCD ≤ 7.7 V.  
14. Dynamic characteristics  
Table 16. Dynamic characteristics  
VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V;  
Tamb = −40 °C to +85 °C; unless otherwise specified.  
Symbol  
ffr(LCD)  
fosc  
Parameter  
Conditions  
Min  
40  
20  
20  
300  
-
Typ  
66  
34  
-
Max  
135  
65  
65  
-
Unit  
Hz  
[1]  
LCD frame frequency  
oscillator frequency  
external clock frequency  
RES LOW pulse width  
RES LOW set-up time  
VDD = 3.0 V  
kHz  
kHz  
ns  
fclk(ext)  
tw(RESL)  
tsu(RESL)  
[2]  
-
-
30  
μs  
Serial bus interface (see Figure 22)[3]  
fSCL  
SCL clock frequency  
0
-
-
-
-
-
-
-
-
-
-
-
-
400  
-
kHz  
μs  
μs  
ns  
ns  
μs  
μs  
pF  
μs  
μs  
μs  
ns  
tLOW  
tHIGH  
tSU;DAT  
tHD;DAT  
tr  
LOW period of the SCL clock  
HIGH period of the SCL clock  
data set-up time  
1.3  
0.6  
-
100  
-
data hold time  
0
0.9  
0.3  
0.3  
400  
-
[4]  
[4]  
rise time of both SDA and SCL signals  
fall time of both SDA and SCL signals  
capacitive load for each bus line  
set-up time for a repeated START condition  
hold time (repeated) START condition  
set-up time for STOP condition  
20 + 0.1Cb  
tf  
20 + 0.1Cb  
Cb  
-
tSU;STA  
tHD;STA  
tSU;STO  
tSP  
0.6  
0.6  
0.6  
-
-
-
pulse width of spikes that must be  
suppressed by the input filter  
on bus  
50  
tBUF  
bus free time between a STOP and START  
condition  
1.3  
-
-
μs  
[1] ffr = fclk(ext)/480 or fosc/480.  
[2] A reset is generated if tw(RESL) > 3 ns (see Figure 21).  
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH, with an  
input voltage swing of VSS to VDD  
.
[4] Cb = total capacitance of one bus line in pF.  
PCF8531  
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© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
35 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
V
DD  
RES  
V
IL  
t
t
mgs476  
su(RESL)  
w(RESL)  
Fig 21. Reset timing  
SDA  
SCL  
t
t
t
f
BUF  
LOW  
t
HD;STA  
t
r
t
t
SU;DAT  
HD;DAT  
t
HIGH  
SDA  
t
SU;STA  
t
SU;STO  
mga728  
Fig 22. I2C-bus timing  
PCF8531  
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Product data sheet  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
mgs478  
mgs477  
400  
400  
I
I
DD  
DD  
(μA)  
(μA)  
2×  
5×  
300  
300  
4×  
3×  
200  
100  
200  
100  
V
LCD  
= 9 V  
7.5 V  
4 V  
2
4
6
8
10  
2
3
4
DD2  
5
(V)  
V
LCD  
(V)  
V
and V  
DD3  
VDD1 = 2 V; 4 × voltage multiplier; Tamb = 27 °C; TC = 0;  
BS = 100; no VLCD load.  
VDD1 = 1.8 V; VDD2 and VDD3 = 2.6 V; Tamb = 27 °C;  
fosc = 34 kHz; no VLCD load.  
Fig 23. Supply current as a function of supply  
voltage 2 and supply voltage 3  
Fig 24. Supply current as a function of LCD supply  
voltage; different multiplication factors  
mgs479  
mgs480  
9
30  
V
LCD  
I
(μA)  
(V)  
8
7
6
20  
I
DD(LCD)  
TC  
TC  
0
1
I
DD  
10  
TC  
TC  
6
7
0
−50  
0
50  
100  
2
4
6
8
10  
T (°C)  
V
LCD  
(V)  
VLCD = 7.5 V; VDD1 to VDD3 = 2.7 V; Tamb = 27 °C;  
no VLCD load.  
VDD1 = 1.8 V; VDD2 and VDD3 = 2.5 V; external VLCD  
amb = 27 °C; TC = 0; BS = 100; no VLCD load.  
;
T
Fig 25. LCD supply voltage as a function of  
temperature  
Fig 26. Supply current as a function of LCD supply  
voltage  
PCF8531  
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Product data sheet  
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37 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
mgs482  
mgs481  
30  
86  
I
DD  
I
(μA)  
(μA)  
84  
I
DD(LCD)  
20  
10  
0
82  
80  
78  
I
DD  
0
20  
40  
60  
80  
3
3.2  
3.4  
3.6  
3.8  
V
4
(V)  
f (kHz)  
LCD  
VDD1 = 2.5 V; VDD2 and VDD3 = 2.5 V; external VLCD  
;
VDD1 = 1.8 V; VDD2 = 2.5 V; 2 × voltage multiplier;  
amb = 27 °C; TC = 0; BS = 111; no VLCD load.  
Tamb = 27 °C; TC = 0; BS = 100; no VLCD load.  
T
Fig 27. Supply current as a function of frequency  
Fig 28. Supply current as a function of LCD supply  
voltage  
PCF8531  
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Product data sheet  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
15. Application information  
15.1 Typical system configuration  
V
LCD  
V
to V  
DD3  
DD1  
V
DD(I2C)  
128 column drivers  
34 row drivers  
HOST  
MICROPROCESSOR/  
MICROCONTROLLER  
PCF8531  
LCD PANEL  
R
R
pu  
pu  
V
SS1  
V
SS2  
,
V
SS  
RES  
SCL  
SDA  
V
, V  
SS1 SS2  
mgs483  
Fig 29. Typical system configuration  
The host microprocessor/microcontroller and the PCF8531 are both connected to the  
I2C-bus. The SDA and SCL lines must be connected to the positive power supply via  
pull-up resistors. The internal oscillator requires no external components. The appropriate  
intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip.  
The only other connections required to complete the system are to the power supplies  
(VDD, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD  
.
15.2 Power supply connections for internal VLCD generation  
1.8 V (1.9 V) to 5.5 V  
V
DD1  
V
DD1  
1 μF  
V
V
DD2  
2.5 V to 4.5 V  
V
V
DD2  
DD3  
2.5 V to 4.5 V  
1 μF  
DD3  
1 μF  
V
SS1  
V
SS2  
V
SS1  
V
SS2  
GND  
GND  
013aaa354  
013aaa355  
Fig 30. Recommended VDD connections for internal VLCD generation  
PCF8531  
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Product data sheet  
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39 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
V
V
LCDIN  
LCDOUT  
1 μF  
V
SS2  
V
LCDSENSE  
013aaa356  
Fig 31. Recommended VLCD connections for internal VLCD generation  
15.3 Power supply connections for external VLCD generation  
4.0 V to 9.0 V  
V
LCDIN  
V
LCDIN  
V
DD1  
1.8 V (1.9 V) to 5.5 V  
1 μF  
4.0 V to 9.0 V  
or  
V
V
V
V
n.c.  
n.c.  
LCDOUT  
LCDOUT  
V
V
DD2  
1 μF  
DD3  
V
SS1  
V
SS2  
LCDSENSE  
LCDSENSE  
GND  
013aaa358  
Remark: When using an external VLCD, the internal VLCD generator must never be switched on  
otherwise damages will occur.  
Fig 32. Recommended VDD connections for external VLCD generation  
15.4 Information about VLCD connections  
VLCDIN — This input is used for generating the 5 LCD bias levels. It is the power supply for  
the bias level buffers.  
V
LCDOUT — This is the VLCD output if VLCD is generated internally. It is the output of the  
charge pump. In this case pin VLCDOUT must be connected to VLCDIN and to VLCDSENSE  
(see Figure 31). VLCDOUT must be left open circuit when VLCD is supplied from an external  
source (see Figure 32).  
V
LCDSENSE — When using the internal VLCD generation, this pin must be connected to  
V
LCDOUT and VLCDIN (see Figure 31). When using an external VLCD supply it must be  
connected to VLCDIN or to ground (see Figure 32).  
PCF8531  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
15.5 Chip-on-glass application  
DISPLAY 34 × 128 PIXELS  
17  
128  
17  
PCF8531  
R
R
supply  
I/O  
C
ext  
3
V
V
SS1  
SS2  
V
V
V
LCD  
DD1  
to  
I/O  
DD3  
mgs484  
Fig 33. Chip-on-glass application  
The required minimum values for the external capacitors in a chip-on-glass application  
are:  
• Cext = 100 nF between VLCD and VSS1, VSS2; Cext = 470 nF between VDD1, VDD2, VDD3  
and VSS1, VSS2  
.
• Higher capacitor values are recommended for ripple reduction.  
• For COG applications, the recommended ITO track resistance must be minimized for  
the I/O and supply connections. Optimized values for these tracks are below 50 Ω for  
the supply (Rsupply) and below 100 Ω for the I/O connections (RI/O).  
• To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application,  
NXP strongly recommended implementing a series input resistance in the reset line  
(recommended minimum value 8 kΩ) on the glass (ITO). If the reset input is not used,  
this input must be connected to VDD1 using a short connection.  
PCF8531  
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Product data sheet  
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41 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
15.6 Programming example  
Table 17. Programming example for PCF8531  
Step  
Serial bus byte  
Display  
Operation  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
1
2
3
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
SA0  
0
0
0
1
start; slave address; R/W = 0  
control byte; Co = 1; RS = 0  
0
H[1:0] independent  
command; select function  
and RAM command page  
(H[1:0] = 00)  
4
5
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
control byte; Co = 1; RS = 0  
function and RAM command  
page PD = 0 and V = 1  
6
7
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
control byte; Co = 1; RS = 0  
function and RAM command  
page select display setting  
command page H[1:0] = 01  
8
9
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
control byte; Co = 1; RS = 0  
display setting command  
page; set normal mode  
(D = 1; IM = 0 and E = 0)  
10  
11  
12  
13  
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
control byte; Co = 1; RS = 0  
select multiplex rate 1:34  
control byte; Co = 1; RS = 0  
H[2:0] independent  
command; select function  
and RAM command page  
H[1:0] = 00  
14  
15  
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
control byte; Co = 1; RS = 0  
function and RAM command  
page; select HV-gen  
command page H[1:0] = 10  
16  
17  
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
control byte; Co = 1; RS = 0  
HV-gen command page;  
select voltage multiplication  
factor 5 S[1:0] = 11  
18  
19  
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
control byte; Co = 1; RS = 0  
HV-gen command page;  
select temperature  
coefficient 2 TC[2:0] = 010  
20  
21  
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
control byte; Co = 1; RS = 0  
HV-gen command page;  
select high VLCD  
programming range  
(PRS = 1); voltage multiplier  
off (HVE = 1)  
22  
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0  
PCF8531  
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Product data sheet  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Table 17. Programming example for PCF8531 …continued  
Step  
Serial bus byte  
Display  
Operation  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
23  
1
0
1
0
0
0
0
0
HV-gen command page; set  
VLCD = 7.71 V;  
VOP[6:0] = 0100000  
24  
25  
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
control byte; Co = 0; RS = 1  
data write; Y and X are  
initialized to 0 by default, so  
they are not set here  
mgs405  
mgs406  
mgs407  
mgs407  
mgs409  
mgs410  
mgs411  
mgs411  
26  
27  
28  
29  
30  
31  
32  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
data write  
data write  
data write  
data write  
data write  
1
0
1
0
1
data write; last data and stop  
transmission  
SA0  
repeated start; slave address;  
R/W = 0  
PCF8531  
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Product data sheet  
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PCF8531  
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34 x 128 pixel matrix driver  
Table 17. Programming example for PCF8531 …continued  
Step  
Serial bus byte  
Display  
Operation  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
33  
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0  
mgs411  
34  
0
0
0
0
0
0
0
1
H[1:0] independent  
command; select function  
and RAM command page  
H[1:0] = 00  
35  
36  
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
control byte; Co = 1; RS = 0  
function and RAM command  
page; select display setting  
command page H[1:0] = 01  
mgs411  
37  
38  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
control byte; Co = 1; RS = 0  
H[1:0] independent  
command; select function  
and RAM command page  
H[1:0] = 00  
39  
40  
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
control byte; Co = 1; RS = 0  
display control; set inverse  
video mode (D = 1; E = 1  
and IM = 0)  
mgs412  
mgs412  
mgs412  
mgs412  
mgs414  
41  
42  
43  
44  
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0  
set X address of RAM; set  
address to ‘0000000’  
control byte; Co = 0; RS = 1  
data write  
PCF8531  
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NXP Semiconductors  
34 x 128 pixel matrix driver  
16. Package outline  
Not applicable.  
17. Handling information  
All input and output pins are protected against ElectroStatic Discharge (ESD) under  
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that  
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent  
standards.  
18. Packing information  
Table 18. Tray dimensions (see Figure 34)  
Symbol  
Description  
Value  
A
B
C
D
E
F
x
pocket pitch in x direction  
pocket pitch in y direction  
pocket width in x direction  
pocket width in y direction  
tray width in x direction  
tray width in y direction  
number of pockets, x direction  
13.72 mm  
4.17 mm  
12.34 mm  
2.05 mm  
50.8 mm  
50.8 mm  
3
y
number of pockets, y direction 10  
x
A
C
y
D
B
F
E
mgs488  
Fig 34. Tray details  
PCF8531  
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Product data sheet  
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45 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
P C F 8 5 3 1  
mgs489  
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die  
surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad  
location diagram (Figure 2) for the orientating and position of the type name on the die surface.  
Fig 35. Tray alignment  
19. Abbreviations  
Table 19. Abbreviations  
Acronym  
Description  
CDM  
CMOS  
COG  
DDRAM  
EMC  
ESD  
HBM  
HV  
Charged Device Model  
Complementary Metal-Oxide Semiconductor  
Chip-On-Glass  
Double Data Random Access Memory  
ElectroMagnetic Compatibility  
ElectroStatic Discharge  
Human Body Model  
High Voltage  
IC  
Integrated Circuit  
ITO  
Indium Tin Oxide  
LCD  
LSB  
MM  
Liquid Crystal Display  
Least Significant Bit  
Machine Model  
MPU  
POR  
RAM  
RC  
MicroProcessor Unit  
Power-On Reset  
Random Access Memory  
Resistance-Capacitance  
Temperature Coefficient  
Serial Clock Line  
TC  
SCL  
SDA  
Serial DAta line  
PCF8531  
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Product data sheet  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
20. References  
[1] AN10706 — Handling bare die  
[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous  
semiconductor devices  
[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena  
[4] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body  
Model (HBM)  
[5] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model  
(MM)  
[6] JESD78 — IC Latch-Up Test  
[7] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive  
(ESDS) Devices  
[8] NX3-00092 — NXP store and transport requirements  
[9] UM10204 — I2C-bus specification and user manual  
PCF8531  
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Product data sheet  
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PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
21. Revision history  
Table 20. Revision history  
Document ID  
PCF8531 v.5  
Modifications:  
Release date  
20100810  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
PCF8531_4  
• Added Figure 11, Figure 30 to Figure 32  
• Added Section 15.2 to Section 15.4  
• Changes and corrections in Table 4 and Table 11  
• Deleted old fab information  
PCF8531_4  
20080613  
20000211  
19990810  
19990322  
Product data sheet  
Product data sheet  
Product data sheet  
Product data sheet  
-
-
-
-
PCF8531_3  
PCF8531_2  
PCF8531_SDS_1  
-
PCF8531_3  
PCF8531_2  
PCF8531_SDS_1  
PCF8531  
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NXP Semiconductors  
34 x 128 pixel matrix driver  
22. Legal information  
22.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
22.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
22.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
49 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Bare die — All die are tested on compliance with their related technical  
specifications as stated in this data sheet up to the point of wafer sawing and  
are handled in accordance with the NXP Semiconductors storage and  
transportation conditions. If there are data sheet limits not guaranteed, these  
will be separately indicated in the data sheet. There are no post-packing tests  
performed on individual die or wafers.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors has no control of third party procedures in the sawing,  
handling, packing or assembly of the die. Accordingly, NXP Semiconductors  
assumes no liability for device functionality or performance of the die or  
systems after third party sawing, handling, packing or assembly of the die. It  
is the responsibility of the customer to test and qualify their application in  
which the die is used.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
All die sales are conditioned upon and subject to the customer entering into a  
written die sale agreement with NXP Semiconductors through its legal  
department.  
22.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
I2C-bus — logo is a trademark of NXP B.V.  
23. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PCF8531  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 05 — 10 August 2010  
50 of 51  
PCF8531  
NXP Semiconductors  
34 x 128 pixel matrix driver  
24. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
10.1.4  
10.2  
10.3  
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 29  
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 30  
Command decoder . . . . . . . . . . . . . . . . . . . . 31  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
11  
12  
13  
14  
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 32  
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33  
Static characteristics . . . . . . . . . . . . . . . . . . . 34  
Dynamic characteristics. . . . . . . . . . . . . . . . . 35  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6  
15  
15.1  
15.2  
Application information . . . . . . . . . . . . . . . . . 39  
Typical system configuration . . . . . . . . . . . . . 39  
Power supply connections for internal  
VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 39  
Power supply connections for external  
VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 40  
Information about VLCD connections . . . . . . . 40  
Chip-on-glass application. . . . . . . . . . . . . . . . 41  
Programming example. . . . . . . . . . . . . . . . . . 42  
7
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
Functional description . . . . . . . . . . . . . . . . . . 14  
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 14  
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 14  
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Display data RAM. . . . . . . . . . . . . . . . . . . . . . 14  
Timing generator. . . . . . . . . . . . . . . . . . . . . . . 14  
Address counter . . . . . . . . . . . . . . . . . . . . . . . 14  
Display address counter. . . . . . . . . . . . . . . . . 14  
Command decoder. . . . . . . . . . . . . . . . . . . . . 14  
Bias voltage generator . . . . . . . . . . . . . . . . . . 15  
VLCD generator . . . . . . . . . . . . . . . . . . . . . . . . 15  
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Column driver outputs. . . . . . . . . . . . . . . . . . . 15  
Row driver outputs . . . . . . . . . . . . . . . . . . . . . 15  
15.3  
15.4  
15.5  
15.6  
16  
17  
18  
19  
20  
21  
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 45  
Handling information . . . . . . . . . . . . . . . . . . . 45  
Packing information . . . . . . . . . . . . . . . . . . . . 45  
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46  
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 48  
7.8  
7.9  
7.10  
7.11  
7.12  
7.13  
7.14  
7.15  
22  
Legal information . . . . . . . . . . . . . . . . . . . . . . 49  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 49  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
22.1  
22.2  
22.3  
22.4  
8
LCD waveforms and DDRAM to data  
mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
8.1  
9
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
PD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Set Y address. . . . . . . . . . . . . . . . . . . . . . . . . 21  
Set X address. . . . . . . . . . . . . . . . . . . . . . . . . 21  
Set multiplex rate . . . . . . . . . . . . . . . . . . . . . . 21  
Display control (D, E, and IM). . . . . . . . . . . . . 21  
Set bias system . . . . . . . . . . . . . . . . . . . . . . . 22  
LCD bias voltage . . . . . . . . . . . . . . . . . . . . . . 23  
Set VLCD value . . . . . . . . . . . . . . . . . . . . . . . . 23  
Voltage multiplier control S[1:0] . . . . . . . . . . . 24  
Temperature compensation . . . . . . . . . . . . . . 24  
23  
24  
Contact information . . . . . . . . . . . . . . . . . . . . 50  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
9.1  
9.2  
9.2.1  
9.2.2  
9.3  
9.4  
9.5  
9.6  
9.7  
9.8  
9.9  
9.10  
9.11  
10  
10.1  
10.1.1  
10.1.2  
10.1.3  
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 28  
Characteristics of the I2C-bus. . . . . . . . . . . . . 28  
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
START and STOP conditions . . . . . . . . . . . . . 28  
System configuration . . . . . . . . . . . . . . . . . . . 28  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2010.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 10 August 2010  
Document identifier: PCF8531  

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