935286782518 [NXP]
70W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO36, PLASTIC, SOT851-2, HSOP-36;
| 型号： | 935286782518 |
| 厂家： | 
NXP |
| 描述： | 70W, 2 CHANNEL, AUDIO AMPLIFIER, PDSO36, PLASTIC, SOT851-2, HSOP-36 放大器 光电二极管 商用集成电路 |
| 文件： | 总53页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDF8599
I2C-bus controlled dual channel 43 W/2 Ω single channel
85 W/1 Ω class-D power amplifier with load diagnostics
Rev. 02 — 30 July 2009
Product data sheet
1. General description
The TDF8599 is a dual Bridge-Tied Load (BTL) car audio amplifier comprising an
NDMOST-NDMOST output stage based on SOI BCDMOS technology. Low power
dissipation enables the TDF8599 high-efficiency, class-D amplifier to be used with a
smaller heat sink than those normally used with standard class-AB amplifiers.
The TDF8599 can operate in either non-I2C-bus mode or I2C-bus mode. When in I2C-bus
mode, DC load detection results and fault conditions can be easily read back from the
device. Up to five I2C-bus addresses can be selected depending on the value of the
external resistor connected to pins ADS and MOD.
When pin ADS is short circuited to pin AGND, the TDF8599 operates in non-I2C-bus
mode. Switching between Operating mode and Mute mode in non-I2C-bus mode is only
possible using pins EN and SEL_MUTE.
2. Features
I High-efficiency
I Low quiescent current
I Operating voltage from 8 V to 18 V
I Two 4 Ω/2 Ω capable BTL channels or one 1 Ω capable BTL channel
I Differential inputs
I Supports I2C-bus mode with five I2C-bus addresses or non-I2C-bus mode operation
I Clip detect
I Independent short circuit protection for each channel
I Advanced short circuit protection for load, GND and supply
I Load dump protection
I Thermal foldback and thermal protection
I DC offset protection
I Selectable AD or BD modulation
I Parallel channel mode for high current drive capability
I Advanced clocking:
N Switchable oscillator clock source: internal for Master mode or external for Slave
mode
N Spread spectrum mode
N Phase staggering
N Frequency hopping
I No ‘pop noise’ caused by DC output offset voltage
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
I I2C-bus mode:
N DC load detection
N AC load detection
N Thermal pre-warning diagnostic level setting
N Identification of activated protections or warnings
N Selectable diagnostic information available using pin DIAG and pin CLIP
I Qualified in accordance with AEC-Q100
3. Applications
I Car audio
4. Quick reference data
Table 1.
Quick reference data
VP = 14.4 V unless otherwise stated.
Symbol
VP
Parameter
Conditions
Min
Typ
14.4
-
Max
18
Unit
V
[1]
[2]
supply voltage
standby current
total quiescent current
8
-
Istb
voltage on pin EN < 0.8 V
10
µA
mA
Iq(tot)
Operating mode; no load, snubbers and
filter connected
-
90
120
Po
output power
Stereo mode
THD = 1 %; RL = 4 Ω
THD = 10 %; RL = 4 Ω
square wave (EIAJ); RL = 4 Ω
THD = 1 %; RL = 2 Ω
THD = 10 %; RL = 2 Ω
square wave (EIAJ); RL = 2 Ω
Parallel mode
18
24
-
20
26
40
32
43
70
-
-
-
-
-
-
W
W
W
W
W
W
29
39
-
[2]
THD = 10 %; RL = 1 Ω
-
85
-
W
[1] In this data sheet, VP1, VP2 and VPA are all described as VP.
[2] Output power is measured indirectly based on RDSon measurement.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDF8599TH
TDF8599TD
HSOP36
HSOP36
plastic, heatsink small outline package; 36 leads; low stand-off height
plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-2
SOT938-1
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
2 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
6. Block diagram
V
V
V
P2
DDA
10
P1
31
24
34
32
VSTAB1
BOOT1N
STABI1
9
8
AGND
SVRR
V
P1
DRIVER
HIGH
TDF8599
33
29
PWM
CONTROL
OUT1N
1
2
DRIVER
LOW
IN1P
IN1N
PGND1
BOOT1P
V
P1
DRIVER
HIGH
28
23
PWM
CONTROL
OUT1P
DRIVER
LOW
PGND1
5
ACGND
BOOT2N
+
V
P2
DRIVER
HIGH
22
26
27
PWM
CONTROL
OUT2N
BOOT2P
OUT2P
3
4
DRIVER
LOW
IN2P
IN2N
PGND2
V
P2
DRIVER
HIGH
PWM
CONTROL
DRIVER
LOW
18
19
17
12
OSCSET
OSCIO
SSM
PGND2
OSCILLATOR
5 V STABI
MOD
35
21
V
DDD
VSTAB2
STABI2
6
EN
SEL_MUTE
SCL
7
PROTECTION
MODE
SELECT
+
DIAGNOSTICS
16
15
11
OVP, OCP, OTP,
UVP, TFP,
2
SDA
I C-BUS
WP,DCP.
ADS
36
14
13
20
30
25
GNDD/HW
DIAG CLIP DCP
PGND1
PGND2
001aai766
Fig 1. Block diagram
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
3 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
7. Pinning information
7.1 Pinning
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
GNDD/HW
IN1P
V
DDD
IN1N
3
VSTAB1
OUT1N
IN2P
4
IN2N
5
BOOT1N
ACGND
EN
6
V
P1
7
PGND1
BOOT1P
OUT1P
SEL_MUTE
SVRR
AGND
8
9
TDF8599TH
10
11
12
13
14
15
16
17
18
OUT2P
V
DDA
BOOT2P
PGND2
ADS
MOD
CLIP
DIAG
SDA
V
P2
BOOT2N
OUT2N
VSTAB2
DCP
SCL
SSM
OSCIO
OSCSET
001aai767
Fig 2. Heatsink up (top view) pin configuration TDF8599TH
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
4 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
1
2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
IN1P
IN1N
GNDD/HW
V
DDD
3
IN2P
VSTAB1
OUT1N
4
IN2N
5
ACGND
EN
BOOT1N
6
V
P1
7
SEL_MUTE
SVRR
PGND1
BOOT1P
OUT1P
OUT2P
BOOT2P
PGND2
8
9
AGND
TDF8599TD
10
11
12
13
14
15
16
17
18
V
DDA
ADS
MOD
CLIP
V
P2
DIAG
SDA
BOOT2N
OUT2N
VSTAB2
DCP
SCL
SSM
OSCSET
OSCIO
001aai768
Fig 3. Heatsink down (top view) pin configuration TDF8599TD
7.2 Pin description
Table 3.
Pin description
Pin Type[1]
Symbol
IN1P
Description
1
2
3
4
5
6
I
I
I
I
I
I
channel 1 positive audio input
channel 1 negative audio input
channel 2 positive audio input
channel 2 negative audio input
decoupling for input reference voltage
enable input:
IN1N
IN2P
IN2N
ACGND
EN
non-I2C-bus mode: switch between off and Mute mode
I2C-bus mode: off and Standby mode
select mute or unmute
SEL_MUTE
SVRR
AGND
VDDA
7
I
8
I
decoupling for internal half supply reference voltage
analog supply ground
9
G
P
I
10
11
analog supply voltage
ADS
non-I2C-bus mode: connected to pin AGND
I2C-bus mode: selection and address selection pin
modulation mode, phase shift and parallel mode select
MOD
12
I
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
5 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Table 3.
Pin description …continued
Symbol
CLIP
DIAG
SDA
Pin Type[1]
Description
13
14
15
16
17
O
O
I/O
I
clip output; open-drain
diagnostic output; open-drain
I2C-bus data input and output
I2C-bus clock input
SCL
SSM
master setting: Spread spectrum mode frequency
slave setting: phase lock operation
master/slave oscillator setting
OSCSET
OSCIO
18
19
master only setting: set internal oscillator frequency
external oscillator slave setting: input
internal oscillator master setting: output
DC protection input for the filtered output voltages
decoupling internal stabilizer 2 for DMOST drivers
channel 2 negative PWM output
boot 2 negative bootstrap capacitor
channel 2 power supply voltage
channel 2 power ground
I/O
I
DCP
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSTAB2
OUT2N
BOOT2N
O
[2]
VP2
P
PGND2
BOOT2P
OUT2P
OUT1P
BOOT1P
PGND1
G
boot 2 positive bootstrap capacitor
channel 2 positive PWM output
channel 1 positive PWM output
boot 1 positive bootstrap capacitor
channel 1 power ground
O
O
G
P
[2]
VP1
channel 1 power supply voltage
boot 1 negative bootstrap capacitor
channel 1 negative PWM output
decoupling internal stabilizer 1 for DMOST drivers
decoupling of the internal 5 V logic supply
ground digital supply voltage
BOOT1N
OUT1N
VSTAB1
VDDD
O
G
GNDD/HW
handle wafer connection
[1] I = input, O = output, I/O = input/output, G = ground and P = power supply.
[2] In this data sheet supply voltage VP describes VP1 and VP2
.
8. Functional description
8.1 General
The TDF8599 is a dual full bridge (BTL) audio power amplifier using class-D technology.
The audio input signal is converted into a Pulse-Width Modulated (PWM) signal using the
analog input and PWM control stages. A PWM signal is applied to driver circuits for both
high-side and low-side enabling the DMOS power output transistors to be driven. An
external 2nd order low-pass filter converts the PWM signal into an analog audio signal
across the loudspeakers.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
6 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
The TDF8599 includes integrated common circuits for all channels such as the oscillator,
all reference sources, mode functionality and a digital timing manager. In addition, the
built-in protection includes thermal foldback, temperature, overcurrent and overvoltage
(load dump).
The TDF8599 operates in either I2C-bus mode or non-I2C-bus mode. In I2C-bus mode,
DC load detection, frequency hopping and extended configuration functions are provided
together with enhanced diagnostic information.
8.2 Mode selection
The mode pins EN, ADS and SEL_MUTE enable mute state, I2C-bus mode and Operating
mode switching.
Pin SEL_MUTE is used to mute and unmute the device and must be connected to an
external capacitor (CON). This capacitor generates a time constant which is used to
ensure smooth fade-in and fade-out of the input signal.
The TDF8599 is enabled when pin EN is HIGH. When pin EN is LOW, the TDF8599 is off
and the supply current is at its lowest value (typically 2 µA). When off, the TDF8599 is
completely deactivated and will not react to I2C-bus commands.
I2C-bus mode is selected by connecting a resistor between pins ADS and AGND. In
I2C-bus mode with pin EN HIGH, the TDF8599 waits for further commands (see Table 4).
I2C-bus mode is described in Section 9 on page 24.
Non-I2C-bus mode is selected by connecting pin ADS to pin AGND. In non-I2C-bus mode,
the default TDF8599 state is Mute mode. The amplifiers switch idle (50 % duty cycle) and
the audio signal is suppressed at the output. In addition, the capacitor (CSVRR) is charged
to half the supply voltage. To enter Operating mode, pin SEL_MUTE must be HIGH with
S1 open, enabling capacitor (CON) charged by an internal pull-up (see Figure 4). In
addition, pin EN must be driven HIGH.
S2
S2
EN
EN
3.3 V
3.3 V
ADS
ADS
TDF8599
TDF8599
SEL_MUTE
SEL_MUTE
R
ADS
AGND
AGND
C
ON
C
ON
S1
001aai769
001aai770
a. Non-I2C-bus mode
b. I2C-bus mode
See Table 13 for detailed information on
RADS
.
Fig 4. Mode selection
I2C-bus mode and non-I2C-bus mode control are described in Table 4 on page 8 and
Table 5 on page 8. Switches S1 and S2 are shown in Figure 4.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
7 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Table 4.
I2C-bus mode operation
Pin EN
Pin SEL_MUTE
Bit IB1[D0]
Bit IB2[D0]
Mode
HIGH (S2 closed)
HIGH
LOW
LOW
X[1]
1
0
Operating mode
Mute mode
Standby mode
off
1
1
0
X[1]
X[1]
X[1]
LOW (S2 open)
[1] X = do not care.
Table 5.
Pin EN
Non-I2C-bus mode operation
Pin SEL_MUTE
Mode
HIGH (S2 closed)
HIGH (S1 open)
LOW (S1 closed)
X[1]
Operating mode
Mute mode
off
LOW (S2 open)
[1] X = do not care.
8.3 Pulse-width modulation frequency
The output signal from the amplifier is a PWM signal with a clock frequency of fosc. This
frequency is set by connecting a resistor (Rosc) between pins OSCSET and AGND. The
optimal clock frequency setting is between 300 kHz and 400 kHz. Connecting a resistor
with a value of 39 kΩ, for example, sets the clock frequency to 320 kHz (see Figure 6).
The external capacitor (Cosc) has no influence on the oscillator frequency. It does
however, reduce jitter and sensitivity to disturbance. Using a 2nd order LC demodulation
filter in the application generates an analog audio signal across the loudspeaker.
8.3.1 Master and slave mode selection
In a master and slave configuration, multiple TDF8599 devices are daisy-chained together
in one audio application with a single device providing the clock frequency signal for all
other devices. In this situation, it is recommended that the oscillators of all devices are
synchronized for optimum EMI behavior as follows:
All OSCIO pins are connected together and one TDF8599 in the application is configured
as the clock-master. All other TDF8599 devices are configured as clock-slaves (see
Figure 6).
• The clock-master pin OSCIO is configured as the oscillator output. When a resistor
(Rosc) is connected between pins OSCSET and AGND, the TDF8599 is in Master
mode.
• The clock-slave pins OSCIO are configured as the oscillator inputs. When pin
OSCSET is directly connected to pin AGND (see Table 6), the TDF8599 is in Slave
mode.
Table 6.
Mode
Mode setting pin OSCIO
Settings
Pin OSCSET
Pin OSCIO
output
Master
Slave
Rosc > 26 kΩ
Rosc = 0 Ω; shorted to pin AGND
input
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
8 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
The value of the resistor Rosc sets the clock frequency based on Equation 1:
12.45 × 109
f osc
=
[Hz]
(1)
---------------------------
Rosc
001aai771
50
R
osc
(kΩ)
40
30
20
10
0
300
350
400
450
500
(kHz)
f
osc
Fig 5. Clock frequency as a function of Rosc
OSCSET
OSCSET
OSCSET
R
osc
C
osc
TDF8599
TDF8599
TDF8599
OSCIO
Master
OSCIO
Slave 1
OSCIO
Slave 2
R
f
osc
001aai772
Fig 6. Master and slave configuration
In Master mode, Spread spectrum mode and frequency hopping can be enabled. In Slave
mode, phase staggering and phase lock operation can be selected. An external clock can
be used as the master-clock on pin OSCIO of the slave devices. When using an external
clock it must remain active during the shutdown sequence to ensure that all devices are
switched off and able to enter the off state as described in Section 8.2.
8.3.2 Spread spectrum mode (Master mode)
Spread spectrum mode is a technique of modulating the oscillator frequency with a slowly
varying signal to broaden the switching spectrum, thereby reducing the spectral density of
the EMI. Connecting a capacitor (CSSM) to pin SSM enables Spread spectrum mode (see
Figure 7). When pin SSM is connected to pin AGND, Spread spectrum mode is disabled.
The capacitor on pin SSM (CSSM) sets the spreading frequency when Spread spectrum
mode is active. The current (ISSM) flowing in and out of pin SSM is typically 5 µA. This
gives a triangular voltage on pin SSM that sweeps around the voltage set by pin OSCSET
± 5 %. The voltage on pin SSM is used to modulate the oscillator frequency.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
9 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
The spread spectrum frequency (fSSM) can be calculated using Equation 2:
ISSM
f SSM
=
[Hz]
(2)
-----------------------------------------------------
2 × CSSM × V1 × 10 %
where the voltage on pin OSCSET = V1 and is calculated as 100 µA × Rosc (V) with
ISSM = 5 µA.
100 µA
100 µA
OSCSET
OSCSET
R
osc
C
osc
R
osc
C
osc
5 µA
I
SSM
SSM
SSM
C
SSM
001aai773
001aai774
a. Off
b. On
Fig 7. Spread spectrum mode
The frequency swings between 0.95 × fosc and 1.05 × fosc; see Figure 8.
OSCIO
max(V)
SSM
min(V)
t (ms)
001aai775
Fig 8. Spread spectrum operation in Master mode
8.3.3 Frequency hopping (Master mode)
Frequency hopping is a technique used to change the oscillator frequency for AM tuner
compatibility. In Master mode, the resistor connected between pins OSCSET and AGND
sets the oscillator frequency (fosc). In I2C-bus mode, this frequency can be varied by
± 10 %. Set bit IB1[D4] to logic 1 and bit IB1[D3] to either logic 0 (0.9 × fosc) or logic 1
(1.1 × fosc).
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect
of the external oscillator signal connected to pin OSCIO. Phase lock operation is also
needed to enable phase staggering, see Section 8.4.2. Phase lock operation is enabled
when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and CPLL_p) and
a resistor (RPLL) between pin SSM and pin AGND (see Figure 9).
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
10 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Connecting pin SSM to pin AGND disables phase lock operation and causes the slave to
directly use the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on
the desired loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BPLL Ω. The
corresponding values for CPLL_s and CPLL_p are given by Equation 3 and Equation 4:
0.032
RPLL × BPLL
CPLL_p
=
[F]
(3)
------------------------------
Remark: CPLL_p is only needed when 1⁄4 π phase shift is selected. See Section 8.4.2 for
more detailed information.
0.8
CPLL_s
=
[F]
(4)
------------------------------
RPLL × BPLL
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BPLL should be 100 × fSSM
.
100 µA
OSCSET
SSM
100 µA
OSCSET
PLL
C
PLL_s
SSM
PLL
(1)
R
PLL
C
PLL_p
001aai776
001aai777
(1) Only needed when 1⁄4 π phase shift is
selected.
a. Off
b. On
Fig 9. Phase lock operation
Table 7 lists all oscillator modes.
Table 7.
Oscillator modes
OSCSET pin
Rosc > 26 kΩ
Rosc > 26 kΩ
Rosc = 0 Ω
OSCIO pin
output
output
input
SSM pin
Oscillator modes
CSSM to pin AGND
shorted to pin AGND
master, spread spectrum
master, no spread spectrum
CPLL + RPLL to pin AGND slave, PLL enabled
shorted to pin AGND slave, PLL disabled
Rosc = 0 Ω
input
8.4 Operation mode selection
Pin MOD is used to select specific operating modes. The value of resistor (RMOD
)
connected between pins MOD and AGND together with the non-I2C-bus mode or I2C-bus
mode determine the operating mode (see Table 8). The mode of operation depends on
whether non-I2C-bus mode or I2C-bus mode is active. This in turn is determined by the
resistor value connected between pins ADS and AGND.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
11 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
In non-I2C-bus mode, pin MOD is used to select:
1. AD or BD modulation (see Section 8.4.1).
2. 1⁄2 π phase shift when an oscillator is used in Slave mode (see Section 8.4.2).
3. Parallel mode operation (see Section 8.4.3).
In I2C-bus mode, pin MOD can only select Parallel mode. In addition, the modulation
mode and phase shift are programmed using I2C-bus commands.
Table 8.
Operation mode selection with the MOD pin
I2C-bus mode Non-I2C-bus mode
RMOD (kΩ)
0 (short to AGND) Stereo mode
AD modulation: no phase shift in Slave mode
BD modulation: no phase shift in Slave mode
AD modulation: 1⁄2 π phase shift in Slave mode
BD modulation: 1⁄2 π phase shift in Slave mode
AD modulation: no phase shift in Slave mode
BD modulation: no phase shift in Slave mode
4.7
13
33
100
Parallel mode[1]
∞ (open)
[1] See Section 8.4.3 on page 14 for more detailed information.
The information on pin MOD is latched when one of the TDF8599 outputs starts switching,
to avoid incorrect information on pin MOD caused by disturbances of switching amplifier
outputs.
8.4.1 Modulation mode
In non-I2C-bus mode, pin MOD is used to select either AD or BD modulation mode (see
Table 8). In I2C-bus mode, the modulation mode is selected using an I2C-bus command.
• AD modulation mode: the bridge halves switch in opposite phase.
• BD modulation mode: the bridge halves switch in phase but the input signal for the
modulators is inverted.
Figure 10 and Figure 11 show simplified representations of AD and BD modulation.
+V
+V
P
P
INxP
OUTP OUTN
INxN
AD
BD
001aai778
Fig 10. AD/BD modulation switching circuit
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
12 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
INxP
OUTxP
001aai779
a. Bridge half 1
INxN
OUTxN
001aai780
b. Bridge half 2 switched in the opposite phase to bridge half 1
Fig 11. AD modulation
INxP
OUTxP
OUTxP, OUTxN
001aai781
a. Phase switching cycle
INxN
OUTxN
001aai782
b. Inverted signal to the modulator
Fig 12. BD modulation
8.4.2 Phase staggering (Slave mode)
In Slave mode with phase lock operation enabled, a phase shift with respect to the
incoming clock signal can be selected to distribute the switching moments over time. In
non-I2C-bus mode, 1⁄2 π phase shift can be programmed using pin MOD. In I2C-bus mode,
five different phase shifts (1⁄4 π, 1⁄3 π, 1⁄2 π, 2⁄3 π, 3⁄4 π) can be selected using the I2C-bus
bits (IB3[D1:D3]). See Table 8 for selection of the phase shift in non-I2C-bus mode with pin
MOD. An additional capacitor must be connected to pin SSM when 1⁄4 π phase shift is
used (see Figure 9). An example of using 1⁄2 π phase shift for BD modulation is shown in
Figure 13.
TDF8599_2
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TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
OUT1P
OUT1N
OUT2P
OUT2N
phase
0
master
π
OUT1P
OUT1N
OUT2P
OUT2N
1
2
π
slave
2
3
π
001aai783
Fig 13. Master and slave operation with 1⁄2 π phase shift
8.4.3 Parallel mode
In Parallel mode; the two output stages operate in parallel to enlarge the drive capability.
The inputs and outputs for Parallel mode must be connected on the Printed-Circuit Board
(PCB) as shown in Figure 14. The parallel connection can be made after the output filter,
as shown in Figure 14 or directly to the device output pins (OUTxP and OUTxN).
IN1P
IN1N
IN2N
IN2P
MOD
OUT1N
OUT1P
+
−
−
TDF8599
OUT2P
OUT2N
+
R
MOD
001aai784
Fig 14. Parallel mode
In Parallel mode, the channel 1 I2C-bus bits can be programmed using the I2C-bus.
However, CLIP detection must be deactivated by disabling it for both channel 1 and
channel 2.
8.5 Protection
The TDF8599 includes a range of built-in protection functions. How the TDF8599
manages the various possible fault conditions for each protection is described in the
following sections:
TDF8599_2
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TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Table 9.
Overview of protection types
Protection type
Thermal foldback
Overtemperature
Overcurrent
Reference
Section 8.5.1
Section 8.5.2
Section 8.5.3
Section 8.5.4
Section 8.5.5
Section 8.5.6
Section 8.5.6
Window
DC Offset
Undervoltage
Overvoltage
8.5.1 Thermal foldback
Thermal Foldback Protection (TFP) is activated when the average junction temperature
exceeds the threshold level (145 °C). TFP decreases amplifier gain such that the
combination of power dissipation and Rth(j-a) create a junction temperature around the
threshold level. The device will not completely switch off but remains operational at the
lower output power levels. If the average junction temperature continues to increase, a
second built-in temperature protection threshold level shuts down the amplifier completely.
8.5.2 Overtemperature protection
If the average junction temperature Tj > 160 °C, OverTemperature Protection (OTP) is
activated and the power stage shuts down immediately.
8.5.3 Overcurrent protection
OverCurrent Protection (OCP) is activated when the output current exceeds the maximum
output current of 8 A. OCP regulates the output voltage such that the maximum output
current is limited to 8 A. The amplifier outputs keep switching and the amplifier is NOT
shutdown completely. This is called current limiting.
OCP also detects when the loudspeaker terminals are short circuited or one of the
amplifier’s demodulated outputs is short circuited to one of the supply lines. In either case,
the shorted channel(s) are switched off.
The amplifier can distinguish between loudspeaker impedance drops and a low-ohmic
short across the load or one of the supply lines. This impedance threshold depends on the
supply voltage used. When a short is made across the load causing the impedance to
drop below the threshold level, the shorted channel(s) are switched off. They try to restart
every 50 ms. If the short circuit condition is still present after 50 ms, the cycle repeats. The
average power dissipation will be low because of this reduced duty cycle.
When a channel is switched off due to a short circuit on one of the supply lines, Window
Protection (WP) is activated. WP ensures the amplifier does not start-up after 50 ms until
the supply line short circuit is removed.
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TDF8599
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I2C-bus controlled dual channel class-D power amplifier
8.5.4 Window protection
Window Protection (WP) checks the PWM output voltage before switching from Standby
mode to Mute mode (with both outputs switching) and is activated as follows:
• During the start-up sequence:
– When the TDF8599 is switched from standby to mute (td(stb-mute)). When a short
circuit on one of the output terminals (i.e. between VP or GND) is detected, the
start-up procedure is interrupted and the TDF8599 waits for open circuit outputs.
No large currents flow in the event of a short circuit to the supply lines because the
check is performed before the power stages are enabled.
• During operation:
–
A short to one of the supply lines activates OCP causing the amplifier channel to
shutdown. After 50 ms the amplifier channel restarts and WP is activated.
However, the corresponding amplifier channel will not start-up until the supply line
short circuit has been removed.
8.5.5 DC offset protection
DC offset Protection (DCP) is activated when the DC content in the demodulated output
voltage exceeds a set threshold (typically 2 V). DCP is active in both Mute mode and
Operating mode. Figure 15 shows how false triggering of the DCP by low frequencies in
the audio signal is prevented using the external capacitor (CF) to generate a cut-off
frequency.
OUT1P
OUT1N
OUT2P
OUT2N
V
ref
50 kΩ
V to I
V to I
IB1[D6]
IB2[D6]
DCP
C
F
DIAG
IB1[D7]
S4
DB1[D2]
S
Q
IB2[D7]
S3
switch off channels
001aai785
Fig 15. DC offset protection and diagnostic output
TDF8599_2
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Product data sheet
Rev. 02 — 30 July 2009
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TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
In I2C-bus mode, DC offsets generate a voltage shift around the bias voltage. When the
voltage shift exceeds threshold values, the offset alarm bit DB1[D2] is set and if bit
IB1[D7] is not set, diagnostic information is also given. Any detected offset shuts down
both channels when bit IB2[D7] is not set. To restart the TDF8599 in I2C-bus mode, pin
EN must be toggled or DCP disabled by connecting pin DCP to pin AGND.
In non-I2C-bus mode, when an offset is detected, DCP always gives diagnostic
information on pin DIAG and shuts down both channels.
Connecting a capacitor between pins DCP and AGND enables DC offset protection.
Connecting pin DCP to pin AGND disables DCP in both I2C-bus and non-I2C-bus mode.
8.5.6 Supply voltages
UnderVoltage Protection (UVP) is activated when the supply voltage drops below the UVP
threshold (typically 7.5 V). UVP triggers the UVP circuit causing the system to first mute
and then stop switching. When the supply voltage rises above the threshold level, the
system restarts.
OverVoltage Protection (OVP) is activated when the supply voltage exceeds the OVP
threshold (typically 27 V). The OVP (or load dump) circuit is activated and the power
stages are shutdown.
An overview of all protection circuits and the amplifier states is given in Table 10.
8.5.7 Overview of protection circuits and amplifier states
Table 10. Overview of TDF8599 protection circuits and amplifier states
Protection circuit name
Amplifier state
Complete
shutdown
Channel
shutdown
Restart[1]
TFP
OTP
OCP
WP
N[2]
N[2]
Y[3]
Y[3]
Y[4]
Y
Y
N
N
Y
N
Y
DCP
UVP
OVP
Y
N
N[5]
Y[6]
Y
Y
N
Y
N
[1] When fault is removed.
[2] Amplifier gain depends on the junction temperature and size of the heat sink.
[3] TFP influences restart timing depending on heat sink size.
[4] Shorted load causes a restart of the channel every 50 ms.
[5] Latched protection is reset by toggling pin EN or by disabling DCP in I2C-bus mode.
[6] In I2C-bus mode deep supply voltage drops will cause a Power-On Reset (POR). The restart requires an
I2C-bus command.
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I2C-bus controlled dual channel class-D power amplifier
8.6 Diagnostic output
8.6.1 Diagnostic table
The diagnostic information for I2C-bus mode and non-I2C-bus mode is shown in Table 11.
The instruction bitmap and data bytes are described in Table 14 and Table 15.
Pins DIAG and CLIP have an open-drain output which must have an external pull-up
resistor connected to an external voltage. Pins CLIP and DIAG can show both fixed and
I2C-bus selectable information.
Pin DIAG goes LOW when a short circuit to one of the amplifier outputs occurs. The
microprocessor reads the failure information using the I2C-bus. The I2C-bus bits are set
for a short circuit. These bits can be reset with the I2C-bus read command.
Even after the short has been removed, the microprocessor knows what was wrong after
reading the I2C-bus. In principle, during a single I2C-bus read command, the old
information is read. To read the current information, two read commands must be sent,
one after another.
When selected, pin DIAG gives the current diagnostic information. Pin DIAG is released
instantly when the failure is removed, independent of the I2C-bus latches.
Table 11. Available data on pins DIAG and CLIP
Diagnostic
I2C-bus mode
Non-I2C-bus mode
Pin DIAG Pin CLIP Pin DIAG
Pin CLIP
no
Power-on reset
UVP or OVP
Clip detection
Temperature pre-warning
OCP/WP
yes
yes
no
no
no
yes
yes
no
selectable no
selectable no
yes
yes
no
no
yes
no
yes
DCP
selectable no
yes no
yes
yes
no
OTP
no
When OCP is triggered, the open-drain DIAG output is activated. The diagnostic output
signal during different short circuit conditions is illustrated in Figure 16.
shorted load
short to GND or V line
P
AMPLIFIER
RESTART
NO
RESTART
pull up V
AGND = 0 V
≈50 ms ≈50 ms ≈50 ms
001aai786
Fig 16. Diagnostic output for short circuit conditions
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TDF8599
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I2C-bus controlled dual channel class-D power amplifier
8.6.2 Load identification (I2C-bus mode only)
8.6.2.1 DC load detection
DC load detection is only available in I2C-bus mode and is controlled using bit IB2[D2].
The default setting is logic 0 for bit IB2[D2] which disables DC load detection. DC load
detection is enabled when bit IB2[D2] = 1. Load detection takes place before the class-D
amplifier output stage starts switching in Mute mode and the start-up time from Standby
mode to Mute mode is increased by tdet(DCload) (see Figure 17).
V
P
DRIVER
HIGH
B
OUTN
PWM
CONTROL
DRIVER
LOW
PGND1
R
L
V
P
DRIVER
HIGH
OUTP
PWM
CONTROL
DRIVER
LOW
PGND2
001aai787
Fig 17. DC load detection circuit
out (V)
out−
out+
t (s)
t
t
det(DCload)
d(stb-mute)
001aai788
Fig 18. DC load detection procedure
The capacitor connected to pin SEL_MUTE (see Figure 4 on page 7) is used to create an
inaudible current test pulse, drawn from the positive amplifier output. The diagnostic
‘speaker load’ (or ‘open load’), based on the voltage difference between pins OUTxP and
OUTxN is shown in Figure 19.
SPEAKER LOAD
OPEN LOAD
0 Ω
25 Ω 350 Ω
001aai789
Fig 19. DC load detection limits
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TDF8599
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I2C-bus controlled dual channel class-D power amplifier
Remark: DC load detection identifies a short circuited speaker as a valid speaker load.
OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,
performs diagnostics on shorted loads. However, the diagnostics are performed after the
DC load detection cycle has finished and once the amplifier is in Operating mode.
The result of the DC load detection is stored in bits DB1[D4] and DB2[D4].
Table 12. Interpretation of DC load detection bits
DC load bits DB1[D4] and DB2[D4]
OCP bits DB1[D3] and DB2[D3] Description
0
0
1
0
1
0
speaker load
shorted load
open load
Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must
be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load
detection is interrupted by a sudden large change in supply voltage (triggered by UVP or
OVP) or if the amplifier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC
load detection enable bit IB2[D2] must be reset after the DC load protection cycle to
release any amplifier hang-up. Once the DC load detection cycle has finished, DC load
detection can be restarted by toggling the DC load detection enable bit IB2[D2]. However,
this can only be used if both amplifier channels have not been enabled with bit IB1[D1] or
bit IB2[D1]. See Section 8.6.2.2 “Recommended start-up sequence with DC load
detection enabled” for detailed information.
8.6.2.2 Recommended start-up sequence with DC load detection enabled
The flow diagram (Figure 20) illustrates the TDF8599’s ability to perform a DC load
detection without starting the amplifiers. After a DC load detection cycle finishes without
setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is
toggled).
To limit the maximum number of DC load detection cycle loops, a counter and limit have
been added. The loop exits after the predefined number of cycles (COUNTMAX), if the
DC load detection cycle finishes with an invalid detection.
Depending on the application needs, the invalid DC load detection cycle can be handled
as follows:
• the amplifier can be started without DC load detection
• the DC load detection loop can be executed again
A valid DC load detection cycle does not affect the normal amplifier start-up timing.
TDF8599_2
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Product data sheet
Rev. 02 — 30 July 2009
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TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
2
I C-bus TX
IB1[D0] = 1
IB2[D2] = 1
IB1[D1] = 1
IB2[D1] = 1
startup
enable DC load
disable channel 1
disable channel 2
COUNT = 0
2
I C-bus TX
WAIT DC load
IB1[D0] = 1
IB2[D2] = 1
IB1[D1] = 1
IB2[D1] = 1
startup
enable DC load
disable channel 1
disable channel 2
restart
DC load
2
I C-bus RX
NO
DB1[D4] = 1
DB2[D4] = 1
DB1[D6] = 1
channel 1 open load
channel 2 open load
DC load valid
YES
COUNT ≤ COUNTMAX
ERROR HANDLING
start amplifier
anyway
COUNT = COUNT + 1
2
I C-bus TX
IB1[D0] = 1
IB2[D2] = 0
IB1[D1] = 1
IB2[D1] = 1
startup
disable DC load
disable channel 1
disable channel 2
NO
DB1[D6] = 1
DC load valid
YES
2
I C-bus TX
IB1[D0] = 1
startup
IB2[D2] = 0
IB1[D1] = 0
IB2[D1] = 0
disable DC load
enable channel 1
enable channel 2
001aaj061
Fig 20. Recommended start-up sequence with DC load detection enabled
8.6.2.3 AC load detection
AC load detection is only available in I2C-bus mode and is controlled using bit IB3[D4].
The default setting for bit IB3[D4] = 0 disables AC load detection. When AC load detection
is enabled (bit IB3[D4] = 1), the amplifier load current is measured and compared with a
reference level. Pin CLIP is activated when this threshold is reached. Using this
information, AC load detection can be performed using a predetermined input signal
frequency and level. The frequency and signal level should be chosen so that the load
current exceeds the programmed current threshold when the AC coupled load (tweeter) is
present.
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Product data sheet
Rev. 02 — 30 July 2009
21 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
8.6.2.4 CLIP detection
CLIP detection gives information for clip levels ≥ 1 %. Pin CLIP is used as the output for
the clip detection circuitry on both channel 1 and channel 2. Setting either bit IB1[D5] or bit
IB2[D5] to logic 0 defines which channel reports clip information on the CLIP pin.
In Parallel mode, disabling clip detection on both channels requires both bits to be set to
bit IB1[D5] = 1 and bit IB2[D5] = 1.
8.6.3 Start-up and shutdown sequence
To prevent switch on or switch off ‘pop noise’, a capacitor (CSVRR) connected to pin SVRR
is used to smooth start-up and shutdown. During start-up and shutdown, the output
voltage tracks the voltage on pin SVRR. Increasing CSVRR results in a longer start-up and
shutdown time. Enhanced pop-noise performance is achieved by muting the amplifier until
the SVRR voltage reaches its final value and the outputs start switching. The value of
capacitor connected to pin SEL_MUTE (CON) determines the unmute and mute timing.
The voltage on pin SEL_MUTE determines the amplifier gain. Increasing CON increases
the unmute and mute times. In addition, a larger CON value increases the DC load
detection cycle.
When the amplifier is switched off with an I2C-bus command or by pulling pin EN LOW, the
amplifier is first muted and then capacitor (CSVRR) is discharged.
In Slave mode, the device enters the off state immediately after capacitor (CSVRR) is
discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of
approximately 50 ms to allow slave devices to enter the off state.
When an external clock is connected to pin OSCIO (in Slave mode), the clock must
remain active during the shutdown sequence for delay (td(1)) to ensure that the slaved
TDF8599 devices are able to enter the off state.
TDF8599_2
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Product data sheet
Rev. 02 — 30 July 2009
22 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
V
DDA
DIAG
(1)
t
d
EN
ACGND
(3)
t
d
IB1[D0] and
IB2[D0] = 0
t
d(mute-fgain)
mute delay
(2)
t
d
SEL_MUTE
SVRR
t
t
t
det(DCload)
wake
d(stb-mute)
OUTn
001aai790
(1) Shutdown hold delay.
(2) Master mode shutdown delay.
(3) Shutdown delay.
Fig 21. Start-up and shutdown timing in I2C-bus mode with DC load detection
TDF8599_2
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Product data sheet
Rev. 02 — 30 July 2009
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TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
V
DDA
DIAG
(2)
(1)
t
t
d
d
EN
ACGND
t
d(mute-fgain)
(3)
SEL_MUTE
SVRR
t
d
t
d(stb-mute)
OUTn
001aai791
(1) Shutdown hold delay.
(2) Shutdown delay.
(3) Master mode shutdown delay.
Fig 22. Start-up and shutdown timing in non-I2C-bus mode
9. I2C-bus specification
TDF8599 address with hardware address select.
Table 13. TDF8599 address using an external resistor
[1]
RADS
A6 A5 A4 A3 A2 A1 A0 R/W
Open
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0 = Write to TDF8599
1 = Read from TDF8599
100 kΩ to pin AGND
33 kΩ to pin AGND
13 kΩ to pin AGND
4.7 kΩ to pin AGND
Ground
non-I2C-bus mode select
[1] Required external resistor accuracy is 1 %.
The information on pin ADS is latched when the amplifier starts switching.
TDF8599_2
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Product data sheet
Rev. 02 — 30 July 2009
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TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
SCL
SDA
SCL
SDA
(1)
(2)
Mµp
Mµp
START
STOP
(1)
SLAVE
SLAVE
001aai792
001aai793
(1) When SCL is HIGH, SDA changes to form the start or
stop condition.
(1) SDA is allowed to change.
(2) All data bits must be valid on the positive edges of SCL.
Fig 23. I2C-bus start and stop conditions
Fig 24. Data bits sent from Master microprocessor
(Mµp)
SCL
SDA
1
2
7
8
9
1
2
7
8
9
MSB
MSB − 1
LSB + 1
ACK
MSB
MSB − 1
LSB + 1
LSB
ACK
Mµp
START
ADDRESS
WRITE
WRITE DATA
STOP
(1)
ACK
SLAVE
ACK
001aai794
(1) To stop the transfer after the last acknowledge a stop condition must be generated.
Fig 25. I2C-bus write
SCL
SDA
1
2
7
8
9
1
2
7
8
9
MSB
MSB − 1
LSB + 1
ACK
MSB
MSB − 1
LSB + 1
LSB
(1)
Mµp START
ADDRESS
READ
ACK
STOP
SLAVE
ACKNOWLEDGE
READ DATA
001aai795
(1) To stop the transfer, the last byte must not be acknowledged (SDA is HIGH) and a stop condition must be generated.
Fig 26. I2C-bus read
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TDF8599
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I2C-bus controlled dual channel class-D power amplifier
9.1 Instruction bytes
If R/W bit = 0, the TDF8599 expects three instruction bytes: IB1, IB2 and IB3. After a
power-on reset, all unspecified instruction bits must be set to zero’.
Table 14. Instruction byte descriptions
Bit
D7
D6
D5
D4
D3
Value Description
Instruction byte IB1
Instruction byte IB2
Instruction byte IB3
0
1
0
1
0
1
0
1
0
offset detection on pin DIAG
no offset detection on pin DIAG
channel 1 offset monitoring on
channel 1 offset monitoring off
channel 1 clip detect on pin CLIP
offset protection on
-
-
-
-
-
offset protection off
channel 2 offset monitoring on
channel 2 offset monitoring off
channel 2 clip detect on pin CLIP
channel 1 no clip detect on pin CLIP channel 2 no clip detect on pin CLIP -
disable frequency hopping
enable frequency hopping[1]
oscillator frequency as set with
thermal pre-warning on pin CLIP
disable AC load detection
no thermal pre warning on pin CLIP enable AC load detection
temperature pre-warning at 140 °C oscillator phase shift bits
Rosc − 10 %
IB3[D3] to IB3[D1][2]
1
oscillator frequency as set with
temperature pre-warning at 120 °C
Rosc + 10 %
D2
D1
D0
0
1
0
1
0
1
-
DC-load detection disabled
DC-load detection enabled
channel 2 enabled
-
channel 1 enabled
channel 1 disabled
channel 2 disabled
TDF8599 in Standby mode
all channels operating
all channels muted
AD modulation
BD modulation
TDF8599 in Mute or Operating
modes[3]
[1] See Section 8.3.3 on page 10 for information on IB1[D3] and IB1[D4].
[2] See Table 15 “Phase shift bit settings” for information.
[3] See Table 4 for information on IB1[D0] and IB2[D0].
Table 15. Phase shift bit settings
D3
0
D2
0
D1
0
Phase
0
0
0
1
1⁄4 π
1⁄3 π
1⁄2 π
2⁄3 π
3⁄4 π
0
1
0
0
1
1
1
0
0
1
0
1
TDF8599_2
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TDF8599
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I2C-bus controlled dual channel class-D power amplifier
9.2 Data bytes
If R/W = 1, the TDF8599 sends two data bytes to the microprocessor (DB1 and DB2). All
short diagnostic and offset protection bits are latched. In addition, all bits are reset after a
read operation except the DC load detection bits (DBx[D4], DB1[D6]). The default setting
for all bits is logic 0.
In Parallel mode, the diagnostic information is stored in byte DB1.
Table 16. Description of data bytes
Bit
Value DB1 channel 1
DB2 channel 2
D7
0
1
at least 1 instruction bit set to logic 1 below maximum temperature
all instruction bits are set to logic 0
maximum temperature protection
activated
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
invalid DC load data
valid DC load data
no temperature warning
temperature pre-warning active
no undervoltage
no overvoltage
overvoltage protection active
speaker load channel 1
open load channel 1
no shorted load channel 1
shorted load channel 1
no offset
undervoltage protection active
speaker load channel 2
open load channel 2
no shorted load channel 2
shorted load channel 2
reserved
offset detected
reserved
no short to VP channel 1
short to VP channel 1
no short to ground channel 1
short to ground channel 1
no short to VP channel 2
short to VP channel 2
no short to ground channel 2
short to ground channel 2
Data byte DB1[D7] indicates whether the instruction bits have been set to logic 0. In
principle, DB1[D7] is set after a POR or when all the instruction bits are programmed to
logic 0. Pin DIAG is driven HIGH when bit DB1[D7] = 1.
TDF8599_2
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Product data sheet
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TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
10. Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Operating mode
off state
Min
Max Unit
VP
supply voltage
-
18
V
V
V
[1]
−1
-
+50
50
load dump; duration
50 ms, tr > 2.5 ms
[2]
[2]
IORM
repetitive peak output
current
maximum output current
limiting
8
-
A
IOM
Vi
peak output current
input voltage
maximum; non-repetitive
-
12
A
V
pins SCL, SDA, ADS,
MOD, SSM, OSCIO, EN
and SEL_MUTE
0
5.5
Vo
output voltage
pins DIAG and CLIP
0
-
10
V
RESR
equivalent series resistance between pins VP and
PGNDn
350
mΩ
Tj
junction temperature
storage temperature
ambient temperature
-
150
°C
Tstg
Tamb
VESD
−55
−40
+150 °C
+85
°C
[3]
[4]
electrostatic discharge
voltage
HBM
C = 100 pF;
Rs = 1.5 kΩ
CDM
-
2000
V
non-corner pins
corner pins
-
500
750
VP
V
V
V
-
[5]
V(prot)
protection voltage
AC and DC short circuit
voltage of output pins
across load and to
0
supply and ground
[1] Floating condition assumed for outputs.
[2] Current limiting concept.
[3] Human Body Model (HBM).
[4] Charged-Device Model (CDM).
[5] The output pins are defined as the output pins of the filter connected between the TDF8599 output pins and
the load.
11. Thermal characteristics
Table 18. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction in free air
to ambient
35
K/W
Rth(j-c)
thermal resistance from junction
to case
1
K/W
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
28 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
12. Static characteristics
Table 19. Static characteristics
VP = 14.4 V; fosc = 320 kHz; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol
Supply
VP
Parameter
Conditions
Min Typ Max Unit
supply voltage
8
-
14.4 18
V
IP
supply current
off state; Tj ≤ 85 °C; VP = 14.4 V
2
10
µA
µA
mA
Istb
standby current
total quiescent current
voltage on pin EN < 0.8 V
-
-
10
Iq(tot)
Operating mode; no load,
-
90
120
snubbers and filter connected
Series resistance output switches
RDSon
drain-source on-state resistance power switch;
Tj = 25 °C
-
-
130
170
-
-
mΩ
mΩ
Tj = 100 °C
I2C-bus interface: pins SCL and SDA
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
0
-
-
-
1.5
5.5
0.4
V
V
V
VIH
VOL
2.3
0
pin SDA; Iload = 5 mA
Address, phase shift and modulation mode select: pins ADS and MOD
[1]
[1]
Vi
Ii
input voltage
input current
pins not connected
pins shorted to GND
1.5
80
2
2.7
V
120 160
µA
Enable and SEL_MUTE input: pins EN and SEL_MUTE
Vi
input voltage
pin EN; off state
pin EN; Standby mode; I2C-bus
mode
0
2
-
-
0.8
5
V
V
pin EN; Mute mode or Operating
mode; non-I2C-bus mode
2
0
3
-
-
-
5
V
V
V
pin SEL_MUTE; Mute mode;
voltage on pin EN > 2 V
0.8
5
pin SEL_MUTE; Operating mode;
voltage on pin EN > 2 V
Ii
input current
pin EN; 2.5 V
-
-
-
-
5
µA
µA
pin SEL_MUTE; Operating mode;
0.8 V
50
Diagnostic output
THDclip
total harmonic distortion clip
detection level
-
0.2
-
%
V
[2]
Vth(offset)
VOL
threshold voltage for offset
detection
1
-
2
-
3
LOW-level output voltage
DIAG or CLIP pins activated;
Io = 1 mA
0.3
50
V
IL
leakage current
DIAG and CLIP pins; diagnostic
not activated
-
-
µA
Audio inputs; pins IN1N, IN1P, IN2N and IN2P
Vi
input voltage
-
2.45 -
V
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
29 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Table 19. Static characteristics …continued
VP = 14.4 V; fosc = 320 kHz; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol Parameter Conditions
SVRR voltage and ACGND input bias voltage in Mute and Operating modes
Min Typ Max Unit
Vref
reference voltage
input ACGND pin
2
2.45 3
V
V
half supply reference SVRR pin
6.9 7.2 7.5
Amplifier outputs; pins OUT1N, OUT1P, OUT2N and OUT2P
VO(offset)
output offset voltage
BTL; Mute mode
-
-
-
-
25
70
mV
mV
[3][5]
BTL; Operating mode
Stabilizer output; pins VSTAB1 and VSTAB2
Vo output voltage
stabilizer output in Mute mode and
Operating mode
8
10
12
V
Voltage protections
V(prot)
protection voltage
undervoltage; amplifier is muted
6.8 7.2
26.2 27
8
-
V
V
overvoltage; load dump protection
is activated
VP that a POR occurs at
3
8
3.7 4.4
V
A
Current protection
IO(ocp)
overcurrent protection output
current
current limit
-
-
Temperature protection
Tprot
protection temperature
155
140
-
-
160
150
°C
°C
Tact(th_fold)
thermal foldback activation
temperature
gain = −1 dB
Tj(AV)(warn1)
Tj(AV)(warn2)
average junction temperature for IB2[D3] = 0; non-I2C-bus mode
pre-warning 1
-
-
140 150
120 130
°C
°C
average junction temperature for IB2[D3] = 1
pre-warning 2
DC load detection levels: I2C-bus mode only[6]
Zth(load)
load detection threshold
impedance
for normal speaker; DB1[D4] = 0;
DB2[D4] = 0
-
-
-
25
-
Ω
Ω
Zth(open)
open load detection threshold
impedance
DB1[D4] = 1; DB2[D4] = 1
350
AC load detection levels: I2C-bus mode only
Ith(o)det(load)AC
AC load detection output
threshold current
700 900 1100 mA
Start-up/shut-down/mute timing
[4]
[4]
twake
wake-up time
on pin EN before first I2C-bus
transmission is recognized
-
-
500
µs
tdet(DCload)
td(stb-mute)
DC load detection time
CON = 470 nF
-
-
250
140
-
-
ms
ms
delay time from standby to mute measured from amplifier enabling
to start of mute release (no DC
load detection); CSVRR = 47 µF
C
ON = 470 nF
[5]
td(mute-fgain)
mute to full gain delay time
CON = 470 nF
-
15
-
ms
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
30 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Table 19. Static characteristics …continued
VP = 14.4 V; fosc = 320 kHz; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Unit
td
delay time
shutdown delay time from EN pin
LOW to SVRR LOW;
SVRR < 0.1 V; CSVRR = 47 µF
145 260 425
ms
ms
ms
shutdown delay time from pin EN
LOW to ACGND LOW; voltage on
pin ACGND < 0.1 V; Master mode
-
-
400
50
-
-
delay in Master mode to allow
slaved devices to shutdown
fosc = 320 kHz
Speaker load impedance
RL load resistance
stereo mode
parallel mode
1.6
0.8
4
-
-
-
Ω
Ω
[1] Required resistor accuracy for pins ADS and MOD is 1 %; see Section 9 on page 24.
[2] Maximum leakage current from DCP pin to ground = 3 µA.
[3] DC output offset voltage is applied to the output gradually during the transition between Mute mode and Operating mode.
[4] I2C-bus mode only.
[5] The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin.
[6] The DC load valid bit DB1[D6] must be used; Section 8.6.2.1 on page 19. The DC load enable bit IB2[D2] must be reset after each load
detection cycle to prevent amplifier hang-up incidents.
[7] The output offset values can be either positive or negative. The Vth(offset) limit values (excluding Typ) are the valid absolute values.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
31 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
12.1 Switching characteristics
Table 20. Switching characteristics
VP = 14.4 V; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Internal oscillator
fosc
oscillator frequency
external clock frequency;
-
320
-
-
kHz
kHz
R
osc = 39 kΩ
internal fixed frequency and Spread
spectrum mode frequency based on
the resistor value connected to pin
OSCSET for the master setting
300
450
Master/slave setting (OSCIO pin)
Rosc
oscillator resistance
resistor value on pin OSCSET;
master setting
26
39
49
kΩ
VOL
VOH
VIL
LOW-level output voltage
HIGH-level output voltage
LOW-level input voltage
HIGH-level input voltage
tracking frequency
output
-
-
-
-
-
-
-
0.8
-
V
output
4
V
input
-
0.8
-
V
VIH
input
4
V
ftrack
Nslave
PLL enabled
driven by one master
300
-
500
12
kHz
number of slaves
Spread spectrum mode setting
∆fosc
oscillator frequency variation
between maximum and minimum
values; Spread spectrum mode
activated
-
-
10
7
-
-
%
fsw
switching frequency
Spread spectrum mode activated;
Hz
C
SSM = 1 µF
Frequency hopping
fosc(int)
internal oscillator frequency
change positive; IB1[D4] = 1;
IB1[D3] = 1
-
-
fosc + 10 % -
fosc − 10 % -
kHz
kHz
change negative; IB1[D4] = 1;
IB1[D3] = 0
Timing
tr
rise time
PWM output; Io = 0 A
PWM output; Io = 0 A
Io = 0 A
-
-
-
10
10
80
-
-
-
ns
ns
ns
tf
fall time
tw(min)
minimum pulse width
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
32 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
13. Dynamic characteristics
Table 21. Dynamic characteristics
VP = 14.4 V; RL = 4 Ω; fi = 1 kHz; fosc = 320 kHz; Rs(L) < 0.04 Ω[1]; −40 °C < Tamb < +85 °C; Stereo mode; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2]
Po
output power
Stereo mode;
THD = 1 %; RL = 4 Ω
THD = 10 %; RL = 4 Ω
square wave (EIAJ); RL = 4 Ω
THD = 1 %; RL = 2 Ω
THD = 10 %; RL = 2 Ω
square wave (EIAJ); RL = 2 Ω
Parallel mode
18
24
-
20
26
40
32
43
70
-
-
-
-
-
-
W
W
W
W
W
W
29
39
-
[2]
THD = 10 %; RL = 1 Ω
fi = 1 kHz; Po = 1 W
fi = 10 kHz; Po = 1 W
-
85
-
W
%
[3]
[3]
THD
total harmonic distortion
-
0.02 0.1
0.02 0.1
-
%
Gv(cl)
αcs
closed-loop voltage gain
channel separation
25
-
26
70
27
-
dB
dB
fi = 1 kHz; Po = 1 W
SVRR
supply voltage rejection ratio Operating mode
[4]
[4]
fripple = 100 Hz
fripple = 1 kHz
Mute mode
-
-
70
70
-
-
dB
dB
[4]
[4]
fripple = 1 kHz
-
70
-
dB
off state and Standby mode
fripple = 1 kHz
-
90
-
dB
|Zi(dif)
|
differential input impedance
output noise voltage
60
100
150
kΩ
Vn(o)
Operating mode
BD mode
[5]
[5]
-
-
60
77
µV
µV
AD mode
100
140
Mute mode
BD mode
[6]
[6]
-
25
85
0
32
µV
µV
dB
dB
dB
%
AD mode
-
110
αbal(ch)
αmute
CMRR
ηpo
channel balance
mute attenuation
-
1
-
[7]
66
65
-
-
common mode rejection ratio Vi(CM) = 1 V RMS
output power efficiency Po = 20 W
80
90
-
-
[1] Rs(L) is the sum of the inductor series resistance from the low-pass LC filter in the application together with all resistance from PCB
traces or wiring between the output pin of the TDF8599 and the inductor to the measurement point. LC filter dimensioning is L = 10 µH,
C = 1 µF for 2 Ω load and L = 5 µH, C = 2.2 µF for 4 Ω load.
[2] Output power is measured indirectly based on RDSon measurement.
[3] Total harmonic distortion is measured at the bandwidth of 22 Hz to 20 kHz, AES brick wall. The maximum limit is guaranteed but may
not be 100 % tested.
[4] Vripple = Vripple(max) = 2 V p-p; Rs = 0 Ω.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
33 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
[5] B = 22 Hz to 20 kHz, AES brick wall, Rs = 0 Ω.
[6] B = 22 Hz to 20 kHz, AES brick wall, independent of Rs.
[7] Vi = Vi(max) = 0.5 V RMS.
14. Application information
14.1 Output power estimation (Stereo mode)
The output power, just before clipping, can be estimated using Equation 5:
2
RL
f osc
× 1 – tw(min)
×
× V p
-----------------------------------------------------
---------
RL + 2 × (RDSon + Rs)
2
Po
=
[W]
(5)
---------------------------------------------------------------------------------------------------------------------------------------
2 × RL
Where,
• VP = supply voltage (V)
• RL = load impedance (Ω)
• RDSon = on resistance of power switch (Ω)
• Rs = series resistance of the output inductor (Ω)
• tw(min) = minimum pulse width(s) depending on output current (s)
• fosc = oscillator frequency in Hz (typically 320 kHz)
The output power at 10 % THD can be estimated by: Po(2) = 1.25 × Po(1) where
Po(1) = 0.5 % and Po(2) = 10 %.
Figure 27 and Figure 28 show the estimated output power at THD = 0.5 % and
THD = 10 % as a function of supply voltage for different load impedances in stereo mode.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
34 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aai796
001aai797
80
80
P
P
o
o
(W)
(W)
60
60
(1)
(2)
40
20
0
40
20
0
(1)
(2)
(3)
(3)
8
10
12
14
16
18
8
10
12
14
16
18
V
(V)
V (V)
P
P
THD = 0.5 %.
THD = 10 %.
(1) RDSon = 0.12 Ω (at Tj = 25 °C), Rs = 0.025 Ω,
(1) RDSon = 0.12 Ω (at Tj = 25 °C), Rs = 0.025 Ω,
tw(min) = 130 ns and IO(ocp) = 8 A (minimum).
tw(min) = 130 ns and IO(ocp) = 8 A (minimum).
(2) RL = 1 Ω.
(3) RL = 2 Ω.
(4) RL = 4 Ω.
(2) RL = 1 Ω.
(3) RL = 2 Ω.
(4) RL = 4 Ω.
Fig 27. Po as a function of VP in stereo mode with
THD = 0.5 %
Fig 28. Po as a function of VP in stereo mode with
THD = 10 %
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
35 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
14.2 Output power estimation (Parallel mode)
Figure 29 and Figure 30 show the estimated output power at THD = 0.5 % and
THD = 10 % as a function of the supply voltage for different load impedances in parallel
mode.
001aai798
001aai799
(1)
160
160
P
P
o
o
(W)
(W)
120
120
(1)
80
40
0
80
40
0
(2)
(3)
(2)
(3)
8
10
12
14
16
18
8
10
12
14
16
18
V
(V)
V (V)
P
P
THD = 0.5 %.
THD = 10 %.
(1) RDSon = 0.06 Ω (at Tj = 25 °C), Rs = 0.0125 Ω,
(1) RDSon = 0.06 Ω (at Tj = 25 °C), Rs = 0.0125 Ω,
tw(min) = 130 ns and IO(ocp) = 16 A (minimum).
tw(min) = 130 ns and IO(ocp) = 16 A (minimum).
(2) RL = 1 Ω.
(3) RL = 2 Ω.
(4) RL = 4 Ω.
(2) RL = 1 Ω.
(3) RL = 2 Ω.
(4) RL = 4 Ω.
Fig 29. Po as a function of VP in parallel mode with
THD = 0.5 %
Fig 30. Po as a function of VP parallel mode with
THD = 10 %
14.3 Output current limiting
The peak output current is internally limited to 8 A maximum. During normal operation, the
output current should not exceed this threshold level otherwise the output signal will be
distorted. The peak output current can be estimated using Equation 6:
VP
I ≤
≤ 8 [A]
(6)
-----------------------------------------------------
o
RL + 2 × (RDSon + Rs)
• Io = output current (A)
• VP = supply voltage (V)
• RL = load impedance (Ω)
• RDSon = on-resistance of power switch (Ω)
• Rs = series resistance of output inductor (Ω)
Example: A 1 Ω speaker can be used with a supply voltage of 11 V before current limiting
is triggered.
Current limiting (clipping) avoids audio holes but can cause distortion similar to voltage
clipping. In Parallel mode, the output current is internally limited above 16 A.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
36 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
14.4 Speaker configuration and impedance
A flat-frequency response (due to a 2nd order Butterworth filter) is obtained by changing
the low-pass filter components (LLC, CLC) based on the speaker configuration and
impedance. Table 22 shows the required values.
Table 22. Filter component values
Load impedance (Ω)
LLC (µH)
CLC (µF)
1
2
4
2.5
5
4.4
2.2
1
10
Remark: When using a 1 Ω load impedance in Parallel mode, the outputs are shorted
after the low-pass filter switches two 2 Ω filters in parallel.
14.5 Heat sink requirements
In some applications, it is necessary to connect an external heat sink to the TDF8599.
Thermal foldback activates at Tj = 145 °C. The expression below shows the relationship
between the maximum power dissipation before activation of thermal foldback and the
total thermal resistance from junction to ambient;
T j(max) – T
Rth(j-a)
=
amb[K/W]
(7)
-----------------------------------
Pmax
Pmax is determined by the efficiency (η) of the TDF8599. The efficiency measured as a
function of output power is given in Figure 39. The power dissipation can be derived as a
function of output power (see Figure 32).
Example 1:
• VP = 14.4 V
• Po = 2 × 25 W into 4 Ω (THD = 10 % continuous)
• Tj(max) = 140 °C
• Tamb = 25 °C
• Pmax = 5.8 W (from Figure 40)
• The required Rth(j-a) = 115 °C / 5.8 W = 19 K/W
The total thermal resistance Rth(j-a) consists of: Rth(j-c) + Rth(c-h) + Rth(h-a)
Where:
• Thermal resistance from junction to case (Rth(j-c)) = 1.1 K/W
• Thermal resistance from case to heat sink (Rth(c-h)) = 0.5 K/W to 1 K/W (depending on
mounting)
• Thermal resistance from heat sink to ambient (Rth(h-a)) would then be
19 − (1.1 + 1) = 17 K/W.
If an audio signal has a crest factor of 10 (the ratio between peak power and average
power = 10 dB) then Tj will be much lower.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
37 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
Example 2:
• VP = 14.4 V
• Po = 2 × (25 W / 10) = 2 × 2.5 W into 4 Ω (audio with crest factor of 10)
• Tamb = 25 °C
• Pmax = 2.5 W (from Figure 40)
• Rth(j-a) = 19 K/W
• Tj(max) = 25 °C + (2.5 W × 19 K/W) = 72 °C
14.6 Curves measured in reference design
001aai800
001aai801
2
2
10
10
THD + N
(%)
THD + N
(%)
10
10
1
1
(1)
(1)
−1
−1
10
10
(2)
(3)
(2)
(3)
−2
−2
10
10
−3
−3
10
10
−1
2
−1
2
10
1
10
10
10
1
10
10
P
(W)
P (W)
o
o
(1) VP = 14.4 V; RL = 2 Ω at 6 kHz.
(2) VP = 14.4 V; RL = 2 Ω at 1 kHz.
(3) VP = 14.4 V, RL = 2 Ω at 100 Hz.
(1) VP = 14.4 V; RL = 4 Ω at 6 kHz.
(2) VP = 14.4 V; RL = 4 Ω at 1 kHz.
(3) VP = 14.4 V, RL = 4 Ω at 100 Hz.
Fig 31. THD + N as a function of output power with a
Fig 32. THD + N as a function of output power with a
2 Ω load
4 Ω load
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
38 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aai802
001aai803
1
1
THD + N
(%)
THD + N
(%)
−1
−1
10
10
(1)
(1)
−2
−2
(2)
10
10
10
(2)
−3
−3
10
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
f (Hz)
(1) VP = 14.4 V; RL = 2 Ω at 10 W.
(2) VP = 14.4 V; RL = 2 Ω at 1 W.
(1) VP = 14.4 V; RL = 4 Ω at 10 W.
(2) VP = 14.4 V; RL = 4 Ω at 1 W.
Fig 33. THD + N as a function of frequency with a 2 Ω
Fig 34. THD + N as a function of frequency with a 4 Ω
load
load
001aai804
001aai805
−60
−60
α
(dB)
α
(dB)
cs
cs
−70
−70
−80
−80
(1)
(1)
(2)
(2)
−90
−90
−100
−100
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
f (Hz)
Po = 1 W; VP = 14.4 V; RL = 2 Ω.
(1) Channel 1 to channel 2.
Po = 1 W; VP = 14.4 V; RL = 4 Ω.
(1) Channel 1 to channel 2.
(2) Channel 2 to channel 1.
(2) Channel 2 to channel 1.
Fig 35. Channel separation as a function of frequency
Fig 36. Channel separation as a function of frequency
with a 2 Ω load
with a 4 Ω load
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
39 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
001aai806
001aai807
−75
1.0
G
(dB)
0.8
CMRR
(dB)
0.6
0.4
0.2
0
−80
−85
−90
(2)
(1)
−0.2
(1)
(2)
−0.4
−0.6
−0.8
−1.0
−2
−1
2
2
3
4
5
10
10
1
10
10
10
10
10
10
10
f (kHz)
f (Hz)
Vi = 1 V; Ri = 0 Ω.
Vi = 100 mV RMS; Ri = 0 Ω.
(1) VP = 14.4 V; RL = 2 Ω.
(2) VP = 14.4 V; RL = 4 Ω.
(1) VP = 14.4 V; RL = 2 Ω.
(2) VP = 14.4 V; RL = 4 Ω.
Fig 37. CMRR as a function of frequency
Fig 38. Gain as a function of frequency
001aai808
001aai809
100
20
(2)
(1)
η
(%)
P
D
(W)
80
16
60
40
20
0
12
8
(1)
(2)
4
0
0
10
20
30
40
50
P
60
(W)
0
20
40
60
P (W)
o
o
(1) VP = 14.4 V; RL = 2 Ω at 1 kHz.
(2) VP = 14.4 V; RL = 4 Ω at 1 kHz.
(1) VP = 14.4 V; RL = 2 Ω at 1 kHz.
(2) VP = 14.4 V; RL = 4 Ω at 1 kHz.
Fig 39. Efficiency as a function of output power
Fig 40. Power dissipation as a function of total output
power
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
40 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
14.7 Typical application schematics
bead
bead
bead
V
V
V
P1
P2
PA
100 µF
35 V
100 µF
35 V
V
P
1000 µF
35 V
PGND1
GND
PGND2
C
C
C
C
IN1P
IN1N
IN2P
IN2N
470 nF
470 nF
470 nF
470 nF
GNDD/HW
IN1P
IN1N
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
IN1P
IN1N
100 nF
V
DDD
220 nF
VSTAB1
OUT1N
IN2P
IN2N
IN2P
IN2N
L
LC
OUT1N
15 nF
C
ACGND
100 nF
100 nF
10 Ω
C
LC
BOOT1N
ACGND
EN
22 Ω
V
P1
100 nF
V
P1
(1)
470 pF
470 pF
enable
V
PGND1
470 pF
P1
470 pF
SEL_MUTE
PGND1
(1)
mute/on
PGND1
22 Ω
470 nF
C
BOOT1P
OUT1P
SVRR
AGND
LC
10 Ω
10 Ω
100 nF
15 nF
47 µF
L
LC
OUT1P
100 nF
TDF8599
L
LC
V
OUT2P
DDA
OUT2P
10
11
12
13
14
15
16
17
18
V
PA
bead
15 nF
100 nF
2
non-I C-bus
mode
C
BOOT2P
ADS
LC
22 Ω
4.7 kΩ
10 kΩ
10 kΩ
PGND2
PGND2
MOD
CLIP
DIAG
SDA
BD modulation
setting
470 pF
470 pF
100 nF
V
PGND2
470 pF
P2
470 pF
V
P2
V
Pull-up
Pull-up
V
22 Ω
P2
C
BOOT2N
OUT2N
VSTAB2
DCP
LC
V
10 Ω
100 nF
15 nF
L
LC
OUT2N
220 nF
SCL
(2)
1 µF
SSM
(3)
100 nF
OSCIO
OSCSET
MASTER
MODE
39 kΩ
001aai810
Dual BTL mode (stereo) in non-I2C-bus mode with DC offset protection disabled; Spread spectrum
mode enabled BD modulation.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 41. Example application diagram for dual BTL in non-I2C-bus mode
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
41 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
bead
bead
bead
V
V
V
P1
P2
PA
100 µF
35 V
100 µF
35 V
V
P
1000 µF
35 V
PGND1
GND
PGND2
C
C
C
C
IN1P
IN1N
IN2P
IN2N
470 nF
470 nF
470 nF
470 nF
GNDD/HW
IN1P
IN1N
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
IN1P
IN1N
100 nF
V
DDD
220 nF
VSTAB1
OUT1N
IN2P
IN2N
IN2P
IN2N
L
LC
OUT1N
15 nF
C
ACGND
100 nF
10 Ω
C
LC
BOOT1N
ACGND
EN
100 nF
22 Ω
V
P1
100 nF
V
P1
(1)
470 pF
470 pF
enable
V
PGND1
470 pF
P1
470 pF
(1)
SEL_MUTE
SVRR
PGND1
PGND1
22 Ω
470 nF
47 µF
C
BOOT1P
OUT1P
OUT2P
BOOT2P
PGND2
LC
10 Ω
10 Ω
100 nF
15 nF
L
LC
AGND
OUT1P
100 nF
TDF8599
L
LC
V
DDA
OUT2P
10
11
12
13
14
15
16
17
18
V
PA
bead
15 nF
100 nF
R
ADS
2
I C-bus
C
ADS
LC
address select
22 Ω
≤ 33 kΩ
PGND2
MOD
CLIP
DIAG
SDA
stereo mode
setting
470 pF
470 pF
100 nF
V
PGND2
470 pF
P2
470 pF
10 kΩ
10 kΩ
V
P2
V
Pull-up
Pull-up
V
22 Ω
P2
C
BOOT2N
OUT2N
VSTAB2
DCP
LC
V
10 Ω
100 nF
15 nF
L
LC
OUT2N
connect
to µP
220 nF
SCL
SSM
(2)
(3)
100 nF
4.7 µF
OSCIO
OSCSET
MASTER
MODE
39 kΩ
001aai811
Dual BTL mode (stereo) in I2C-bus mode with DC offset protection enabled; Spread spectrum
mode disabled.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 42. Example application diagram for dual BTL in I2C-bus mode
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
42 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
bead
bead
bead
V
V
V
P1
P2
PA
100 µF
35 V
100 µF
35 V
V
P
1000 µF
35 V
PGND1
GND
PGND2
C
C
INP
470 nF
470 nF
GNDD/HW
IN1P
IN1N
36
35
34
33
32
31
30
29
28
1
2
INP
INN
100 nF
INN
V
DDD
220 nF
VSTAB1
OUT1N
IN2P
IN2N
3
L
LC
4
15 nF
C
ACGND
10 Ω
BOOT1N
ACGND
EN
5
100 nF
V
P1
100 nF
V
P1
(1)
470 pF
470 pF
6
enable
OUTN
V
PGND1
470 pF
P1
(1)
SEL_MUTE
PGND1
470 pF
7
100 nF
C
LC
PGND1
470 nF
47 µF
BOOT1P
OUT1P
OUT2P
SVRR
AGND
8
10 Ω
10 Ω
15 nF
22 Ω
L
LC
9
100 nF
TDF8599
L
LC
V
DDA
27
26
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
18
V
PA
bead
22 Ω
15 nF
R
ADS
2
I C-bus
BOOT2P
PGND2
ADS
address select
C
LC
100 nF
≥ 100 kΩ
10 kΩ
PGND2
MOD
CLIP
DIAG
SDA
parallel mode
setting
470 pF
470 pF
100 nF
OUTP
V
PGND2
470 pF
P2
V
P2
470 pF
V
V
Pull-up
Pull-up
V
P2
10 kΩ
BOOT2N
OUT2N
VSTAB2
DCP
10 Ω
15 nF
L
LC
connect
to µP
220 nF
SCL
SSM
fixed
frequency
(2)
(3)
4.7 µF
100 nF
OSCIO
OSCSET
MASTER
MODE
39 kΩ
001aai812
Single BTL mode (parallel) in I2C-bus mode with DC offset protection enabled; Spread spectrum
mode disabled.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
Fig 43. Example application diagram for a single BTL in I2C-bus mode
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
43 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
bead
bead
bead
V
V
V
P1
P2
PA
100 µF
35 V
100 µF
35 V
C
C
C
C
IN1P
IN1N
IN2P
IN2N
470 nF
470 nF
470 nF
470 nF
GNDD/HW
IN1P
IN1N
V
36
35
34
33
32
31
30
29
28
1
2
P
IN1P
IN1N
1000 µF
35 V
100 nF
PGND1
V
DDD
GND
PGND2
220 nF
VSTAB1
OUT1N
IN2P
IN2N
3
IN2P
IN2N
L
LC
OUT1N
100 nF
4
15 nF
C
ACGND
10 Ω
C
BOOT1N
ACGND
LC
5
100 nF
22 Ω
V
P1
V
(1)
P1
EN
470 pF
470 pF
6
enable
100 nF
PGND1
V
PGND1
470 pF
P1
470 pF
(1)
SEL_MUTE
7
PGND1
22 Ω
470 nF
C
BOOT1P
OUT1P
OUT2P
BOOT2P
PGND2
SVRR
AGND
LC
8
10 Ω
10 Ω
100 nF
15 nF
47 µF
L
LC
OUT1P
9
100 nF
bead
TDF8599
MASTER
L
LC
V
DDA
OUT2P
100 nF
27
26
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
18
V
PA
15 nF
R
ADS
2
C-bus
C
ADS
I
LC
address select
22 Ω
≤ 33 kΩ
10 kΩ
PGND2
470 pF
MOD
CLIP
DIAG
SDA
stereo mode
setting
470 pF
100 nF
V
PGND2
470 pF
P2
470 pF
V
P2
V
Pull-up
Pull-up
V
22 Ω
P2
10 kΩ
C
BOOT2N
OUT2N
VSTAB2
DCP
LC
V
10 Ω
100 nF
15 nF
L
LC
OUT2N
220 nF
SCL
1 µF
spread
spectrum
mode
SSM
DC offset
protection enabled
(3)
(2)
4.7 µF
100 nF
OSCIO
OSCSET
MASTER
MODE
20 kΩ
39 kΩ
C
470 nF
470 nF
INP
GNDD/HW
IN1P
IN1N
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
IN3P
IN3N
100 nF
V
DDD
C
INN
220 nF
VSTAB1
OUT1N
IN2P
IN2N
L
LC
15 nF
C
ACGND
10 Ω
BOOT1N
ACGND
100 nF
V
(1)
P1
V
P1
EN
470 pF
470 pF
100 nF
PGND1
OUT3N
V
PGND1
470 pF
P1
470 pF
(1)
SEL_MUTE
100 nF
C
LC
PGND1
470 nF
47 µF
BOOT1P
OUT1P
OUT2P
SVRR
AGND
10 Ω
10 Ω
15 nF
22 Ω
L
LC
100 nF
TDF8599
SLAVE
L
LC
V
DDA
27
26
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
18
V
PA
bead
22 Ω
15 nF
R
ADS
2
I
C-bus
address select
BOOT2P
PGND2
ADS
C
LC
100 nF
≥ 100 kΩ
10 kΩ
PGND2
470 pF
MOD
CLIP
DIAG
SDA
parallel mode
setting
470 pF
100 nF
OUT3P
V
PGND2
470 pF
P2
470 pF
V
P2
V
Pull-up
Pull-up
V
P2
10 kΩ
BOOT2N
OUT2N
VSTAB2
DCP
V
10 Ω
15 nF
L
LC
connect
to µP
220 nF
SCL
270 nF
10 nF
5.1 kΩ
SSM
phase lock
operation
(4)
DC offset
4.7 µF
protection enabled
(3)
OSCIO
OSCSET
SLAVE MODE
001aai813
I2C-bus mode: Dual BTL in Master mode, one BTLs in Slave mode; DC offset protection enabled.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.
(4) See Section 8.3.4 on page 10 for detailed information on PLL operation.
Fig 44. Master-slave example application diagram; dual BTL master and one BTL slave in
I2C-bus mode
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
44 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
15. Package outline
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-2
D
E
A
x
c
y
X
E
2
M
H
E
v
A
D
1
D
2
1
18
pin 1 index
Q
A
A
2
E
1
(A )
3
A
4
θ
L
p
detail X
36
19
z
M
w
b
p
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(2)
UNIT
mm
A
A
A
4
b
c
D
D
1
D
E
E
E
e
H
L
p
Q
v
w
x
y
Z
θ
2
3
p
2
1
2
E
max.
+0.08 0.38 0.32
−0.04 0.25 0.23
3.5
3.2
16.0 13.0 1.1 11.1 6.2 2.9
15.8 12.6 0.9 10.9 5.8 2.5
14.5 1.1 1.7
13.9 0.8 1.5
2.55
2.20
8°
0°
0.65
3.5
0.35
0.25 0.12 0.03 0.07
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
SOT851-2
04-05-04
Fig 45. Package outline SOT851-2 (HSOP36)
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
45 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height
SOT938-1
A
E
E
D
2
X
y
M
H
E
v
A
D
1
D
2
36
19
Q
E
A
2
1
A
pin index
(A )
3
A
1
A
4
θ
L
p
detail X
1
18
M
w
Z
b
p
e
y
Z
θ
0
5
10 mm
°
°
2.55
2.20
8
0
scale
0.1
DIMENSIONS (mm are the original dimensions)
A
max
(1)
(2)
(2)
UNIT
A
1
A
2
A
3
A
4
b
c
D
D
1
D
2
E
E
E
e
H
L
p
Q
v
w
p
1
2
E
0.3
0.1
3.3
3.0
0.1
0
0.38 0.32 16.0 13.0
0.25 0.23 15.8 12.6
1.1
0.9
11.1
10.9
6.2
5.8
2.9
2.5
14.5
13.9
1.1
0.8
1.5
1.4
mm
3.6
0.35
0.65
0.25 0.12
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
06-01-20
06-04-07
SOT938-1
Fig 46. Package outline SOT938-1 (HSOP36)
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
46 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
16. Handling information
In accordance with SNW-FQ-611-D. The number of the quality specification can be found
in the Quality Reference Handbook. The handbook can be ordered using the code
9398 510 63011.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
© NXP B.V. 2009. All rights reserved.
TDF8599_2
Product data sheet
Rev. 02 — 30 July 2009
47 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 47) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 23 and 24
Table 23. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 24. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 47.
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
48 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 47. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 25. Abbreviations
Abbreviation
BCDMOS
BTL
Description
Bipolar Complementary and double Diffused Metal-Oxide Semiconductor
Bridge-Tied Load
DCP
DC offset Protection
EMI
I2C
ElectroMagnetic Interference
Inter-Integrated Circuit
LSB
Least Significant Bit
Mµp
Master microprocessor
MSB
Most Significant Bit
NDMOST
OCP
N-type double Diffused Metal-Oxide Semiconductor Transistor
OverCurrent Protection
OTP
OverTemperature Protection
OverVoltage Protection
OVP
POR
Power-On Reset
PWM
SOI
Pulse-Width Modulation
Silicon On Insulator
TFP
Thermal Foldback Protection
UnderVoltage Protection
UVP
WP
Window Protection
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
49 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
19. Revision history
Table 26. Revision history
Document ID
TDF8599_2
Release date
20090730
Data sheet status
Change notice
Supersedes
Product data sheet
-
TDF8599_1
Modifications:
• Data sheet status changed from Objective data sheet to Product data sheet.
• Various minor textual inconsistencies in the data sheet corrected.
• Changed Section 8.2: Figure 4 on page 7.
• Changed Section 8.2: Table 4 on page 8.
• Changed Section 8.2: Table 5 on page 8.
• Changed Section 8.6.3: Figure 20 on page 21.
• Changed Section 8.6.3: Figure 21 on page 23.
• Changed Section 14.7: Figure 41 on page 41, Figure 42 on page 42, Figure 43 on page 43
and Figure 44 on page 44.
TDF8599_1
20081113
Product data sheet
-
-
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
50 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
20.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
20.3 Disclaimers
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
51 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
22. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. I2C-bus mode operation . . . . . . . . . . . . . . . . . . .8
Table 5. Non-I2C-bus mode operation . . . . . . . . . . . . . . .8
Table 6. Mode setting pin OSCIO . . . . . . . . . . . . . . . . . .8
Table 7. Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .11
Table 8. Operation mode selection with the MOD pin . .12
Table 9. Overview of protection types . . . . . . . . . . . . . .15
Table 10. Overview of TDF8599 protection circuits
Table 14. Instruction byte descriptions . . . . . . . . . . . . . . 26
Table 15. Phase shift bit settings . . . . . . . . . . . . . . . . . . 26
Table 16. Description of data bytes . . . . . . . . . . . . . . . . . 27
Table 17. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Thermal characteristics . . . . . . . . . . . . . . . . . . 28
Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . . 29
Table 20. Switching characteristics . . . . . . . . . . . . . . . . . 32
Table 21. Dynamic characteristics . . . . . . . . . . . . . . . . . 33
Table 22. Filter component values . . . . . . . . . . . . . . . . . 37
Table 23. SnPb eutectic process (from J-STD-020C) . . . 48
Table 24. Lead-free process (from J-STD-020C) . . . . . . 48
Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 50
and amplifier states . . . . . . . . . . . . . . . . . . . . .17
Table 11. Available data on pins DIAG and CLIP . . . . . .18
Table 12. Interpretation of DC load detection bits . . . . . .20
Table 13. TDF8599 address using an external resistor . .24
23. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 2. Heatsink up (top view) pin configuration
TDF8599TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Fig 3. Heatsink down (top view) pin configuration
Fig 28. Po as a function of VP in stereo mode with
THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Fig 29. Po as a function of VP in parallel mode with
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Fig 30. Po as a function of VP parallel mode with
THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Fig 31. THD + N as a function of output power with a
2 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Fig 32. THD + N as a function of output power with a
4 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Fig 33. THD + N as a function of frequency with a
2 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig 34. THD + N as a function of frequency with a
4 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig 35. Channel separation as a function of
TDF8599TD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Fig 4. Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Fig 5. Clock frequency as a function of Rosc . . . . . . . . . .9
Fig 6. Master and slave configuration . . . . . . . . . . . . . . .9
Fig 7. Spread spectrum mode . . . . . . . . . . . . . . . . . . . .10
Fig 8. Spread spectrum operation in Master mode . . . .10
Fig 9. Phase lock operation . . . . . . . . . . . . . . . . . . . . . .11
Fig 10. AD/BD modulation switching circuit . . . . . . . . . . .12
Fig 11. AD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 12. BD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 13. Master and slave operation with 1⁄2 p phase
shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 14. Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 15. DC offset protection and diagnostic output . . . . .16
Fig 16. Diagnostic output for short circuit conditions . . . .18
Fig 17. DC load detection circuit . . . . . . . . . . . . . . . . . . .19
Fig 18. DC load detection procedure . . . . . . . . . . . . . . . .19
Fig 19. DC load detection limits . . . . . . . . . . . . . . . . . . . .19
Fig 20. Recommended start-up sequence with DC load
detection enabled. . . . . . . . . . . . . . . . . . . . . . . . .21
Fig 21. Start-up and shutdown timing in I2C-bus mode
with DC load detection. . . . . . . . . . . . . . . . . . . . .23
Fig 22. Start-up and shutdown timing in non-I2C-bus
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 23. I2C-bus start and stop conditions. . . . . . . . . . . . .25
Fig 24. Data bits sent from Master microprocessor
(Mmp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Fig 25. I2C-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Fig 26. I2C-bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Fig 27. Po as a function of VP in stereo mode with
frequency with a 2 W load. . . . . . . . . . . . . . . . . . 39
Fig 36. Channel separation as a function of
frequency with a 4 W load. . . . . . . . . . . . . . . . . . 39
Fig 37. CMRR as a function of frequency . . . . . . . . . . . . 40
Fig 38. Gain as a function of frequency. . . . . . . . . . . . . . 40
Fig 39. Efficiency as a function of output power . . . . . . . 40
Fig 40. Power dissipation as a function of total output
power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Fig 41. Example application diagram for dual BTL in
non-I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . 41
Fig 42. Example application diagram for dual BTL in
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Fig 43. Example application diagram for a single BTL in
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Fig 44. Master-slave example application diagram; dual
BTL master and one BTL slave in I2C-bus mode 44
Fig 45. Package outline SOT851-2 (HSOP36) . . . . . . . . 45
Fig 46. Package outline SOT938-1 (HSOP36) . . . . . . . . 46
Fig 47. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
TDF8599_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 30 July 2009
52 of 53
TDF8599
NXP Semiconductors
I2C-bus controlled dual channel class-D power amplifier
24. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
13
Dynamic characteristics. . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
14
Application information . . . . . . . . . . . . . . . . . 34
Output power estimation (Stereo mode) . . . . 34
Output power estimation (Parallel mode) . . . . 36
Output current limiting . . . . . . . . . . . . . . . . . . 36
Speaker configuration and impedance. . . . . . 37
Heat sink requirements . . . . . . . . . . . . . . . . . 37
Curves measured in reference design . . . . . . 38
Typical application schematics. . . . . . . . . . . . 41
14.1
14.2
14.3
14.4
14.5
14.6
14.7
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 45
Handling information . . . . . . . . . . . . . . . . . . . 47
8
8.1
8.2
8.3
Functional description . . . . . . . . . . . . . . . . . . . 6
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pulse-width modulation frequency . . . . . . . . . . 8
Master and slave mode selection . . . . . . . . . . . 8
Spread spectrum mode (Master mode) . . . . . . 9
Frequency hopping (Master mode). . . . . . . . . 10
Phase lock operation (Slave mode) . . . . . . . . 10
Operation mode selection. . . . . . . . . . . . . . . . 11
Modulation mode . . . . . . . . . . . . . . . . . . . . . . 12
Phase staggering (Slave mode) . . . . . . . . . . . 13
Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal foldback . . . . . . . . . . . . . . . . . . . . . . 15
Overtemperature protection . . . . . . . . . . . . . . 15
Overcurrent protection . . . . . . . . . . . . . . . . . . 15
Window protection . . . . . . . . . . . . . . . . . . . . . 16
DC offset protection . . . . . . . . . . . . . . . . . . . . 16
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . 17
Overview of protection circuits and
17
Soldering of SMD packages . . . . . . . . . . . . . . 47
Introduction to soldering. . . . . . . . . . . . . . . . . 47
Wave and reflow soldering . . . . . . . . . . . . . . . 47
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 47
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 48
17.1
17.2
17.3
17.4
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.4.1
8.4.2
8.4.3
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
18
19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision history . . . . . . . . . . . . . . . . . . . . . . . 50
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 51
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51
20.1
20.2
20.3
20.4
21
22
23
24
Contact information . . . . . . . . . . . . . . . . . . . . 51
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
amplifier states . . . . . . . . . . . . . . . . . . . . . . . . 17
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . 18
Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 18
Load identification (I2C-bus mode only) . . . . . 19
DC load detection . . . . . . . . . . . . . . . . . . . . . . 19
Recommended start-up sequence with
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2
DC load detection enabled . . . . . . . . . . . . . . . 20
AC load detection . . . . . . . . . . . . . . . . . . . . . . 21
CLIP detection . . . . . . . . . . . . . . . . . . . . . . . . 22
Start-up and shutdown sequence. . . . . . . . . . 22
8.6.2.3
8.6.2.4
8.6.3
9
9.1
9.2
I2C-bus specification . . . . . . . . . . . . . . . . . . . . 24
Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 26
Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal characteristics. . . . . . . . . . . . . . . . . . 28
Static characteristics. . . . . . . . . . . . . . . . . . . . 29
Switching characteristics . . . . . . . . . . . . . . . . 32
11
12
12.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 July 2009
Document identifier: TDF8599_2
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